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8XC251SQ

型号：

8XC251SQ

描述：

高性能CHMOS微控制器[ HIGH-PERFORMANCE CHMOS MICROCONTROLLER ]

品牌：

INTEL[ INTEL ]

页数：

36 页

PDF大小：

409 K

下载PDF手册
PRELIMINARY  
8XC251SA/SB/SP/SQ  
HIGH-PERFORMANCE  
CHMOS MICROCONTROLLER  
Commercial/Express  
■ Real-time and Programmed Wait State  
Bus Operation  
■ User-selectable Configurations:  
— External Wait States (0-3 wait states)  
— Address Range & Memory Mapping  
— Page Mode  
®
■ Binary-code Compatible with MCS 51  
■ Pin Compatible with 44-pin PLCC and 40-  
pin PDIP MCS 51 Sockets  
■ 32 Programmable I/O Lines  
®
■ Register-based MCS 251 Architecture  
■ Seven Maskable Interrupt Sources  
with Four Programmable Priority  
Levels  
— 40-byte Register File  
— Registers Accessible as Bytes, Words,  
or Double Words  
■ Three Flexible 16-bit Timer/counters  
■ Hardware Watchdog Timer  
■ Programmable Counter Array  
— High-speed Output  
■ Enriched MCS 51 Instruction Set  
— 16-bit and 32-bit Arithmetic and Logic  
Instructions  
— Compare and Conditional Jump  
Instructions  
— Compare/Capture Operation  
— Pulse Width Modulator  
— Expanded Set of Move Instructions  
— Watchdog Timer  
■ Linear Addressing  
■ Programmable Serial I/O Port  
— Framing Error Detection  
■ 256-Kbyte Expanded External Code/Data  
Memory Space  
■ ROM/OTPROM/EPROM Options:  
16 Kbytes (SB/SQ), 8 Kbytes (SA/SP), or  
without ROM/OTPROM/EPROM  
— Automatic Address Recognition  
■ High-performance CHMOS Technology  
■ Static Standby to 16-MHz Operation  
■ 16-bit Internal Code Fetch  
■ Complete System Development  
■ 64-Kbyte Extended Stack Space  
Support  
■ On-chip Data RAM Options:  
— Compatible with Existing Tools  
1-Kbyte (SA/SB) or 512-Byte (SP/SQ)  
— New MCS 251 Tools Available:  
■ 8-bit, 2-clock External Code Fetch in  
Compiler, Assembler, Debugger, ICE  
Page Mode  
■ Fast MCS 251 Instruction Pipeline  
■ Package Options (PDIP, PLCC, and  
Ceramic DIP)  
A member of the Intel family of 8-bit MCS 251 microcontrollers, the 8XC251SA/SB/SP/SQ is binary-code  
compatible with MCS 51 microcontrollers and pin compatible with 40-pin PDIP and 44-pin PLCC MCS 51  
microcontrollers. MCS 251 microcontrollers feature an enriched instruction set, linear addressing, and  
efficient C-language support. The 8XC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip RAM and is  
available with 8 Kbytes or 16 Kbytes of on-chip ROM/OTPROM/EPROM, or without ROM/OTPROM/EPROM.  
A variety of features can be selected by new user-programmable configurations.  
COPYRIGHT © INTEL CORPORATION, 1996  
May 1996  
Order Number: 272783-003  
Information in this document is provided in connection with Intel products. No license, express or implied, by  
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in  
Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel  
disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or  
warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright  
or other intellectual property right. Intel products are not intended for use in medical, life saving, or life  
sustaining applications.  
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.  
*Third-party brands and names are the property of their respective owners.  
Copies of documents which have an ordering number and are referenced in this document, or other Intel  
literature, may be obtained from:  
Intel Corporation  
P.O. Box 7641  
Mt. Prospect IL 60056-764  
or call 1-800-548-4725  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
I/O Ports and  
Peripheral Signals  
System Bus and I/O Ports  
P0.7:0  
P1.7:0  
P2.7:0  
P3.7:0  
Code  
OTPROM/ROM  
8 Kbytes  
or  
Data RAM  
512 Bytes  
or  
Port 0  
Drivers  
Port 2  
Drivers  
Port 1  
Drivers  
Port 3  
Drivers  
1024 Bytes  
16 Kbytes  
Memory Data (16)  
Watchdog  
Timer  
Memory Address (16)  
Peripheral  
Interface  
Bus Interface  
Timer/  
Counters  
Code Bus (16)  
Code Address (24)  
Interrupt  
Handler  
Instruction Sequencer  
PCA  
SRC1 (8)  
SRC2 (8)  
Serial I/O  
Clock  
&
Reset  
Data  
Register  
File  
Memory  
Interface  
ALU  
Peripherals  
DST (16)  
®
MCS 251 Microcontroller Core  
Clock & Reset  
8XC251SA/SB/SP/SQ Microcontroller  
A4214-01  
Figure 1. 8XC251SA/SB/SP/SQ Block Diagram  
PRELIMINARY  
3
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
1.0 NOMENCLATURE  
X
XX  
8
X
X
XXXXX XX  
A2815-01  
Figure 2. The 8XC251SA/SB/SP/SQ Family Nomenclature  
Table 1. Description of Product Nomenclature  
Parameter  
Options  
Description  
Temperature and Burn-in  
Options  
no mark  
Commercial operating temperature range (0°C to 70°C) with  
Intel standard burn-in.  
T
Express operating temperature range (-40°C to 85°C) with  
Intel standard burn-in.  
Packaging Options  
N
P
44-pin Plastic Leaded Chip Carrier (PLCC)  
40-pin Plastic Dual In-line Package (PDIP)  
40-pin Ceramic Dual In-line Package (Ceramic DIP)  
Without ROM/OTPROM/EPROM  
ROM  
C
Program Memory Options  
0
3
7
User programmable OTPROM/EPROM  
CHMOS  
Process Information  
Product Family  
C
251  
SA  
SB  
8-bit control architecture  
Device Memory Options  
1-Kbyte RAM/8-Kbyte ROM/OTPROM/EPROM  
1-Kbyte RAM/16-Kbyte ROM/OTPROM/EPROM or without  
ROM/OTPROM/EPROM  
SP  
SQ  
512-byte RAM/8-Kbyte ROM/OTPROM/EPROM  
512-byte RAM/16-Kbyte ROM/OTPROM/EPROM or without  
ROM/OTPROM/EPROM  
Device Speed  
16  
External clock frequency  
4
PRELIMINARY  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
Table 2 lists the proliferation options. See Figure 2 for the 8XC251SA/SB/SP/SQ family nomenclature.  
.
Table 2. Proliferation Options  
8XC251SA/SB/SP/SQ  
(0 – 16 MHz; 5 V ±10%)  
80C251SB16  
80C251SQ16  
83C251SA16  
83C251SB16  
83C251SP16  
83C251SQ16  
87C251SA16  
87C251SB16  
87C251SP16  
87C251SQ16  
CPU-only  
CPU-only  
ROM  
ROM  
ROM  
ROM  
OTPROM/EPROM  
OTPROM/EPROM  
OTPROM/EPROM  
OTPROM/EPROM  
Table 3 lists the 8XC251SA/SB/SP/SQ packages.  
Table 3. Package Information  
Definition Temperature  
44 ld. PLCC  
Pkg.  
N
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
-40°C to +85°C  
-40°C to +85°C  
P
40 ld. Plastic DIP  
40 ld. Ceramic DIP  
44 ld. PLCC  
C
TN  
TP  
40 ld. Plastic DIP  
PRELIMINARY  
5
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
2.0 PINOUT  
P1.5 / CEX2  
P1.6 / CEX3 / WAIT#  
P1.7 / CEX4 / A17 / WCLK  
RST  
7
8
9
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
AD4 / P0.4  
AD5 / P0.5  
AD6 / P0.6  
AD7 / P0.7  
8XC251SA  
8XC251SB  
8XC251SP  
8XC251SQ  
10  
11  
12  
13  
14  
15  
16  
17  
P3.0 / RXD  
EA# / V  
PP  
V
V
CC2  
SS2  
P3.1 / TXD  
P3.2 / INT0#  
P3.3 / INT1#  
P3.4 / T0  
ALE / PROG#  
PSEN#  
A15 / P2.7  
A14 / P2.6  
A13 / P2.5  
View of component as  
mounted on PC board  
P3.5 / T1  
A4205-02  
Figure 3. 8XC251SA/SB/SP/SQ 44-pin PLCC Package  
6
PRELIMINARY  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
V
P1.0 / T2  
P1.1 / T2EX  
P1.2 / ECI  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
1
CC  
AD0 / P0.0  
AD1 / P0.1  
AD2 / P0.2  
AD3 / P0.3  
AD4 / P0.4  
AD5 / P0.5  
AD6 / P0.6  
AD7 / P0.7  
2
3
P1.3 / CEX0  
P1.4 / CEX1  
P1.5 / CEX2  
P1.6 / CEX3 / WAIT#  
P1.7 / CEX4 / A17 / WCLK  
RST  
4
5
8XC251SA  
8XC251SB  
8XC251SP  
8XC251SQ  
6
7
8
9
V
EA# /  
P3.0 / RXD  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
PP  
P3.1 / TXD  
ALE / PROG#  
PSEN#  
P3.2 / INT0#  
P3.3 / INT1#  
P3.4 / T0  
A15 / P2.7  
A14 / P2.6  
A13 / P2.5  
A12 / P2.4  
A11 / P2.3  
A10 / P2.2  
A9 / P2.1  
View of  
component  
as mounted  
on PC board  
P3.5 / T1  
P3.6 / WR#  
P3.7 / RD# / A16  
XTAL2  
XTAL1  
V
A8 / P2.0  
SS  
A4206-03  
Figure 4. 8XC251SA/SB/SP/SQ 40-pin PDIP and Ceramic DIP Packages  
PRELIMINARY  
7
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
Table 4. 8XC251SA/SB/SP/SQ Pin Assignment  
PLCC  
1
DIP  
Name  
PLCC  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
DIP  
Name  
VSS1  
VSS2  
2
1
2
P1.0/T2  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
A8/P2.0  
A9/P2.1  
3
P1.1/T2EX  
P1.2/ECI  
4
3
A10/P2.2  
A11/P2.3  
A12/P2.4  
A13/P2.5  
A14/P2.6  
A15/P2.7  
PSEN#  
5
4
P1.3/CEX0  
P1.4/CEX1  
P1.5/CEX2  
P1.6/CEX3/WAIT#  
P1.7/CEX4/A17/WCLK  
RST  
6
5
7
6
8
7
9
8
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
9
10  
P3.0/RXD  
VCC2  
ALE/PROG#  
VSS2  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
P3.1/TXD  
P3.2/INT0#  
P3.3/INT1#  
P3.4/T0  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
EA#/VPP  
AD7/P0.7  
AD6/P0.6  
AD5/P0.5  
AD4/P0.4  
AD3/P0.3  
AD2/P0.2  
AD1/P0.1  
AD0/P0.0  
VCC  
P3.5/T1  
P3.6/WR#  
P3.7/RD#/A16  
XTAL2  
XTAL1  
VSS  
8
PRELIMINARY  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
Table 5. 8XC251SA/SB/SP/SQ PLCC/DIP Pin Assignments Arranged by Functional Category  
Address & Data  
Name PLCC  
AD0/P0.0  
Input/Output  
Name PLCC  
DIP  
39  
38  
37  
36  
35  
34  
33  
32  
21  
22  
23  
24  
25  
26  
27  
28  
17  
8
DIP  
1
43  
42  
41  
40  
39  
38  
37  
36  
24  
25  
26  
27  
28  
29  
30  
31  
19  
9
P1.0/T2  
2
3
AD1/P0.1  
AD2/P0.2  
AD3/P0.3  
AD4/P0.4  
AD5/P0.5  
AD6/P0.6  
AD7/P0.7  
A8/P2.0  
P1.1/T2EX  
P1.2/ECI  
2
4
3
P1.3/CEX0  
P1.4/CEX1  
P1.5/CEX2  
P1.6/CEX3/WAIT#  
P1.7/CEX4/A17/WCLK  
P3.0/RXD  
5
4
6
5
7
6
8
7
9
8
11  
13  
16  
17  
10  
11  
14  
15  
A9/P2.1  
P3.1/TXD  
A10/P2.2  
P3.4/T0  
A11/P2.3  
P3.5/T1  
A12/P2.4  
A13/P2.5  
Power & Ground  
Name PLCC  
A14/P2.6  
DIP  
A15/P2.7  
VCC  
44  
12  
40  
P3.7/RD#/A16  
P1.7/CEX4/A17/WCLK  
VCC2  
VSS  
22  
20  
31  
VSS1  
1
VSS2  
23, 34  
35  
Processor Control  
Name PLCC  
EA#/VPP  
DIP  
12  
13  
31  
9
P3.2/INT0#  
P3.3/INT1#  
EA#/VPP  
RST  
14  
15  
35  
10  
21  
20  
Bus Control & Status  
Name  
PLCC  
18  
DIP  
P3.6/WR#  
P3.7/RD#/A16  
ALE/PROG#  
PSEN#  
16  
19  
17  
30  
29  
XTAL1  
18  
19  
33  
XTAL2  
32  
PRELIMINARY  
9
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
3.0 SIGNALS  
Table 6. Signal Descriptions  
Signal  
Alternate  
Function  
Type  
Description  
Name  
A17  
O
18th Address Bit (A17). Output to memory as 18th external address  
P1.7/CEX4/  
bit (A17) in extended bus applications, depending on the values of bits WCLK  
RD0 and RD1 in configuration byte UCONFIG0 (see Chapter 4,  
“Device Configuration,” of the 8XC251SA/SB/SP/SQ Embedded  
Microcontroller User’s Manual). See also RD# and PSEN#.  
A16  
O
O
Address Line 16. See RD#.  
RD#  
A15:8†  
AD7:0†  
Address Lines. Upper address lines for the external bus.  
P2.7:0  
P0.7:0  
I/O  
Address/Data Lines. Multiplexed lower address lines and data lines  
for external memory.  
ALE  
O
Address Latch Enable. ALE signals the start of an external bus cycle PROG#  
and indicates that valid address information is available on lines A15:8  
and AD7:0. An external latch can use ALE to demultiplex the address  
from the address/data bus.  
CEX4:0  
EA#  
I/O  
I
Programmable Counter Array (PCA) Input/Output Pins. These are P1.6:3  
input signals for the PCA capture mode and output signals for the PCA P1.7/A17/  
compare mode and PCA PWM mode.  
WAIT#  
External Access. Directs program memory accesses to on-chip or off- VPP  
chip code memory. For EA# = 0, all program memory accesses are off-  
chip. For EA# = 1, an access is to on-chip ROM/OTPROM/EPROM if  
the address is within the range of the on-chip  
ROM/OTPROM/EPROM; otherwise the access is off-chip. The value  
of EA# is latched at reset. For devices without on-chip  
ROM/OTPROM/EPROM, EA# must be strapped to ground.  
ECI  
I
I
PCA External Clock Input. External clock input to the 16-bit PCA  
P1.2  
timer.  
INT1:0#  
External Interrupts 0 and 1. These inputs set bits IE1:0 in the TCON P3.3:2  
register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by  
a falling edge on INT1#/INT0#. If bits INT1:0 are clear, bits IE1:0 are  
set by a low level on INT1:0#.  
PROG#  
P0.7:0  
I
Programming Pulse. The programming pulse is applied to this pin for ALE  
programming the on-chip OTPROM.  
I/O  
I/O  
Port 0. This is an 8-bit, open-drain, bidirectional I/O port.  
AD7:0  
P1.0  
Port 1. This is an 8-bit, bidirectional I/O port with internal pullups.  
T2  
P1.1  
T2EX  
P1.2  
ECI  
P1.7:3  
CEX3:0  
CEX4/A17/  
WAIT#/  
WCLK  
P2.7:0  
I/O  
Port 2. This is an 8-bit, bidirectional I/O port with internal pullups.  
A15:8  
†
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (com-  
patible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page-  
mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits  
(A15:8) and the data (D7:0).  
10  
PRELIMINARY  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
Table 6. Signal Descriptions (Continued)  
Alternate  
Signal  
Name  
Type  
Description  
Function  
P3.0  
P3.1  
I/O  
Port 3. This is an 8-bit, bidirectional I/O port with internal pullups.  
RXD  
TXD  
P3.3:2  
P3.5:4  
P3.6  
INT1:0#  
T1:0  
WR#  
P3.7  
RD#/A16  
PSEN#  
O
O
I
Program Store Enable. Read signal output. This output is asserted  
for a memory address range that depends on bits RD0 and RD1 in  
configuration byte UCONFIG0 (see RD# and Chapter 4, “Device Con-  
figuration,” in the 8XC251SA/SB/SP/SQ Embedded Microcontroller  
User’s Manual).  
—
RD#  
Read or 17th Address Bit (A16). Read signal output to external data P3.7/A16  
memory or 17th external address bit (A16), depending on the values of  
bits RD0 and RD1 in configuration byte UCONFIG0. (See PSEN# and  
Chapter 4, “Device Configuration,” in the 8XC251SA/SB/SP/SQ  
Embedded Microcontroller User’s Manual).  
RST  
Reset. Reset input to the chip. Holding this pin high for 64 oscillator  
periods while the oscillator is running resets the device. The port pins  
are driven to their reset conditions when a voltage greater than VIH1 is  
applied, whether or not the oscillator is running. This pin has an inter-  
nal pulldown resistor, which allows the device to be reset by connect-  
—
ing a capacitor between this pin and VCC  
.
Asserting RST when the chip is in idle mode or powerdown mode  
returns the chip to normal operation.  
RXD  
T1:0  
T2  
I/O  
I
Receive Serial Data. RXD sends and receives data in serial I/O mode P3.0  
0 and receives data in serial I/O modes 1, 2, and 3.  
Timer 1:0 External Clock Inputs. When timer 1:0 operates as a  
counter, a falling edge on the T1:0 pin increments the count.  
P3.5:4  
I/O  
Timer 2 Clock Input/Output. For the timer 2 capture mode, this signal P1.0  
is the external clock input. For the clock-out mode, it is the timer 2  
clock output.  
T2EX  
TXD  
I
Timer 2 External Input. In timer 2 capture mode, a falling edge ini-  
tiates a capture of the timer 2 registers. In auto-reload mode, a falling  
edge causes the timer 2 registers to be reloaded. In the up-down  
counter mode, this signal determines the count direction: 1 = up, 0 =  
down.  
P1.1  
O
Transmit Serial Data. TXD outputs the shift clock in serial I/O mode 0 P3.1  
and transmits serial data in serial I/O modes 1, 2, and 3.  
VCC  
PWR Supply Voltage. Connect this pin to the +5V supply voltage.  
—
—
VCC2  
PWR Secondary Supply Voltage 2. This supply voltage connection is pro-  
vided to reduce power supply noise. Connection of this pin to the +5V  
supply voltage is recommended. However, when using the 8XC251SB  
as a pin-for-pin replacement for the 8XC51FX, VSS2 can be uncon-  
nected without loss of compatibility. (Not available on DIP)  
†
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (com-  
patible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page-  
mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits  
(A15:8) and the data (D7:0).  
PRELIMINARY  
11  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
Table 6. Signal Descriptions (Continued)  
Signal  
Alternate  
Function  
Type  
Description  
Name  
VPP  
I
Programming Supply Voltage. The programming supply voltage is  
applied to this pin for programming the on-chip OTPROM/EPROM.  
EA#  
VSS  
GND Circuit Ground. Connect this pin to ground.  
—
—
VSS1  
GND Secondary Ground. This ground is provided to reduce ground bounce  
and improve power supply bypassing. Connection of this pin to ground  
is recommended. However, when using the 8XC251SA/SB/SP/SQ as  
a pin-for-pin replacement for the 8XC51BH, VSS1 can be unconnected  
without loss of compatibility. (Not available on DIP)  
VSS2  
GND Secondary Ground 2. This ground is provided to reduce ground  
bounce and improve power supply bypassing. Connection of this pin to  
ground is recommended. However, when using the 8XC251SB as a  
pin-for-pin replacement for the 8XC51FX, VSS2 can be unconnected  
without loss of compatibility. (Not available on DIP)  
—
WAIT#  
I
Real-time Wait State Input. The real-time WAIT# input is enabled by P1.6/CEX3  
writing a logical ‘1’ to the WCON.0 (RTWE) bit at S:A7H. During bus  
cycles, the external memory system can signal ‘system ready’ to the  
microcontroller in real time by controlling the WAIT# input signal on the  
port 1.6 input.  
WCLK  
O
Wait Clock Output. The real-time WCLK output is driven at port 1.7  
(WCLK) by writing a logical ‘1’ to the WCON.1 (RTWCE) bit at S:A7H.  
When enabled, the WCLK output produces a square wave signal with  
a period of one-half the oscillator frequency.  
P1.7/CEX4/  
A17  
WR#  
O
I
Write. Write signal output to external memory.  
P3.6  
—
XTAL1  
Input to the On-chip, Inverting, Oscillator Amplifier. To use the  
internal oscillator, a crystal/resonator circuit is connected to this pin. If  
an external oscillator is used, its output is connected to this pin. XTAL1  
is the clock source for internal timing.  
XTAL2  
O
Output of the On-chip, Inverting, Oscillator Amplifier. To use the  
internal oscillator, a crystal/resonator circuit is connected to this pin. If  
an external oscillator is used, leave XTAL2 unconnected.  
—
†
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (com-  
patible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page-  
mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits  
(A15:8) and the data (D7:0).  
12  
PRELIMINARY  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
Table 7. Memory Signal Selections (RD1:0)  
P1.7/CEX/  
A17/WCLK  
RD1:0  
P3.7/RD#/A16  
PSEN#  
WR#  
Features  
0
0
1
0
1
0
A17  
A16  
Asserted for  
all addresses all memory locations  
Asserted for writes to 256-Kbyte external  
memory  
P1.7/CEX4/  
WCLK  
A16  
Asserted for Asserted for writes to 128-Kbyte external  
all addresses all memory locations memory  
P1.7/CEX4/  
WCLK  
P3.7 only  
Asserted for Asserted for writes to 64-Kbyte external  
all addresses all memory locations  
memory. One  
additional port pin.  
1
1
P1.7/CEX4/  
WCLK  
RD# asserted  
for addresses  
≤ 7F:FFFFH  
Asserted for  
≥ 80:0000H  
Asserted only for  
writes to MCS 51  
microcontroller data  
memory locations.  
64-Kbyte external  
memory. Compatible  
with MCS 51 micro-  
controllers.  
PRELIMINARY  
13  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
4.0 ADDRESS MAP  
Table 8. 8XC251SA/SB/SP/SQ Address Map  
Internal  
Description  
Address)  
Notes  
1, 3, 10  
3, 4, 5  
3
FF:FFFFH  
FF:4000H  
External Memory except the top eight bytes (FF:FFF8H–FF:FFFFH) which are  
reserved for the configuration array.  
FF:3FFFH  
FF:0000H  
External memory or on-chip nonvolatile memory (8Kbytes FF:0000H - FF:1FFFH,  
16Kbytes FF:0000H - FF:3FFFH).  
FE:FFFFH  
FE:0000H  
External Memory  
FD:FFFFH  
02:0000H  
Reserved  
6
01:FFFFH  
01:0000H  
External Memory  
3
00:FFFFH  
00:E000H  
External memory or with configuration bit EMAP# = 0, addresses in this range  
access on-chip code memory in region FF: (16 Kbyte devices only).  
5, 7  
7
00:DFFFH  
00:0420H  
External Memory  
00:041FH  
00:0080H  
On-chip RAM (512 bytes 00:0020H - 00:021FH, 1024 bytes 00:0020H -  
00:041FH)  
7
00:007FH  
00:0020H  
On-chip RAM  
8
00:001FH  
00:0000H  
Storage for R0–R7 of Register File  
2, 9  
NOTES:  
1. 18 address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration).  
2. The special function registers (SFRs) and the register file have separate internal address spaces.  
3. Data in this area is accessible by indirect addressing only.  
4. Devices reset into internal or external starting locations depending on the state of EA# and configura-  
tion byte information See EA#. See also UCONFIG1:0 bit definitions in the 8XC251SA/SB/SP/SQ  
Embedded Microcontroller User’s Manual.  
5. The 16-Kbyte ROM/OTPROM/EPROM devices allow internal locations FF:2000H–FF:3FFFH to map  
into region 00:. In this case, if EA# = 1, a data read to 00:E000H–00:FFFFH is redirected to internal  
ROM/OTPROM/EPROM (see bit 1 in UCONFIG0). This is not available for 8-Kbyte  
ROM/OTPROM/EPROM devices.  
6. This reserved area returns indeterminate values.  
7. Data is accessible by direct and indirect addressing.  
8. Data is accessible by direct, indirect, and bit addressing.  
9. Data is accessible by direct, indirect, and register addressing.  
10. Eight addresses at the top of all external memory maps are reserved for current and future device  
configuration byte information.  
14  
PRELIMINARY  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
5.0 ELECTRICAL CHARACTERISTICS  
ABSOLUTE MAXIMUM RATINGS  
NOTICE: This document contains preliminary  
information on new products in production. The  
specifications are subject to change without notice.  
Verify with your local Intel sales office that you  
have the latest datasheet before finalizing a  
design.  
Storage Temperature ................................... -65°C to +150°C  
Voltage on EA#/VPP Pin to VSS ......................... 0 V to +13.0 V  
Voltage on Any other Pin to VSS ..................... -0.5 V to +6.5 V  
IOL per I/O Pin................................................................. 15 mA  
Power Dissipation .......................................................... 1.5 W  
† WARNING: Stressing the device beyond the  
“Absolute Maximum Ratings” may cause perma-  
nent damage. These are stress ratings only. Oper-  
ation beyond the “Operating Conditions” is not  
recommended and extended exposure beyond the  
“Operating Conditions” may affect device  
reliability.  
OPERATING CONDITIONS†  
TA (Ambient Temperature Under Bias):  
Commercial ................................................. 0°C to +70°C  
Express .................................................... -40°C to +85°C  
V
CC (Digital Supply Voltage) .............................. 4.5 V to 5.5 V  
VSS ..................................................................................... 0 V  
NOTE  
Maximum power dissipation is  
based on package heat-transfer  
limitations, not device power  
consumption.  
PRELIMINARY  
15  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
5.1 D.C. Characteristics  
Parameter values apply to all devices unless otherwise indicated.  
Table 9. DC Characteristics at VCC = 4.5 – 5.5 V  
Symbol  
Parameter  
Min  
Typical  
Max  
Units  
Test Conditions  
VIL  
Input Low Voltage  
(except EA#)  
-0.5  
0.2VCC – 0.1  
V
VIL1  
VIH  
Input Low Voltage  
(EA#)  
0
0.2VCC – 0.3  
VCC + 0.5  
V
V
V
V
Input High Voltage  
(except XTAL1, RST)  
0.2VCC + 0.9  
0.7VCC  
VIH1  
VOL  
Input High Voltage  
(XTAL1, RST)  
VCC + 0.5  
Output Low Voltage  
(Port 1, 2, 3)  
0.3  
0.45  
1.0  
IOL = 100 µA  
IOL = 1.6 mA  
IOL = 3.5 mA  
(Note 1, Note 2)  
VOL1  
Output Low Voltage  
(Port 0, ALE, PSEN#)  
0.3  
0.45  
1.0  
V
V
IOL = 200 µA  
IOL = 3.2 mA  
IOL = 7.0 mA  
(Note 1, Note 2)  
VOH  
Output High Voltage  
(Port 1, 2, 3, ALE,  
PSEN#)  
VCC – 0.3  
VCC – 0.7  
VCC – 1.5  
IOH = -10 µA  
IOH = -30 µA  
IOH = -60 µA  
(Note 3)  
NOTES:  
1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows:  
Maximum IOL per port pin: 10 mA  
Maximum IOL per 8-bit port:  
port 0  
ports 1–3  
26 mA  
15 mA  
Maximum Total IOL for  
all output pins  
71 mA  
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed  
to sink current greater than the listed test conditions.  
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level  
outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into  
the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive  
loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to  
qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic.  
3. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specifica-  
tion when the address lines are stabilizing.  
4. Typical values are obtained using VCC = 5.0, TA = 25°C and are not guaranteed.  
16  
PRELIMINARY  
 
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
Table 9. DC Characteristics at VCC = 4.5 – 5.5 V (Continued)  
Symbol  
Parameter  
Min  
Typical  
Max  
Units  
Test Conditions  
VOH1  
Output High Voltage  
(Port 0 in External  
Address)  
V
CC – 0.3  
V
I
OH = -200 µA  
IOH = -3.2 mA  
IOH = -7.0 mA  
VCC – 0.7  
VCC – 1.5  
VOH2  
Output High Voltage  
(Port 2 in External  
Address during Page  
Mode)  
V
CC – 0.3  
V
IOH = -200 µA  
IOH = -3.2 mA  
IOH = -7.0 mA  
VCC – 0.7  
VCC – 1.5  
IIL  
ILI  
ITL  
Logical 0 Input Cur-  
rent (Port 1, 2, 3)  
-50  
+/-10  
-650  
µA  
µA  
µA  
VIN = 0.45 V  
0.45 < VIN < VCC  
VIN = 2.0 V  
Input Leakage Cur-  
rent (Port 0)  
Logical 1-to-0 Transi-  
tion Current (Port 1,  
2, 3)  
RRST  
CIO  
RST Pulldown Resis-  
tor  
40  
225  
kΩ  
Pin Capacitance  
10  
pF  
FOSC = 16 MHz  
TA = 25 °C  
(Note 4)  
IPD  
Powerdown Current  
Idle Mode Current  
Operating Current  
10  
20  
15  
80  
µA  
mA  
mA  
(Note 4)  
IDL  
12  
FOSC = 16 MHz  
FOSC = 16 MHz  
(Note 4)  
ICC  
45  
(Note 4)  
NOTES:  
1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows:  
Maximum IOL per port pin: 10 mA  
Maximum IOL per 8-bit port:  
port 0  
ports 1–3  
26 mA  
15 mA  
Maximum Total IOL for  
all output pins  
71 mA  
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed  
to sink current greater than the listed test conditions.  
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level  
outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into  
the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive  
loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to  
qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic.  
3. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specifica-  
tion when the address lines are stabilizing.  
4. Typical values are obtained using VCC = 5.0, TA = 25°C and are not guaranteed.  
PRELIMINARY  
17  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
VCC  
IPD  
VCC  
P0  
VCC  
EA#  
RST  
8XC251SA  
8XC251SB  
8XC251SP  
8XC251SQ  
(NC)  
XTAL2  
XTAL1  
VSS  
All other 8XC251SA/SB/SP/SQ pins are unconnected.  
A4208-01  
Figure 5. IPD Test Condition, Powerdown Mode, VCC = 2.0 – 5.5V  
70  
60  
50  
40  
30  
20  
10  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16  
Frequency at XTAL (MHz)  
A4400-01  
Figure 6. ICC vs. Frequency (Mhz)  
18  
PRELIMINARY  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
5.2 Definition of AC Symbols  
Table 10. AC Timing Symbol Definitions  
Signals  
Conditions  
A
D
L
Address  
Data In  
ALE  
H
L
High  
Low  
V
X
Z
Valid  
Q
R
W
Data Out  
RD#/PSEN#  
WR#  
No Longer Valid  
Floating  
5.3 A.C. Characteristics  
Test Conditions: Capacitive load on all pins = 50 pF.  
Table 11 lists AC timing parameters for the  
8XC251SA/SB/SP/SQ with no wait states. External  
wait states can be added by extending  
PSEN#/RD#/WR# and/or by extending ALE. In the  
table, Notes 3 and 5 mark parameters affected by an  
ALE wait state, and Notes 4 and 5 mark parameters  
affected by a PSEN#/RD#/WR# wait state.  
Figures 8–10 show the bus cycles with the timing  
parameters.  
Table 11. AC Characteristics  
@ Max Fosc (1)  
Min Max  
N/A N/A  
N/A  
Fosc Variable  
Min Max  
16  
Symbol  
Parameter  
Units  
FOSC  
TOSC  
XTAL1 Frequency  
1/FOSC  
0
MHz  
ns  
N/A  
83.3  
62.5  
@ 12 MHz  
@ 16 MHz  
TLHLL  
ALE Pulse Width  
@ 12 MHz  
ns  
73.3  
52.5  
(1+2M)  
TOSC – 10  
(3)  
@ 16 MHz  
TAVLL  
Address Valid to ALE Low  
@ 12 MHz  
ns  
58.3  
37.5  
(1+2M)  
(3)  
T
OSC – 25  
@ 16 MHz  
TLLAX  
Address Hold after ALE Low  
@ 12 MHz  
ns  
15  
15  
15  
@ 16 MHz  
NOTES:  
1. 16 MHz.  
2. Specifications for PSEN# are identical to those for RD#.  
3. In the formula, M=Number of wait states (0 or 1) for ALE.  
4. In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#.  
5. “Typical” specifications are untested and not guaranteed.  
PRELIMINARY  
19  
 
 
 
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
Table 11. AC Characteristics (Continued)  
@ Max Fosc (1)  
Fosc Variable  
Symbol  
Parameter  
Units  
Min  
Max  
Min  
Max  
TRLRH (2) RD# or PSEN# Pulse Width  
ns  
146.6  
105  
2(1+N)  
@ 12 MHz  
@ 16 MHz  
(4)  
T
OSC – 20  
TWLWH  
WR# Pulse Width  
@ 12 MHz  
ns  
146.6  
105  
2(1+N)  
TOSC – 20  
(4)  
@ 16 MHz  
TLLRL (2) ALE Low to RD# or PSEN# Low  
ns  
58.3  
37.5  
@ 12 MHz  
@ 16 MHz  
TOSC – 25  
TLHAX  
ALE High to Address Hold  
@ 12 MHz  
ns  
83.3  
62.5  
(1+2M)TOSC  
(3)  
@ 16 MHz  
T
RLDV (2) RD#/PSEN# Low to valid Data/Instruction In  
ns  
(4)  
106.6  
65  
2(1+N)  
Tosc – 60  
@ 12 MHz  
@ 16 MHz  
TRHDX (2) Data/Instruction Hold Time. Occurs after  
RD#/PSEN# are exerted to VOH  
0
0
ns  
ns  
TRLAZ (2) RD#/PSEN# Low to Address Float  
Typ.=0  
(5)  
2
Typ. = 0  
(5)  
2
TRHDZ1  
Instruction Float after RD#/PSEN# High  
commercial @ 12 MHz and 16 MHz  
express @ 12 MHz and 16 MHz  
ns  
Typ.=2 18  
Typ.=25  
Typ.=25  
(5)  
18  
10  
5
Typ.=2  
5
10  
(5)  
TRHDZ2  
TRHLH1  
TRHLH2  
Data Float after RD#/PSEN# High  
@ 12 MHz  
ns  
ns  
ns  
156.6  
115  
2Tosc – 10  
@ 16 MHz  
RD#/PSEN# High to ALE High (Instruction)  
10  
10  
@ 12 MHz  
@ 16 MHz  
10  
RD#/PSEN# High to ALE High (Data)  
@ 12 MHz  
156.6  
115  
2Tosc - 10  
@ 16 MHz  
TWHLH  
WR# High to ALE High  
@ 12 MHz  
ns  
171.6  
130  
2Tosc + 5  
@ 16 MHz  
NOTES:  
1. 16 MHz.  
2. Specifications for PSEN# are identical to those for RD#.  
3. In the formula, M=Number of wait states (0 or 1) for ALE.  
4. In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#.  
5. “Typical” specifications are untested and not guaranteed.  
20  
PRELIMINARY  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
Table 11. AC Characteristics (Continued)  
@ Max Fosc (1)  
Fosc Variable  
Symbol  
Parameter  
Units  
Min  
Max  
Min  
Max  
TAVDV1  
Address (P0) Valid to Valid Data/Instruction In  
ns  
243.2  
160  
4(1+M/2)  
OSC – 90  
@ 12 MHz  
@ 16 MHz  
(3)  
T
TAVDV2  
Address (P2) Valid to Valid Data/Instruction In  
ns  
268.2  
185  
4(1+M/2)  
TOSC – 65  
@ 12 MHz  
@ 16 MHz  
(3)  
TAVDV3  
Address (P0) Valid to Valid Instruction In  
ns  
116.6  
75  
2TOSC – 50  
@ 12 MHz  
@ 16 MHz  
T
AVRL (2) Address Valid to RD#/PSEN# Low  
ns  
121.6  
80  
2(1+M)  
@ 12 MHz  
@ 16 MHz  
(3)  
T
OSC – 45  
TAVWL1  
TAVWL2  
TWHQX  
TQVWH  
TWHAX  
NOTES:  
Address (P0) Valid to WR# Low  
@ 12 MHz  
ns  
126.6  
85  
2(1+M)  
(3)  
TOSC – 40  
@ 16 MHz  
Address (P2) Valid to WR# Low  
@ 12 MHz  
ns  
(3)  
146.6  
105  
2(1+M)  
TOSC – 20  
@ 16 MHz  
Data Hold after WR# High  
@ 12 MHz  
ns  
63.3  
42.5  
TOSC – 20  
@ 16 MHz  
Data Valid to WR# High  
@ 12 MHz  
ns  
138.6  
97  
2(1+N)  
TOSC – 28  
(4)  
@ 16 MHz  
WR# High to Address Hold  
@ 12 MHz  
ns  
156.6  
115  
2TOSC – 10  
@ 16 MHz  
1. 16 MHz.  
2. Specifications for PSEN# are identical to those for RD#.  
3. In the formula, M=Number of wait states (0 or 1) for ALE.  
4. In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#.  
5. “Typical” specifications are untested and not guaranteed.  
PRELIMINARY  
21  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
5.3.1 EXTERNAL BUS CYCLES, NONPAGE MODE  
T
OSC  
XTAL1  
ALE  
†
T
LHLL  
†
T
RLRH  
T
RHLH1  
†
T
LLRL  
RD#/PSEN#  
†
T
RLDV  
T
RLAZ  
†
T
LHAX  
T
RHDZ1  
†
T
T
LLAX  
AVLL  
T
RHDX  
P0  
A7:0  
D7:0  
†
Instruction In  
T
AVRL  
†
T
T
AVDV1  
†
AVDV2  
P2/A16/A17  
A15:8/A16/A17  
†
The value of this parameter depends on wait states. See the table of AC characteristics.  
A4211-03  
Figure 7. External Bus Cycle: Code Fetch (Nonpage Mode)  
22  
PRELIMINARY  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
T
OSC  
XTAL1  
ALE  
†
T
LHLL  
†
T
RLRH  
†
T
T
RHLH2  
LLRL  
RD#/PSEN#  
†
T
RLDV  
T
RLAZ  
†
T
LHAX  
T
RHDZ2  
†
T
AVLL  
T
LLAX  
T
RHDX  
D7:0  
P0  
A7:0  
†
Data In  
T
AVRL  
†
T
AVDV1  
†
T
AVDV2  
A15:8/A16/A17  
P2/A16/A17  
†
The value of this parameter depends on wait states. See the table of AC characteristics.  
A4210-03  
Figure 8. External Bus Cycle: Data Read (Nonpage Mode)  
PRELIMINARY  
23  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
T
OSC  
XTAL1  
†
ALE  
T
LHLL  
†
T
WLWH  
T
WHLH  
WR#  
†
T
LHAX  
†
T
QVWH  
T
T
AVLL  
LLAX  
T
WHQX  
P0  
A7:0  
D7:0  
†
Data Out  
T
AVWL1  
†
T
T
AVWL2  
WHAX  
P2/A16/A17  
A15:8/A16/A17  
†
The value of this parameter depends on wait states. See the table of AC characteristics.  
A4179-01  
Figure 9. External Bus Cycle: Data Write (Nonpage Mode)  
24  
PRELIMINARY  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
5.3.2 EXTERNAL BUS CYCLES, PAGE MODE  
T
OSC  
XTAL1  
ALE  
†
T
LHLL  
†
T
LLRL  
†††  
RD#/PSEN#  
†
T
RLDV  
T
RLAZ  
†
T
T
RHDZ1  
T
LHAX  
†
T
AVLL  
T
RHDX  
LLAX  
P2  
A15:8  
D7:0  
D7:0  
†
Instruction In  
Instruction In  
T
AVRL  
†
T
T
AVDV3  
AVDV1  
†
T
AVDV2  
P0/A16/A17  
A7:0/A16/A17  
A7:0/A16/A17  
††  
††  
Page Miss  
Page Hit  
†
The value of this parameter depends on wait states. See the table of AC characteristics.  
A page hit (i.e., a code fetch to the same 256-byte "page" as the previous code fetch) requires one  
state (2TOSC); a page miss requires two states (4TOSC).  
††  
†††  
During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle.  
A4213-02  
Figure 10. External Bus Cycle: Code Fetch (Page Mode)  
PRELIMINARY  
25  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
T
OSC  
XTAL1  
ALE  
†
T
LHLL  
†
T
RLRH  
†
T
T
RHLH2  
LLRL  
RD#/PSEN#  
†
T
RLDV  
T
RLAZ  
†
T
LHAX  
T
RHDZ2  
†
T
AVLL  
T
LLAX  
T
RHDX  
D7:0  
P2  
A15:8  
†
Data In  
T
AVRL  
†
T
AVDV1  
†
T
AVDV2  
A7:0/A16/A17  
P0/A16/A17  
†
The value of this parameter depends on wait states. See the table of AC characteristics.  
A4212-03  
Figure 11. External Bus Cycle: Data Read (Page Mode)  
26  
PRELIMINARY  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
T
OSC  
XTAL1  
ALE  
†
T
LHLL  
†
T
WLWH  
T
WHLH  
WR#  
†
T
LHAX  
†
T
T
QVWH  
AVLL  
T
LLAX  
T
WHQX  
P2  
A15:8  
D7:0  
†
Data Out  
T
AVWL1  
†
T
T
AVWL2  
WHAX  
P0/A16/A17  
A7:0/A16/A17  
†
The value of this parameter depends on wait states. See the table of AC characteristics.  
A4182-01  
Figure 12. External Bus Cycle: Data Write (Page Mode)  
PRELIMINARY  
27  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
5.3.3 DEFINITION OF REAL-TIME WAIT SYMBOLS  
Table 12. Real-time Wait Timing Symbol Definitions  
Signals  
Conditions  
A
Address  
Data  
L
Low  
D
C
Y
X
V
Hold  
Setup  
WCLK  
WAIT#  
WR#  
W
R
RD#/PSEN#  
5.3.4 EXTERNAL BUS CYCLES, REAL-TIME WAIT STATES  
State 1  
State 2  
State 3  
State 1 (next cycle)  
WCLK  
TCLYX min  
TCLYX max  
ALE  
TCLYV  
RD#/PSEN#  
RD#/PSEN#  
stretched  
TRLYX max  
TRLYX min  
TRLYV  
WAIT#  
P0  
A0-A7  
D0-D7  
stretched  
stretched  
A0-A7  
P2  
A8-A15  
A8-A15  
A5000-01  
Figure 13. External Bus Cycle: Code Fetch/Data Read (Nonpage Mode)  
28  
PRELIMINARY  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
State 1  
State 2  
State 3  
State 4  
WCLK  
TCLYX min  
ALE  
TCLYX max  
TCLYV  
WR#  
WR# stretched  
TWLYX max  
T
WLYX min  
TWLYV  
WAIT#  
P0  
D0-D7  
A0-A7  
stretched  
stretched  
P2  
A8-A15  
A5002-01  
Figure 14. External Bus Cycle: Data Write (Nonpage Mode)  
State 1  
State 2  
State 3  
State 1 (next cycle)  
WCLK  
TCLYX min  
TCLYX max  
ALE  
TCLYV  
RD#/PSEN#  
RD#/PSEN# stretched  
TRLYX max  
TRLYX min  
TRLYV  
WAIT#  
P2  
A8-A15  
D0-D7  
A0-A7  
stretched  
stretched  
A8-A15  
P0  
A0-A7  
A5001-01  
Figure 15. External Bus Cycle: Code Fetch/Data Read (Page Mode)  
PRELIMINARY  
29  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
State 1  
State 2  
State 3  
State 4  
WCLK  
TCLYX min  
ALE  
TCLYX max  
TCLYV  
WR#  
WR# stretched  
TWLYX max  
T
WLYX min  
TWLYV  
WAIT#  
P2  
A8-A15  
D0-D7  
stretched  
stretched  
P0  
A0-A7  
A5003-01  
Figure 16. External Bus Cycle: Data Write (Page Mode)  
Table 13. Real-time Wait AC Timing  
Symbol  
TCLYV  
Parameter  
Min  
Max  
Units  
ns  
Wait Clock Low to Wait Set-up  
Wait Hold after Wait Clock Low  
PSEN#/RD# Low to Wait Set-up  
Wait Hold after PSEN#/RD# Low  
WR# Low to Wait Set-up  
0
TOSC – 20  
TCLYX  
TRLYV  
TRLYX  
TWLYV  
TWLYX  
(2W)TOSC + 5  
(1+2W)TOSC – 20  
TOSC – 20  
ns  
0
ns  
(2W)TOSC + 5  
0
(1+2W)TOSC – 20  
TOSC – 20  
ns  
ns  
Wait Hold after WR# Low  
(2W)TOSC + 5  
(1+2W)TOSC – 20  
ns  
30  
PRELIMINARY  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
5.4 AC Characteristics — Serial Port, Shift Register Mode  
Table 14. Serial Port Timing — Shift Register Mode  
Symbol  
TXLXL  
Parameter  
Min  
12TOSC  
Max  
Units  
ns  
Serial Port Clock Cycle Time  
TQVSH  
TXHQX  
TXHDX  
TXHDV  
Output Data Setup to Clock Rising Edge  
Output Data hold after Clock Rising Edge  
Input Data Hold after Clock Rising Edge  
Clock Rising Edge to Input Data Valid  
10TOSC – 133  
2TOSC – 117  
0
ns  
ns  
ns  
10TOSC – 133  
ns  
T
XLXL  
TXD  
T
XHQX  
†
†
Set TI  
T
QVXH  
RXD  
(Out)  
0
1
2
7
4
6
3
5
†
T
AV  
T
T
XHDV  
XHDX  
Set RI  
RXD  
(In)  
Valid  
Valid  
Valid  
Valid  
Valid  
Valid  
Valid  
Valid  
†
TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit.  
A2592-02  
Figure 17. Serial Port Waveform — Shift Register Mode  
5.5 External Clock Drive  
Table 15. External Clock Drive  
Symbol  
1/TCLCL  
TCHCX  
Parameter  
Oscillator Frequency (FOSC  
High Time  
Min  
Max  
Units  
MHz  
ns  
)
16  
20  
20  
TCLCX  
Low Time  
ns  
TCLCH  
Rise Time  
10  
10  
ns  
TCHCL  
Fall Time  
ns  
PRELIMINARY  
31  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
TCLCH  
TCHCX  
VCC – 0.5  
0.7 VCC  
TCLCX  
0.2 VCC – 0.1  
0.45 V  
TCHCL  
TCLCL  
A4119-01  
Figure 18. External Clock Drive Waveforms  
Outputs  
Inputs  
VCC – 0.5  
0.45 V  
0.2 VCC + 0.9  
0.2 VCC – 0.1  
VIH MIN  
VOL MAX  
AC inputs during testing are driven at VCC – 0.5V for a logic 1  
and 0.45 V for a logic 0. Timing measurements are made at  
a min of VIH for a logic 1 and VOL for a logic 0.  
A4118-01  
Figure 19. AC Testing Input, Output Waveforms  
VLOAD + 0.1 V  
VLOAD  
VOH – 0.1 V  
Timing Reference  
Points  
VOL + 0.1 V  
VLOAD – 0.1 V  
For timing purposes, a port pin is no longer floating when a  
100 mV change from load voltage occurs and begins to float  
when a 100 mV change from the loading VOH/VOL level occurs  
with IOL/IOH = ± 20 mA.  
A4117-01  
Figure 20. Float Waveforms  
32  
PRELIMINARY  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
6.0 THERMAL CHARACTERISTICS  
Table 16. Thermal Characteristics  
Package Type  
θJA  
θJC  
All thermal impedance data is approximate for static  
air conditions at 1 watt of power dissipation. Values  
change depending on operating conditions and  
application requirements. The Intel Packaging  
Handbook (order number 240800) describes Intel’s  
thermal impedance test methodology.  
44-pin PLCC  
46°C/W  
45°C/W  
30.5°C/W  
16°C/W  
16°C/W  
10°C/W  
40-pin PDIP  
40-pin Ceramic DIP  
7.0 NONVOLATILE MEMORY PROGRAMMING AND VERIFICATION  
CHARACTERISTICS  
7.1 Definition of Nonvolatile Memory Symbols  
Table 17. Nonvolatile Memory Timing Symbol Definitions  
Signals  
Conditions  
A
D
Q
S
G
E
Address  
Data In  
Data Out  
Supply  
H
L
High  
Low  
V
X
Z
Valid  
No Longer Valid  
Floating  
PROG#  
Enable  
33  
PRELIMINARY  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
7.2 Programming and Verification Timing for Nonvolatile Memory  
Programming Cycle  
Verification Cycle  
P1, P3  
P2  
Address (16 Bits)  
Address  
AVQV  
T
Data In (8 Bits)  
Data Out  
T
T
GHDX  
DVGL  
T
T
GHAX  
AVGL  
T
GHGL  
PROG#  
1
2
3
4
5
T
GHSL  
T
GLGH  
T
SHGL  
12.75V  
EA#/V  
PP  
5V  
T
T
ELQV  
EHQZ  
T
EHSH  
P0  
Mode (8 Bits)  
Mode  
A4128-01  
Figure 21. Timing for Programming and Verification of Nonvolatile Memory  
Table 18. Nonvolatile Memory Programming and Verification Characteristics at  
TA = 21 – 27 °C, VCC = 5 V, and VSS = 0 V  
Symbol  
VPP  
Definition  
Programming Supply Voltage  
Programming Supply Current  
Oscillator Frequency  
Min  
Max  
13.5  
75  
Units  
12.5  
D.C. Volts  
mA  
IPP  
FOSC  
4.0  
48TOSC  
48TOSC  
48TOSC  
48TOSC  
48TOSC  
10  
6.0  
MHz  
TAVGL  
TGHAX  
TDVGL  
TGHDX  
TEHSH  
TSHGL  
TGHSL  
TGLGH  
Address Setup to PROG# Low  
Address Hold after PROG#  
Data Setup to PROG# Low  
Data Hold after PROG#  
ENABLE High to VPP  
VPP Setup to PROG# Low  
VPP Hold after PROG#  
PROG# Width  
µs  
µs  
µs  
10  
90  
110  
34  
PRELIMINARY  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
Table 18. Nonvolatile Memory Programming and Verification Characteristics at  
TA = 21 – 27 °C, VCC = 5 V, and VSS = 0 V(Continued)  
TAVQV  
TELQV  
TEHQZ  
TGHGL  
Address to Data Valid  
48TOSC  
48TOSC  
48TOSC  
ENABLE Low to Data Valid  
Data Float after ENABLE  
PROG# High to PROG# Low  
0
10  
µs  
memory have been retained in this datasheet.  
8.0 ERRATA  
8. Signature Byte information has been deleted.  
See the 8XC251SA/SB/SP/SQ Embedded  
Microcontroller User’s Manual.  
There are no known errata for this product.  
9. Sections in the datasheet are numbered.  
10. New sections have been created to provide  
better organization. These include “Nomencla-  
ture,” “Pinout,” “Signals,” “Address Map,”  
“Electrical Characteristics,” “Thermal Charac-  
teristics,” “Nonvolatile Memory Programming  
and Verification Characteristics”, “Errata,” and  
“Revision History”  
11. Proliferation Options and Package Options are  
in the Nomenclature section.  
12. Temperature range is contained in the Electri-  
cal Characteristics section under “Operating  
Conditions”  
9.0 REVISION HISTORY  
This (-003) revision of the 8XC251SA/SB/SP/SQ  
datasheet contains information on products with  
“[M] [C] '94 '95 C” as the last line of the topside  
marking. This datasheet replaces earlier product  
information. The following changes appear in the -  
003 datasheet:  
1. Real-time wait state operation is described in  
the datasheet.  
2. Memory map reserved locations are newly  
defined and the Memory Map is now referred  
to as the “Address Map.”  
13. Bus timing diagrams have been organized into  
subsections.  
3. AC Characteristics have been updated. The  
following AC parameters have changed: TLLAX  
TRLRH, TWLWH, TLLRL, TRLDV, TRHDZ1, TRHDZ2, TRHLH2  
WHLH, TAVDV1, TAVDV2, TAVRL, TAVWL1, TAVWL2  
TQVWH, and TWHAX  
4. DC Characteristics have been updated. The  
following DC specs have changed: IPD max, IDL  
typical, IDL max, ICC typical, and ICC max.  
5. An ICC vs. Frequency graph is included.  
6. Process information is no longer contained in  
the datasheet.  
7. The section “Programming and Verifying Non-  
volatile Memory” has been deleted. See the  
8XC251SA/SB/SP/SQ Embedded Microcon-  
troller User’s Manual. Timing and Characteris-  
tics for Programming and Verifying Nonvolatile  
,
,
The (-002) revision of the 8XC251SA/SB/SP/SQ  
datasheet contains information on products with  
“[M] [C] '94 '95 B” as the last line of the topside  
marking. This datasheet replaces earlier product  
information. The following changes appear in the -  
002 datasheet:  
T
,
.
1. A corrected PDIP diagram appears on page 7.  
2. A corrected formula to calculate TLHLL is  
described on page 17.  
3. The RD#/PSEN# waveform is changed in Fig-  
ure 11 on page 25.  
PRELIMINARY  
35  
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