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8XC152JC

型号：

8XC152JC

描述：

通用通信控制器8位微控制器[ UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER ]

品牌：

INTEL[ INTEL ]

页数：

17 页

PDF大小：

264 K

下载PDF手册
8XC152JA/JB/JC/JD  
UNIVERSAL COMMUNICATION CONTROLLER  
8-BIT MICROCONTROLLER  
X
8K Factory Mask Programmable ROM Available  
Y
Y
Y
Superset of 80C51 Architecture  
64KB Data Memory Addressing  
256 Bytes On-Chip RAM  
Y
Y
Y
Y
Y
Y
Y
Y
Multi-Protocol Serial Communication  
I/O Port (2.048 Mbps/2.4 Mbps Max)  
Ð SDLC/HDLC Only  
Ð CSMA/CD and SDLC/HDLC  
Ð User Definable Protocols  
Dual On-Chip DMA Channels  
Hold/Hold Acknowledge  
Two General Purpose Timer/Counters  
5 or 7 I/O Ports  
Y
Y
Y
Y
Y
Full Duplex/Half Duplex  
MCS -51 Compatible UART  
É
56 Special Function Registers  
11 Interrupt Sources  
16.5 MHz Maximum Clock Frequency  
Multiple Power Conservation Modes  
64KB Program Memory Addressing  
Available in 48 Pin Dual-in-Line Package  
and 68 Pin Surface Mount PLCC  
Package  
Ý
(See Packaging Spec. Order 231369)  
The 80C152, which is based on the MCS -51 CPU, is a highly integrated single-chip 8-bit microcontroller  
É
designed for cost-sensitive, high-speed, serial communications. It is well suited for implementing Integrated  
Services Digital Networks (ISDN), emerging Local Area Networks, and user defined serial backplane applica-  
tions. In addition to the multi-protocol communication capability, the 80C152 offers traditional microcontroller  
features for peripheral I/O interface and control.  
Silicon implementations are much more cost effective than multi-wire cables found in board level parallel-to-  
serial and serial-to-parallel converters. The 83C152 contains, in silicon, all the features needed for the serial-  
to-parallel conversion. Other 83C152 benefits include: 1) better noise immunity through differential signaling or  
fiber optic connections, 2) data integrity utilizing the standard, designed in CRC checks, and 3) better modulari-  
ty of hardware and software designs. All of theseÐcost, network parameter and real estate improvementsÐ  
apply to 83C152 serial links between boards or systems and 83C152 serial links on a single board.  
*Other brands and names are the property of their respective owners.  
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or  
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make  
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.  
©
COPYRIGHT INTEL CORPORATION, 1995  
October 1989  
Order Number: 270431-003  
8XC152JA/JB/JC/JD  
270431–2  
270431–1  
270431–3  
Figure 1. Connection Diagrams  
2
8XC152JA/JB/JC/JD  
*On 80C152JB/JD Only  
270431–18  
Figure 2. Block Diagram  
3
8XC152JA/JB/JC/JD  
EPSEN is used in conjunction with Port 5 and Port 6  
program memory operations. EPSEN functions like  
PSEN during program memory operation, but sup-  
ports Port 5 and Port 6. EPSEN is the read strobe to  
external program memory for Port 5 and Port 6.  
EPSEN is activated twice during each machine cycle  
unless an external data memory operation occurs on  
Port(s) 0 and Port 2. When external data memory is  
accessed the second activation of EPSEN is  
skipped, which is the same as when using PSEN.  
Note that data memory fetches cannot be made  
through Ports 5 and 6.  
80C152JB/JD General Description  
The 80C152JB/JD is a ROMless extension of the  
80C152 Universal Communication controller. The  
80C152JB has the same five 8-bit I/O ports of the  
80C152, plus an additional two 8-bit I/O ports, Port 5  
and Port 6. The 80C152JB/JD also has two addi-  
tional control pins, EBEN (EPROM Bus ENable), and  
EPSEN (EPROM bus Program Store ENable).  
EBEN selects the functionality of Port 5 and Port 6.  
When EBEN is low, these ports are strictly I/O, simi-  
lar to Port 4. The SFR location for Port 5 is 91H and  
Port 6 is 0A1H. This means Port 5 and Port 6 are not  
bit addressable. With EBEN low, all program memo-  
ry fetches take place via Port 0 and Port 2. (The  
80C152 is a ROMless only product). When EBEN is  
high, Port 5 and Port 6 form an address/data bus  
called the E-Bus (EPROM-Bus) for program memory  
operations.  
When EBEN is high and EA is low, all program mem-  
ory operations take place via Ports 5 and 6. The high  
byte of the address goes out on Port 6, and the low  
byte is output on Port 5. ALE is still used to latch the  
address on Port 5. Next, the op code is read on Port  
5. The timing is the same as when using Ports 0 and  
2 for external program memory operations.  
Table 1. Program Memory Fetches  
Program  
Fetch via  
EBEN  
EA  
PSEN  
EPSEN  
Comments  
0
0
1
1
0
1
0
1
P0, P2  
N/A  
Active  
N/A  
Inactive  
N/A  
Addresses 0–0FFFFH  
Invalid Combination  
Addresses 0–0FFFFH  
Addresses 0–1FFFH  
P5, P6  
Inactive  
Active  
P5, P6  
P0, P2  
Inactive  
Active  
Active  
Inactive  
t
Addresses 2000H  
Table 2. 8XC152 Product Differences  
CSMA/CD  
and  
ROM  
PLCC  
ROMless  
Version  
HDLC/SDLC  
Only  
PLCC  
5 I/O  
Ports  
7 I/0  
Version  
Available  
and  
DIP  
Only  
Ports  
HDLC/SDLC  
80C152JA  
80C152JB  
80C152JC  
80C152JD  
(83C152JA)  
*
*
*
*
*
*
*
*
*
*
*
*
(83C152JC)  
*
*
NOTES:  
e
options available  
0 standard frequency range 3.5 MHz to 12 MHz  
*
0 ‘‘ 1’’ frequency range 3.5 MHz to 16.5 MHz  
b
4
8XC152JA/JB/JC/JD  
Ý
Pin  
Pin Description  
(1)  
DIP  
48  
PLCC  
2
V
V
ÐSupply voltage.  
CC  
(2)  
24  
3,33  
ÐCircuit ground.  
SS  
18-21, 27-30,  
25-28 34-37  
Port 0ÐPort 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin  
can sink 8 LS TTL inputs. Port 0 pins that have 1s written to them float, and in that  
state can be used as high-impedance inputs.  
Port 0 is also the multiplexed low-order address and data bus during accesses to  
external program memory if EBEN is pulled low. During accesses to external Data  
Memory, Port 0 always emits the low-order address byte and serves as the multiplexed  
data bus. In these applications it uses strong internal pullups when emitting 1s.  
Port 0 also outputs the code bytes during program verification. External pullups are  
required during program verification.  
1-8  
4-11  
Port 1ÐPort 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 pins that  
have 1s written to them are pulled high by the internal pullups, and in that state can be  
used as inputs. As inputs, Port 1 pins that are externally being pulled low will source  
current (I , on the data sheet) because of the internal pullups.  
IL  
Port 1 also serves the functions of various special features of the 8XC152, as listed  
below:  
Pin  
Name  
Alternate Function  
P1.0  
P1.1  
P1.2  
P1.3  
P1.4  
P1.5  
P1.6  
GRXD  
GSC data input pin  
GSC data output pin  
GSC enable signal for an external driver  
GSC input pin for external transmit clock  
GSC input pin for external receive clock  
DMA hold input/output  
GTXD  
DEN  
TXC  
RXC  
HLD  
HLDA  
DMA hold acknowledge input/output  
29-36  
41-48  
Port 2ÐPort 2 is an 8-bit bidirectional I/O port with internal pullups. Port 2 pins that  
have 1s written to them are pulled high by the internal pullups, and in that state can be  
used as inputs. As inputs, Port 2 pins that are externally being pulled low will source  
current (I , on the data sheet) because of the internal pullups.  
IL  
Port 2 emits the high-order address byte during fetches from external Program  
Memory if EBEN is pulled low. During accesses to external Data Memory that use 16-  
@
bit addresses (MOVX DPTR and DMA operations), Port 2 emits the high-order  
address byte. In these applications it uses strong internal pullups when emitting 1s.  
@
During accesses to external Data Memory that use 8-bit addresses (MOVX Ri),  
Port 2 emits the contents of the P2 Special Function Register.  
Port 2 also receives the high-order address bits during program verification.  
10- 17 14-16,  
18, 19,  
23-25  
Port 3ÐPort 3 is an 8-bit bidirectional I/O port with internal pullups. Port 3 pins that  
have 1s written to them are pulled high by the internal pullups, and in that state can be  
used as inputs. As inputs, Port 3 pins that are externally being pulled low will source  
current (I , on the data sheet) because of the pullups.  
IL  
Port 3 also serves the functions of various special features of the MCS-51 Family, as  
listed below:  
Pin  
Name  
Alternate Function  
P3.0  
P3.1  
P3.2  
P3.3  
P3.4  
P3.5  
P3.6  
P3.7  
RXD  
TXD  
INT0  
INT1  
T0  
T1  
WR  
RD  
Serial input line  
Serial output line  
External Interrupt 0  
External Interrupt 1  
Timer 0 external input  
Timer 1 external input  
External Data Memory Write strobe  
External Data Memory Read strobe  
5
8XC152JA/JB/JC/JD  
Pin Description (Continued)  
Pin Description  
Ý
Pin  
47-40  
65-58  
Port 4ÐPort 4 is an 8-bit bidirectional I/O port with internal pullups. Port 4 pins that  
have 1s written to them are pulled high by the internal pullups, and in that state can  
be used as inputs. As inputs, Port 4 pins that are externally being pulled low will  
source current (I , on the data sheet) because of the internal pullups. In addition,  
IL  
Port 4 also receives the low-order address bytes during program verification.  
9
13  
55  
RSTÐReset input. A logic low on this pin for three machine cycles while the  
oscillator is running resets the device. An internal pullup resistor permits a power-on  
reset to be generated using only an external capacitor to V . Although the GSC  
SS  
recognizes the reset after three machine cycles, data may continue to be  
transmitted for up to 4 machine cycles after Reset is first applied.  
38  
ALEÐAddress Latch Enable output signal for latching the low byte of the address  
during accesses to external memory.  
In normal operation ALE is emitted at a constant rate of (/6 the oscillator  
frequency, and may be used for external timing or clocking purposes. Note,  
however, that one ALE pulse is skipped during each access to external Data  
Memory. While in Reset, ALE remains at a constant high level.  
37  
54  
56  
PSENÐProgram Store Enable is the Read strobe to External Program Memory.  
When the 8XC152 is executing from external program memory, PSEN is active  
(low). When the device is executing code from External Program Memory, PSEN is  
activated twice each machine cycle, except that two PSEN activations are skipped  
during each access to External Data Memory. While in Reset, PSEN remains at a  
constant high level.  
39  
23  
EAÐExternal Access enable. EA must be externally pulled low in order to enable  
the 8XC152 to fetch code from External Program Memory locations 0000H to  
0FFFH.  
EA must be connected to V for internal program execution.  
CC  
32  
31  
XTAL1ÐInput to the inverting oscillator amplifier and input to the internal clock  
generating circuits.  
22  
XTAL2ÐOutput from the inverting oscillator amplifier.  
N/A  
17, 20  
21, 22  
38, 39  
40, 49  
Port 5ÐPort 5 is an 8-bit bidirectional I/O port with internal pullups. Port 5 pins that  
have 1s written to them are pulled high by the internal pullups, and in that state can  
be used as inputs. As inputs, Port 5 pins that are externally being pulled low will  
source current (I , on the data sheet) because of the internal pullups.  
IL  
Port 5 is also the multiplexed low-order address and data bus during accesses to  
external program memory if EBEN is pulled high. In this application it uses strong  
pullups when emitting 1s.  
N/A  
67, 66  
52, 57  
50, 68  
1, 51  
Port 6ÐPort 6 is an 8-bit bidirectional I/O port with internal pullups. Port 6 pins that  
have 1s written to them are pulled high by the internal pullups, and in that state can  
be used as inputs. As inputs, Port 6 pins that are externally pulled low will source  
current (I , on the data sheet) because of the internal pullups.  
IL  
Port 6 emits the high-order address byte during fetches from external Program  
Memory if EBEN is pulled high. In this application it uses strong pullups when  
emitting 1s.  
N/A  
N/A  
12  
53  
EBENÐE-Bus Enable input that designates whether program memory fetches take  
place via Ports 0 and 2 or Ports 5 and 6. Table 1 shows how the ports are used in  
conjunction with EBEN.  
EPSENÐE-bus Program Store Enable is the Read strobe to external program  
memory when EBEN is high. Table 2 shows when EPSEN is used relative to PSEN  
depending on the status of EBEN and EA.  
6
8XC152JA/JB/JC/JD  
OSCILLATOR CHARACTERISTICS  
XTAL1 and XTAL2 are the input and output, respec-  
tively, of an inverting amplifier which can be config-  
ured for use as an on-chip oscillator, as shown in  
Figure 3.  
To drive the device from an external clock source,  
XTAL1 should be driven, while XTAL2 is left uncon-  
nected, as shown in Figure 4. There are no require-  
ments on the duty cycle of the external clock signal,  
since the input to the internal clocking circuitry is  
through a divide-by-two flip-flop, but minimum and  
maximum high and low times specified on the Data  
Sheet must be observed.  
270431–6  
Figure 4. External Clock Drive  
IDLE MODE  
An external oscillator may encounter as much as a  
100 pF load at XTAL1 when it starts-up. This is due  
to interaction between the amplifier and its feedback  
In Idle Mode, the CPU puts itself to sleep while most  
of the on-chip peripherals remain active. The major  
peripherals that do not remain active during Idle, are  
the DMA channels. The Idle Mode is invoked by  
software. The content of the on-chip RAM and all  
the Special Function Registers remain unchanged  
during this mode. The Idle Mode can be terminated  
by any enabled interrupt or by a hardware reset.  
capacitance. Once the external signal meets the V  
IL  
and V specifications the capacitance will not ex-  
IH  
ceed 20 pF.  
POWER DOWN MODE  
In Power Down Mode, the oscillator is stopped and  
all on-chip functions cease except that the on-chip  
RAM contents are maintained. The mode Power  
Down is invoked by software. The Power Down  
Mode can be terminated only by a hardware reset.  
270431–5  
Figure 3. Using the On-Chip Oscillator  
Table 3. Status of the External Pins During Idle and Power Down Modes  
80C152JA/83C152JA/80C152JC/83C152JC  
Program  
Mode  
Idle  
ALE  
PSEN  
Port 0  
Port 1  
Port 2  
Port 3  
Port 4  
Memory  
Internal  
External  
Internal  
External  
1
1
0
0
1
1
0
Data  
Float  
Data  
Float  
Data  
Data  
Data  
Data  
Data  
Address  
Data  
Data  
Data  
Data  
Data  
Data  
Data  
Data  
Data  
Idle  
Power Down  
Power Down  
²
0
Data  
80C152JB/80C152JD  
Instruction  
Bus  
Mode  
ALE PSEN EPSEN Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6  
Idle  
P0, P2  
P5, P6  
P0, P2  
P5, P6  
1
1
0
0
1
1
0
1
1
1
0
Float Data Address Data Data 0FFH 0FFH  
Idle  
Data Data  
Float Data  
Data Data  
Data  
Data  
Data  
Data Data 0FFH Address  
Data Data 0FFH 0FFH  
Data Data 0FFH 0FFH  
Power Down  
Power Down  
²
1
NOTE:  
For more detailed information on the reduced power modes refer to the Embedded Controller Handbook, and Application  
Note AP-252, ‘‘Designing with the 80C51BH.’’  
²
Note difference of logic level of PSEN during Power Down for ROM JA/JC and ROM emulation mode for JC/JD.  
7
8XC152JA/JB/JC/JD  
ABSOLUTE MAXIMUM RATINGS*  
NOTICE: This data sheet contains preliminary infor-  
mation on new products in production. The specifica-  
tions are subject to change without notice. Verify with  
your local Intel Sales office that you have the latest  
data sheet before finalizing a design.  
a
Ambient Temperature Under Bias ÀÀÀÀ0 C to 70 C  
§
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C  
§
b
a
§
Voltage on Any pin to V ÀÀ 0.5V to (V  
§
0.5V)  
b
a
CC  
SS  
*WARNING: Stressing the device beyond the ‘‘Absolute  
Maximum Ratings’’ may cause permanent damage.  
These are stress ratings only. Operation beyond the  
‘‘Operating Conditions’’ is not recommended and ex-  
tended exposure beyond the ‘‘Operating Conditions’’  
may affect device reliability.  
b
a
Voltage on V to VSSÀÀÀÀÀÀÀÀÀÀÀ 0.5V to 6.5V  
CC  
(9)  
Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.0W  
e
a
0 C to 70 C; V  
e
e
0V)  
SS  
g
5V 10%; V  
D.C. CHARACTERISTICS (T  
§
§
A
CC  
Typ  
Symbol  
Parameter  
Input Low Voltage  
(All Except EA, EBEN)  
Min  
Max  
Unit  
Test Conditions  
(Note 3)  
b
b
b
V
V
V
V
V
V
V
0.5  
0.5  
a
0.2V  
0.2V  
0.1  
V
IL  
CC  
b
Input Low Voltage  
(EA, EBEN)  
0.3  
V
V
V
V
V
V
IL1  
IH  
CC  
a
0.5  
Input High Voltage  
(Except XTAL1, RST)  
0.2V  
0.9  
V
V
CC  
CC  
CC  
a
0.5  
Input High Voltage  
(XTAL1, RST)  
0.7V  
IH1  
OL  
OL1  
OH  
CC  
e
Output Low Voltage  
(Ports 1, 2, 3, 4, 5, 6)  
0.45  
0.45  
I
I
1.6 mA  
(Note 4)  
OL  
e
Output Low Voltage  
(Port 0, ALE, PSEN, EPSEN)  
3.2 mA  
(Note 4)  
e b  
60 mA  
OL  
Output High Voltage  
(Ports 1, 2, 3, 4, 5, 6 COMM9  
ALE, PSEN, EPSEN)  
2.4  
I
OH  
e
g
5V 10%  
V
CC  
e b  
0.9V  
V
V
I
10 mA  
CC  
OH  
e b  
e
V
OH1  
Output High Voltage  
(Port 0 in External  
Bus Mode)  
2.4  
I
400 mA  
OH  
g
V
5V 10%  
CC  
e b  
OH  
0.9V  
V
I
40 mA (Note 5)  
CC  
b
e
0.45V  
I
I
Logical 0 Input  
Current (Ports 1, 2, 3, 4, 5, 6)  
50  
mA  
V
IL  
IN  
b
e
2V  
Logical 1 to 0  
Transition Current  
(Ports 1, 2, 3, 4, 5, 6)  
650  
mA  
mA  
V
TL  
LI  
IN  
k
k
g
I
Input Leakage  
(Port 0, EA)  
10  
60  
0.45  
V
V
CC  
IN  
RRST Reset Pullup Resistor  
40  
kX  
mA  
a
I
I
Logical 1 Input Current (EBEN)  
IH  
Power Supply Current :  
Active (16.5 MHz)  
Idle (16.5 MHz)  
CC  
31  
8
41.1  
15.4  
mA (Note 6)  
mA (Note 6)  
e
2.0V to 5.5V  
Power Down Mode  
10  
mA  
V
CC  
8
8XC152JA/JB/JC/JD  
e
e
c
a
MAX I (ACTIVE)  
cc  
(2.24 FREQ)  
4.16 (Note 6)  
a
2.2 (Note 6)  
c
(0.8 FREQ)  
MAX I (IDLE)  
cc  
270431–7  
Figure 5. I vs Frequency  
CC  
P: PSEN.  
Q: Output data.  
EXPLANATION OF THE AC SYMBOLS  
R: READ signal.  
T: Time.  
V: Valid.  
W: WRITE signal.  
X: No longer a valid logic level.  
Z: Float.  
Each timing symbol has 5 characters. The first char-  
acter is always a ‘T’ (stands for time). The other  
characters, depending on their positions, stand for  
the name of a signal or the logical status of that  
signal. The following is a list of all the characters and  
what they stand for.  
For example,  
A: Address.  
C: Clock  
D: Input data.  
H: Logic level HIGH.  
I: Instruction (program memory contents).  
L: Logic level LOW, or ALE.  
e
e
TAVLL  
TLLPL  
Time for Address Valid to ALE Low.  
Time for ALE Low to PSEN Low.  
9
8XC152JA/JB/JC/JD  
e
a
e
100 pF; Load Capacitance for All Other Outputs  
e
SS  
g
A.C. CHARACTERISTICS (T  
e
0 C to 70 C; V  
5V 10%; V  
0V; Load Capacitance for  
e
80 pF)  
§
§
A
CC  
Port 0, ALE, and PSEN  
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS (Note 7, 10)  
16.5 MHz  
Variable Oscillator  
Symbol  
Parameter  
Unit  
Min  
Max  
Min  
Max  
1/TCLCL  
Oscillator Frequency  
80C152JA/JC  
83C152JA/JC  
3.5  
12  
MHz  
80C152JB/JD  
80C152JA/JC-1  
83C152JA/JC-1  
80C152JB/JD-1  
3.5  
16.5  
MHz  
TLHLL  
TAVLL  
TLLAX  
TLLIV  
ALE Pulse Width  
81  
5
2TCLCL-40  
TCLCL-55  
TCLCL-35  
ns  
ns  
ns  
ns  
Address Valid to ALE Low  
Address Hold After ALE Low  
25  
ALE Low to Valid  
Instruction In  
142  
77  
4TCLCL-100  
3TCLCL-105  
TLLPL  
TPLPH  
TPLIV  
ALE Low to PSEN Low  
PSEN Pulse Width  
20  
TCLCL-40  
ns  
ns  
ns  
137  
3TCLCL-45  
PSEN Low to Valid  
Instruction In  
TPXIX  
TPXIZ  
TAVIV  
TPLAZ  
Input Instruction  
Hold After PSEN  
0
0
ns  
ns  
ns  
ns  
Input Instruction  
Float After PSEN  
35  
198  
10  
TCLCL-25  
5TCLCL-105  
10  
Address to Valid  
Instruction In  
PSEN Low to Address  
Float  
TRLRH  
TWLWH  
TRLDV  
RD Pulse Width  
WR Pulse Width  
263  
263  
6TCLCL-100  
6TCLCL-100  
ns  
ns  
ns  
RD Low to Valid  
Data In  
138  
5TCLCL-165  
TRHDX  
TRHDZ  
TLLDV  
Data Hold After RD  
Data Float After RD  
0
0
ns  
ns  
ns  
51  
2TCLCL-70  
ALE Low to Valid  
Data In  
335  
8TCLCL-150  
TAVDV  
TLLWL  
TAVWL  
Address to Valid  
Data In  
380  
232  
9TCLCL-165  
ns  
ns  
ns  
ns  
a
3TCLCL 50  
ALE Low to RD or  
WR Low  
132  
112  
196  
10  
3TCLCL-50  
4TCLCL-130  
6TCLCL-167  
TCLCL-50  
Address to RD or  
WR Low  
(8)  
TQVWX  
Data Valid to WR  
Transition  
TWHQX  
TRLAZ  
Data Hold After WR  
ns  
ns  
RD Low to Address  
Float  
0
0
a
TCLCL 40  
TWHLH  
RD or WR High to  
ALE High  
20  
100  
TCLCL-40  
ns  
10  
8XC152JA/JB/JC/JD  
EXTERNAL PROGRAM MEMORY READ CYCLE  
270431–8  
EXTERNAL DATA MEMORY READ CYCLE  
270431–9  
11  
8XC152JA/JB/JC/JD  
EXTERNAL DATA MEMORY WRITE CYCLE  
270431–10  
EXTERNAL CLOCK DRIVE  
Symbol  
1/TCLCL  
TCHCX  
TCLCX  
Parameter  
Oscillator Frequency  
High Time  
Min  
3.5  
20  
Max  
Units  
MHz  
ns  
16.5  
Low Time  
20  
ns  
TCLCH  
TCHCL  
Rise Time  
20  
20  
ns  
Fall Time  
ns  
EXTERNAL CLOCK DRIVE WAVEFORM  
270431–11  
12  
8XC152JA/JB/JC/JD  
LOCAL SERIAL CHANNEL TIMINGÐSHIFT REGISTER MODE  
16.5 MHz  
Variable Oscillator  
Symbol  
TXLXL  
Parameter  
Units  
Max  
Min  
Max  
Min  
Serial Port Clock Cycle  
Time  
727  
473  
4
12TCLCL  
ns  
ns  
ns  
ns  
TQVXH  
TXHQX  
TXHDX  
TXHDV  
Output Data Setup to  
Clock Rising Edge  
10TCLCL-133  
2TCLCL-117  
0
Output Data Hold After  
Clock Rising Edge  
Input Data Hold After  
Clock Rising Edge  
0
Clock Rising Edge to  
Input Data Valid  
473  
10TCLCL-133  
ns  
SHIFT REGISTER MODE TIMING WAVEFORMS  
270431–12  
A.C. TESTING:  
INPUT, OUTPUT WAVEFORMS  
FLOAT WAVEFORM  
270431–13  
270431–14  
For Timing Purposes a Port Pin is no Longer Floating when a  
100 mV change from Load Voltage Occurs, and Begins to Float  
when a 100 mV change from the Loaded V /V Level occurs  
b
AC Inputs During Testing are Driven at V  
CC  
0.5 for a Logic ‘‘1’’  
and 0.45V for a Logic ‘‘0’’. Timing Measurements are made at V  
IH  
Min for a Logic ‘‘1’’ and V Max for a Logic ‘‘0’’.  
IL  
OH OL  
t
g
20 mA.  
I
/I  
OL OH  
13  
8XC152JA/JB/JC/JD  
GLOBAL SERIAL PORT TIMINGSÐInternal Baud Rate Generator  
e
16.5 MHz (BAUD  
0)  
Variable Oscillator  
Symbol  
Parameter  
Unit  
Min  
Max  
Min  
Max  
c
HBTJR  
Allowable jitter on  
the Receiver for (/2  
bit time (Manchester  
encoding only)  
0.0375  
0.10  
(0.125  
ms  
a
c
c
(BAUD 1)  
8TCLCL)  
b
25 ns  
c
FBTJR  
HBTJT  
FBTJT  
Allowable jitter on  
the Receiver for one  
full bit time (NRZI  
and Manchester)  
(0.25  
ms  
ns  
ns  
a
(BAUD 1)  
8TCLCL)  
b
25 ns  
g
g
g
Jitter of data from  
Transmitter for (/2  
bit time (Manchester  
encoding only)  
10  
10  
10  
10  
g
Jitter of data from  
Transmitter for one  
full bit time (NRZI  
and Manchester)  
DRTR  
DFTR  
Data rise time for  
(11)  
Receiver  
20  
20  
ns  
ns  
Data fall time for  
(12)  
Receiver  
20  
20  
GSC RECEIVER TIMINGS (INTERNAL BAUD RATE GENERATOR)  
270431–15  
14  
8XC152JA/JB/JC/JD  
GSC TRANSMIT TIMINGS (INTERNAL BAUD RATE GENERATOR)  
270431–16  
GLOBAL SERIAL PORT TIMINGSÐExternal Clock  
16.5 MHz  
Variable Oscillator  
Symbol  
1/ECBT  
ECH  
Parameter  
Unit  
MHz  
ns  
Min  
Max  
Min  
Max  
c
GSC Frequency with an  
External Clock  
2.4  
0.009  
F
0.145  
OSC  
External Clock High  
External Clock Low  
External Clock Rise  
170  
170  
2TCLCL  
a
45 ns  
(13)  
ECL  
2TCLCL  
a
ns  
45 ns  
ECRT  
ECFT  
20  
20  
20  
20  
ns  
(11)  
Time  
External Clock Fall  
(12)  
Time  
ns  
ECDVT  
External Clock to Data  
Valid Out - Transmit  
(to External Clock  
Negative Edge)  
ns  
150  
150  
ECDHT  
ECDSR  
ECDHR  
External Clock Data  
Hold - Transmit  
ns  
ns  
ns  
0
0
(to External Clock  
Negative Edge)  
External Clock Data  
Set-up - Receiver  
(to External Clock  
Positive Edge)  
45  
45  
External Clock to Data  
Hold - Receiver  
50  
50  
(to External Clock  
Positive Edge)  
15  
8XC152JA/JB/JC/JD  
GSC TIMINGS (EXTERNAL CLOCK)  
270431–17  
NOTES:  
1. N.C. pins on PLCC package may be connected to internal die and should not be used in customer applications.  
2. It is recommended that both Pin 3 and Pin 33 be grounded for PLCC devices.  
3. ‘‘Typicals’’ are based on samples taken from early manufacturing lots and are not guaranteed. The measurements were  
e
4. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V s of ALE and Ports  
made with V  
5V at room temperature.  
CC  
OL  
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-  
l
to-0 transitions during bus operations. In the worst cases (capacitive loading  
100 pF), the noise pulse on the ALE pin may  
exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt  
Trigger STROBE input.  
5. Capacitive loading on Ports 0 and 2 may cause the V  
cation when the address bits are stabilizing.  
on ALE and PSEN to momentarily fall below the 0.9V  
specifi-  
CC  
OH  
e
e
a
0.5V; XTAL2 N.C.; Port 0 pins connected to V . ‘‘Operating’’ current is measured with EA connected to V  
e
6. I  
V
is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL  
CC  
b
5 ns, V  
V
0.5V, V  
IL  
SS  
IH  
and  
CC  
CC  
CC  
and GSC inactive.  
RST connected to V . ‘‘Idle’’ current is measured with EA connected to V , RST connected to V  
SS SS CC  
7. The specifications relating to external data memory characteristics are also applicable to DMA operations.  
8. TQVWX should not be confused with TQVWX as specified for 80C51BH. On 80C152, TQVWX is measured from data  
valid to rising edge of WR. On 80C51BH, TQVWX is measured from data valid to falling edge of WR. See timing diagrams.  
9. This value is based on the maximum allowable die temperature and the thermal resistance of the package.  
10. All specifications relating to external program memory characteristics are applicable to:  
EPSEN for PSEN  
Port 5 for Port 0  
Port 6 for Port 2  
when EBEN is at a Logical 1 on the 80C152JB/JD.  
11. Same as TCLCH, use External Clock Drive Waveform.  
12. Same as TCHCL, use External Clock Drive Waveform.  
13. When using the same external clock to drive both the receiver and transmitter, the minimum ECL spec effectively  
becomes 195 ns at all frequencies (assuming 0 ns propagation delay) because ECDVT (150 ns) plus ECDSR (45 ns) re-  
a
e
propagation delay between receivers and transmitters.  
quirements must also be met (150  
45  
195 ns). The 195 ns requirement would also increase to include the maximum  
16  
8XC152JA/JB/JC/JD  
DESIGN NOTES  
Within the 8XC152 there exists a race condition that may set both the RDN and AE bits at the end of a valid  
reception. This will not cause a problem in the application as long as the following steps are followed:  
ÐNever give the receive error interrupt a higher priority than the valid reception interrupt  
ÐDo not leave the valid reception interrupt service routine when AE is set by using a RETI instruction until AE  
is cleared. To clear AE set the GREN bit, this enables the receiver. If the user desires that the receiver remain  
disabled, clear GREN after setting it before leaving the interrupt service routine.  
ÐIf the AE bit is checked by user software in response to a valid reception interrupt, the status of AE should  
be considered invalid.  
The race condition is dependent upon both the temperature that the device is currently operating at and the  
processing the device received during the wafer fabrication.  
When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from  
where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware  
inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the  
possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that  
invokes Idle should not be one that writes to a port pin or to external memory.  
DATA SHEET REVISION SUMMARY  
The following represent the key differences between the ‘‘-003’’ and the ‘‘-002’’ version of the  
80C152/83C152 data sheet. Please review this summary carefully.  
1. Removed minimum GSC frequency spec when used with an external clock.  
2. Change figure ‘‘External Program Memory Read Cycle’’ to show Port 0/Port 5 address floating after PSEN  
goes low.  
3. Added design note on terminating idle with reset.  
4. Added status of PSEN during Power Down mode to Table 3.  
5. Moved all notes to back of data sheet.  
6. Changed microcomputer to microcontroller.  
7. Added External Oscillator start-up capacitance note.  
The following represent the key differences between the ‘‘-002’’ and the ‘‘-001’’ version of the 80C152/  
83C152 data sheet. Please review this summary carefully.  
1. Status of data sheet changed from ‘‘ADVANCED’’ to ‘‘PRELIMINARY’’.  
2. 80C152JC, 83C152JC, and 80C152JD were added.  
3. Added AE/RDN design note.  
4. This revision summary was added.  
Ý
5. Note 13 was added (Effective ECL spec at higher clock rates).  
Ý
Ý
6. Table 2 changed to Table 3 (Status of pins during Idle/Power Down).  
Ý
7. Current Table 2 was added (JA vs. JB vs. JC vs. JD matrix).  
g
g
g
8. Transmit jitter spec changed from 35 ns and 70 ns to 10 ns.  
17  
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