请登录

免费注册
全部商品
电子元器件
方案中心
工业品
PDF资料
购物车 0
上传BOM

产品分类

找货询价

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

QQ咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

会员中心
购物车
技术支持

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

售后咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

8XC196KB

型号：

8XC196KB

描述：

先进的16位微控制器CHMOS无ROM或ROM[ ADVANCED 16-BIT CHMOS MICROCONTROLLER ROMless OR ROM ]

品牌：

INTEL[ INTEL ]

页数：

17 页

PDF大小：

250 K

下载PDF手册
8XC196KB  
ADVANCED 16-BIT CHMOS MICROCONTROLLER  
ROMless OR ROM  
Automotive  
b
a
40 C to 125 C Ambient  
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Dynamically Configurable 8/16-Bit  
Buswidth  
§
§
232 Bytes of On-Chip Register RAM  
8 Kbytes of On-Chip ROM (Optional)  
High-Performance CHMOS Process  
Register-to-Register Architecture  
10-Bit A/D Converter with S/H  
Five 8-Bit I/O Ports  
Y
Y
Y
Y
Y
Y
Y
Y
Y
Full Duplex Serial Port  
Dedicated Baud Rate Generator  
1.725 ms 16 x 16 Multiply  
3 ms 32/16 Divide  
16-Bit Watchdog Timer  
16-Bit Timer  
28 Interrupt Sources  
16-Bit Up/Down Counter w/Capture  
Four 16-Bit Software Timers  
HOLD/HOLDA Bus Protocol  
Pulse Width Modulated Output  
Powerdown and Idle Modes  
High Speed I/O Subsystem  
The 8XC196KB 16-bit microcontroller comes with 8 Kbytes of on-chip mask programmable ROM or in ROM-  
less versions. All devices are high performance members of the 8096 microcontroller family. The 8XC196KB is  
pin-to-pin compatible and uses a true superset of the 8096 instructions. Intel’s CHMOS process provides a  
high performance processor along with low power consumption. To further reduce power requirements, the  
processor can be placed into Idle or Powerdown Mode.  
Bit, byte, word and some 32-bit operations are available on the 8XC196KB. With a 16 MHz oscillator, a 16-bit  
addition takes 0.495 ms, and the instruction times average 0.375 ms to 1.125 ms in typical applications.  
a
Four high-speed capture inputs are provided to record times when events occur. 4  
2 high-speed outputs are  
available for pulse or waveform generation. The high-speed output can also generate four software timers or  
start an A/D conversion. Events can be based on the 16-bit timer or a 16-bit up/down counter.  
Also provided on-chip are an 8 channel, 10-bit A/D converter with Sample and Hold, a serial port with  
synchronous/asynchronous modes and on-chip baud rate generator, a 16-bit watchdog timer, pulse width  
modulated output with prescaler and an on-chip clock failure detect circuitry.  
270679–1  
Figure 1. 8XC196KB Block Diagram  
*Other brands and names are the property of their respective owners.  
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or  
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make  
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.  
©
COPYRIGHT INTEL CORPORATION, 1995  
February 1995  
Order Number: 270679-005  
AUTOMOTIVE 8XC196KB  
270679–3  
Figure 2. The 8XC196KB Family Nomenclature  
Timer 2 has an independent capture register on ris-  
ing edges of (P2.7)  
ARCHITECTURE  
The 8XC196KB is a member of the 8096 family, as  
such has the same architecture and uses the same  
instruction set as the 8096. Many new features have  
been added on the 8CX196KB including:  
HSO line events are stored in a register  
HSO has CAM lock and CAM clear commands  
New baud rate values are needed for serial port,  
which enables higher speeds in all modes.  
CPU FEATURES  
c
Divide by 2 instead of divide by 3 clock for a 1.5  
performance improvement  
Double buffered serial port transmit register (before,  
only receive was double buffered)  
Faster instructions, especially indexed/indirect data  
operations  
Serial port receive overrun and framing error detec-  
tion  
1.725 ms 16 x 16 multiply with 16 MHz clock (is  
6.25 ms on the 8096)  
PWM has a divide by 2 prescaler  
HOLD/HLDA bus protocol  
Faster interrupt response (almost twice as fast)  
Powerdown and Idle Modes  
THERMAL CHARACTERISTICS  
PLCC  
6 new instructions  
i
i
35 C/W  
§
12 C/W  
§
JA  
JC  
8 new interrupt vectors/6 new interrupt sources  
Max Case  
Temperature  
135 C  
§
PERIPHERAL FEATURES  
SFR window switching allows read-only SFRs to be  
written and vice-versa  
NEW INSTRUCTIONS  
PUSHA PUSHes the PSW, IMASK, IMASK1 and  
WSR (used instead of PUSHF when us-  
ing the new interrupts and registers)  
Timer 2 can count up and down by external selec-  
tion  
POPA  
POPs the PSW, IMASK, IMASK1 and  
WSR (used instead of POPF when using  
the new interrupts and registers)  
2
AUTOMOTIVE 8XC196KB  
IDLPD  
Sets the device into Idle or Powerdown  
Mode. The instruction has the following  
DJNZW* Decrement Jump Not Zero using a word  
counter. The instruction format follows  
the DJNZ instruction.  
e
2 for Powerdown. Illegal  
Ý
format: IDLPD key (where key  
Idle and key  
1 for  
e
*See the Functional Deviations section for details.  
keys are processed, but no action is tak-  
en.  
SFR OPERATION  
CMPL  
BMOV  
Compare 2 long direct values. Only the  
direct addressing mode is supported for  
this instruction and the format follows the  
CMP format.  
All of the registers that were present on the 8096  
work the same way as they did, except that the baud  
rate value will be different on the 8XC196KB. The  
new registers shown in the memory map control new  
functions. The most important register is the Window  
Select Register (WSR) which allows the reading of  
the formerly write-only registers, and vice-versa.  
Block move using 2 auto-incrementing  
pointers and a counter. The instruction  
has the following format: BMOV  
IPTR.wCNT. The IPTR is a long word,  
with the low word being the address of  
the source and the upper word being the  
address of the destination. wCNT is the  
number of words to be transferred.  
PACKAGING  
The 8XC196KB is available in 68-pin plastic leaded  
chip carrier (PLCC) and 68-pin CERQUAD pack-  
ages. Contact your local sales office to determine  
the exact ordering code for the part desired.  
270679–2  
Figure 3. 68-Pin PLCC Package  
3
AUTOMOTIVE 8XC196KB  
PLCC  
Description  
PLCC  
Description  
READY  
9
ACH7/PO.7/PMD3  
ACH6/PO.6/PMD2  
ACH2/PO.2  
ACH0/PO.0  
ACH1/PO.1  
ACH3/PO.3  
NMI  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
8
T2RST/P2.4/AINC  
BHE/WRH  
WR/WRL  
7
6
5
PWM/P2.5  
P2.7/T2CAPTURE/PACT  
4
3
V
V
PP  
SS  
2
EA  
1
V
V
HSO.3  
HSO.2  
P2.6  
CC  
SS  
XTAL1  
XTAL2  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
P1.7/HOLD  
P1.6/HLDA  
P1.5/BREQ  
HSO.1  
CLKOUT  
BUSWIDTH  
INST  
ALE/ADV  
RD  
HSO.0  
HSO.5/HSI.3/SID3  
HSO.4/HSI.2/SID2  
HSI.1/SID1  
HSI.0/SID0  
P1.4  
AD0/P3.0  
AD1/P3.1  
AD2/P3.2  
AD3/P3.3  
AD4/P3.4  
AD5/P3.5  
AD6/P3.6  
AD7/P3.7  
AD8/P4.0  
AD9/P4.1  
AD10/P4.2  
AD11/P4.3  
AD12/P4.4  
AD13/P4.5  
AD14/P4.6  
AD15/P4.7  
T2CLK/P2.3  
P1.3  
P1.2  
P1.1  
P1.0  
TXD/P2.0/PVER  
RXD/P2.1/PALE  
RESET  
EXTINT/P2.2/PROG  
V
V
SS  
REF  
ANGND  
ACH4/P0.4/PMD0  
ACH4/P0.5/PMD1  
Figure 4. PLCC Functional Pinouts  
4
AUTOMOTIVE 8XC196KB  
PIN DESCRIPTIONS  
Symbol  
Name and Function  
a
Main Supply Voltage ( 5V)  
V
V
V
CC  
Digital Circuit Ground (0V). There are three V pins, all of which MUST be connected.  
SS  
SS  
a
Reference for the A/D Converter ( 5V). V  
is also the supply voltage to the analog portion  
REF  
REF  
of the A/D converter and the logic used to read Port 0. Must be connected for A/D and Port 0  
to function.  
ANGND  
Reference Ground for the A/D Converter. Must be held at nominally the same potential as  
.
V
SS  
a
V
PP  
Programming Voltage for the EPROM Parts. It should be 12.75V for programming. This pin  
was V on 8X9X-90 parts. It is also the timing pin for the return from powerdown circuit.  
BB  
Connect this pin with a 1 mF capacitor to V and a 1 MX resistor to V . If this function is not  
SS  
CC  
used, V may be tied to V  
PP  
.
CC  
XTAL1  
Input of the Oscillator Inverter and the Internal Clock Generator  
Output of the Oscillator Inverter  
XTAL2  
CLKOUT  
Output of the Internal Clock Generator. The frequency of CLKOUT is (/2 the oscillator  
frequency. It has a 50% duty cycle.  
RESET  
Reset Input to the Chip. Input low for at least 4 state times will reset the chip. The subsequent  
low to high transition resynchronizes CLKOUT and commences a 10-state time sequence in  
which the PSW is cleared, a byte is read from 2018H loading the CCB, and a jump to location  
2080H is executed. Input high for normal operation. RESET has an internal pullup.  
BUSWIDTH Input for Bus Width Selection. If CCR bit 1 is a one, this pin selects the buswidth for the bus  
cycle in progress. If BUSWIDTH is low, an 8-bit cycle occurs. If BUSWIDTH is high, a 16-bit  
cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus. This pin is the TEST pin on the  
8X9X-90 parts. Systems with TEST tied to V need NOT change.  
CC  
NMI  
A positive transition causes an interrupt vector through external memory location 203EH.  
INST  
Output High during an External Memory Read. Indicates the read is an instruction fetch. INST  
is valid throughout the bus cycle. INST is active only during external memory fetches, during  
internal EPROM/ROM fetches INST is held low.  
EA  
Input for Memory Select (External Access). EA equal to a TTL-high causes memory accesses  
to locations 2000H through 3FFFH to be directed to on-chip EPROM/ROM. EA equal to a  
e
12.75V causes execution to begin in the Programming Mode. EA has an internal pulldown,  
TTL-low causes accesses to these locations to be directed to off-chip memory. EA  
a
so it defaults to execute from external memory, unless otherwise driven. EA is latched at  
reset.  
ALE/ADV  
Address Latch Enable or Address Valid Output, as Selected by CCR. Both pin options provide  
a latch to demultiplex the address from the address/data bus. When the pin is ADV, it goes  
inactive (high) at the end of the bus cycle. ADV can be used as a chip select for external  
memory. ALE/ADV is active only during external memory accesses.  
5
AUTOMOTIVE 8XC196KB  
PIN DESCRIPTIONS (Continued)  
Symbol  
Name and Function  
RD  
Read Signal Output to External Memory. RD is active only during external memory reads.  
WR/WRL  
Write and Write Low Output to External Memory, as Selected by the CCR. WR will go low  
for every external write, while WRL will go low only for external writes where an even byte is  
being written. WR/WRL is active during external memory writes.  
e
BHE/WRH  
Byte High Enable or Write High Output as Selected by the CCR. BHE  
0 selects the bank  
0 selects that bank of  
memory that is connected to the low byte. Thus accesses to a 16-bit wide memory can be  
e
of memory that is connected to the high byte of the data bus. A0  
e
e
e
e
to the low byte only (A0  
0, BHE  
e
0). If the WRH function is selected, the pin will go low if the bus  
1), to the high byte only (A0  
1, BHE  
0) or both  
e
bytes (A0  
0, BHE  
cycle is writing to an odd memory location. BHE/WRH is only valid during 16-bit external  
memory write cycles.  
READY  
Ready Input to lengthen external memory cycles, for interfacing with slow or dynamic  
memory, or for bus sharing. If the pin is high, CPU operation continues in a normal manner.  
If the pin is low prior to the falling edge of CLKOUT, the memory controller goes into a wait  
state mode until the next positive transition in CLKOUT occurs with READY high. When  
external memory is not used, READY has no effect. The number of wait states inserted into  
the bus cycle is controlled by the CCR.  
HSI  
Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2, HSI.3.  
Two of which are shared with the HSO Unit (HSI.2 and HSI.3). The HSI pins are also used  
as the SID in Slave Programming Mode.  
HSO  
Outputs from High Speed Output Unit. Six HSO pins are available (HSO.0 through HSO.5).  
HSO.4 and HSO.5 are shared with HSI.  
PORT 0  
8-Bit High Impedance Input-Only Port. These pins can be used as digital inputs and/or as  
analog inputs to the on-chip A/D converter. These pins are also used as inputs to EPROM  
parts to select the Programming Mode.  
PORT 1  
PORT 2  
8-Bit Quasi-Bidirectional I/O Port.  
8-Bit Multi-Functional Port. All of its pins are shared with other functions.  
PORT 3 and 4 8-Bit Bidirectional I/O Ports with Open Drain Outputs. These pins are shared with the  
multiplexed address/data bus which has strong internal pullups.  
HOLD  
HLDA  
BREQ  
Bus Hold Input Requesting Control of the Bus. Enabled by Setting WSR.7  
Bus Hold Acknowledge Output Indicating Release of the Bus. Enabled by setting WSR.7.  
Bus Request Output. Activated when the bus controller has a pending external memory  
cycle. Enabled by setting WSR.7.  
6
AUTOMOTIVE 8XC196KB  
ELECTRICAL CHARACTERISTICS  
NOTICE: This data sheet contains preliminary infor-  
mation on new products in production. The specifica-  
tions are subject to change without notice. Verify with  
your local Intel Sales office that you have the latest  
data sheet before finalizing a design.  
Absolute Maximum Ratings*  
b
a
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 60 C to 150 C  
§
§
*WARNING: Stressing the device beyond the ‘‘Absolute  
Maximum Ratings’’ may cause permanent damage.  
These are stress ratings only. Operation beyond the  
‘‘Operating Conditions’’ is not recommended and ex-  
tended exposure beyond the ‘‘Operating Conditions’’  
may affect device reliability.  
Voltage from V or EA  
PP  
b
a
to V or ANGND ÀÀÀÀÀÀÀÀÀÀÀÀ 0.5V to 13.0V  
SS  
Voltage on Any Pin  
to V or ANGND ÀÀÀÀÀÀÀÀÀÀÀÀÀ 0.5V to 7.0V  
b
a
SS  
This includes V on ROM and CPU devices.  
PP  
Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W  
OPERATING CONDITIONS  
Symbol  
Parameter  
Ambient Temperature under Bias  
Digital Supply Voltage  
Min  
Max  
Units  
b
a
T
A
40  
125  
5.50  
5.50  
16  
C
§
V
V
4.50  
4.50  
3.5  
V
V
CC  
Analog Supply Voltage  
Oscillator Frequency  
REF  
OSC  
F
MHz  
NOTE:  
ANGND and V should be nominally at the same potential.  
SS  
DC CHARACTERISTICS (Under Listed Operating Conditions)  
Symbol  
Parameter  
Min  
Typ  
Max  
Units  
Test Conditions  
e
I
V
Supply Current  
CC  
a
40 C to 125 C Ambient)  
§
50  
70  
mA XTAL1  
e
16 MHz,  
e
CC  
b
e
e
(
V
V
PP  
V
5.5V  
5.5V  
§
Powerdown Mode Current  
CC  
REF  
e
e
I
I
5
2
mA  
V
V
PP  
V
REF  
PD  
CC  
e
16 MHz,  
A/D Reference  
Supply Current  
5
mA XTAL1  
e
REF  
e
e
e
V
V
PP  
V
REF  
5.5V  
5.5V  
CC  
e
16 MHz,  
I
Idle Mode Current  
10  
35  
mA XTAL1  
e
IDLE  
e
V
V
PP  
V
REF  
CC  
b
a
0.8  
V
V
V
V
Input Low Voltage  
0.5V  
V
V
V
V
IL  
(1)  
a
a
a
a
Input High Voltage  
0.2 V  
1.1  
V
V
V
0.5  
0.5  
0.5  
IH  
CC  
CC  
Input High Voltage on XTAL1  
0.7 V  
CC  
IH1  
IH2  
CC  
CC  
Input on High Voltage  
on RESET  
2.6  
e
e
e
V
V
V
Output Low Voltage  
0.3  
0.45  
1.5  
V
V
V
I
I
I
200 mA  
3.2 mA  
7.0 mA  
OL  
OL  
OL  
OL  
b
b
b
e b  
e b  
e b  
Output High Voltage  
(Standard Outputs)  
V
V
V
0.3  
0.7  
1.5  
V
V
V
I
I
I
200 mA  
3.2 mA  
7.0 mA  
OH  
OH1  
CC  
CC  
CC  
OH  
OH  
OH  
b
b
b
e b  
e b  
e b  
Output High Voltage  
(Quasi-Bidirectional  
Outputs)  
V
CC  
V
CC  
V
CC  
0.3  
0.7  
1.5  
V
V
V
I
I
I
15 mA  
30 mA  
60 mA  
OH  
OH  
OH  
7
AUTOMOTIVE 8XC196KB  
DC CHARACTERISTICS (Under Listed Operating Conditions) (Continued)  
Symbol  
Parameter  
Min  
Typ  
Max  
Units  
Test Conditions  
k
k
b
0.3V  
g
I
I
I
I
I
I
Input Leakage Current  
(Std. Inputs)  
10  
mA  
0
V
V
LI  
IN  
CC  
k
k
g
Input Leakage Current  
(Port 0)  
3
mA  
mA  
mA  
mA  
mA  
0
V
V
LI1  
TL  
IL  
IN  
REF  
b
e
e
e
e
1 to 0 Transition Current  
(QBD Pins)  
800  
V
V
V
V
2.0V  
IN  
IN  
IN  
IN  
b
Logical 0 Input Current  
(QBD Pins)  
50  
0.45V  
0.45V  
0.45V  
b
Logical 0 Input Current  
in Reset (ALE, RD, INST)  
9
IL1  
IL2  
b
Logical 0 Input Current in  
Reset (WR, P2.0, BHE)  
700  
HYST  
Hysteresis on RESET Pin  
Reset Pullup Resistor  
Pin Capacitance  
250  
6K  
mV  
X
R
50  
10  
RST  
e
C
S
pF  
F
1.0 MHz  
TEST  
(Any Pin to V  
)
SS  
NOTES: (Notes apply to all specifications)  
1. All pins except RESET and XTAL1. QBC (Quasi-bidirectional) pins include Port 1, P2.6, P2.7.  
2. Standard Outputs include AD0–15, RD, WR, ALE, BHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Port 3 and 4,  
TXD/P2.0 and RXD (in serial mode 0). The V specification is not valid for RESET. Ports 3 and 4 are open drain outputs.  
OH  
3. Standard Inputs include HSI pins, CDE, EA, READY, BUSWIDTH, NMI, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3 and  
T2RST/P2.4  
4. Maximum current per pin must be externally limited to the following values if V  
b
on Output pins: 10 mA  
is held above 0.45V or V is held  
OH  
OL  
below V  
0.7V:  
CC  
I
I
I
OL  
OL  
OL  
on QBD pins: self limiting  
on Standard Output pins: 10 mA  
g
5. Maximum current per bus pin (data and control) during normal operation is 3.2 mA.  
6. During normal (non-transient) conditions the following total current limits apply:  
Port 1, P2.6  
I : 29 mA  
OL  
I : 29 mA  
OL  
I : 13 mA  
OL  
I : 52 mA  
OL  
I : 13 mA  
OL  
I
I
I
I
I
: is Self Limiting  
: 26 mA  
: 11 mA  
: 52 mA  
: 13 mA  
OH  
OH  
OH  
OH  
OH  
HSO, P2.0, RXD, RESET  
P2.5, P2.7, WR, BHE  
AD0–AD15  
RD, ALE, INST, CLKOUT  
7. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and  
e
e
V
V
CC  
5V.  
REF  
e c
MAX 3.88 Freq
I
I
I
I
CC  
e
c
a
MAX 1.65 Freq 5.2  
TYP 2.5 Freq 8.0  
IDLE  
270679–9  
e
c
a
CC  
e
c
a
TYP 0.5 Freq 3.2  
IDLE  
Figure 5. I vs Frequency  
CC  
8
AUTOMOTIVE 8XC196KB  
AC CHARACTERISTICS Over Specified Operating Conditions  
e
The system must meet these specifications to work with the 8XC196KB  
e
e
OSC  
Test Conditions: Capacitance load on all pins  
100 pF, Rise and fall times  
10 ns, F  
16 MHz  
Units  
Symbol  
Parameter  
Address Valid to READY Setup  
ALE Low to READY Setup  
Non READY Time  
Min  
Max  
b
OSC  
T
T
T
T
T
T
T
T
T
T
T
T
T
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
2 T  
75  
ns  
ns  
ns  
AVYV  
LLYV  
YLYH  
CLYX  
LLYX  
AVGV  
LLGV  
CLGX  
AVDV  
RLDV  
CLDV  
RHDZ  
RXDX  
XTAL  
OSC  
b
T
60  
OSC  
No Upper Limit  
(1)  
b
READY Hold after CLKOUT Low  
READY Hold after ALE Low  
Address Valid to Buswidth Setup  
ALE Low to Buswidth Setup  
Buswidth Hold after CLKOUT Low  
Address Valid to Input Data Valid  
RD Active to Input Data Valid  
CLKOUT Low to Input Data Valid  
End of RD to Input Data Float  
Data hold after RD Inactive  
Oscillator Frequency  
0
T
30  
ns  
ns  
OSC  
(1)  
b
b
T
15  
2 T  
40  
75  
OSC  
OSC  
OSC  
b
2 T  
ns  
b
T
60  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
OSC  
0
b
3 T  
55  
OSC  
b
T
T
T
23  
OSC  
OSC  
OSC  
b
b
50  
20  
0
3.5  
62.5  
20  
16  
Oscillator Period (1/f  
)
286  
110  
XTAL  
(1)  
XTAL1 High to CLKOUT High or LOW  
CLKOUT Period  
XHCH  
CLCL  
CHCL  
CLLH  
LLCH  
LHLH  
LHLL  
AVLL  
LLAX  
LLRL  
RLCL  
RLRH  
RHLH  
2 T  
OSC  
b
a
OSC  
CLKOUT High Period  
T
10  
T
10  
10  
OSC  
b
b
CLKOUT Falling Edge to ALE Rising  
10  
15  
10  
15  
ALE/ADV Falling Edge to CLKOUT Rising  
ALE/ADV Cycle Time  
4 T  
OSC  
b
b
b
b
a
OSC  
ALE/ADV High Period  
T
T
T
T
10  
30  
40  
35  
T
OSC  
OSC  
OSC  
OSC  
Address Setup to ALE/ADV Falling Edge  
Address Hold after ALE/ADV Falling Edge  
ALE/ADV Falling Edge to RD Falling Edge  
RD Low to CLKOUT Falling Edge  
RD Low Period  
4
25  
b
a
T
10  
T
T
25  
25  
OSC  
OSC  
OSC  
a
RD Rising Edge to ALE/ADV  
(3)  
Rising Edge  
T
OSC  
T
T
T
T
T
T
RD Low to Address Float  
5
ns  
ns  
ns  
ns  
ns  
ns  
RLAZ  
b
ALE/ADV Falling Edge to WR Falling Edge  
CLKOUT Low to WR Falling Edge  
Data Stable to WR Rising Edge  
CLKOUT High to WR Rising Edge  
WR Low Period  
T
T
T
10  
23  
15  
LLWL  
CLWL  
QVWH  
CHWH  
WLWH  
OSC  
0
25  
b
OSC  
b
5
15  
b
a
OSC  
T
5
OSC  
9
AUTOMOTIVE 8XC196KB  
AC CHARACTERISTICS Over Specified Operating Conditions (Continued)  
e
The system must meet these specifications to work with the 8XC196KB  
e
e
OSC  
Test Conditions: Capacitance load on all pins  
100 pF, Rise and fall times  
10 ns, F  
16 MHz  
Units  
Symbol  
Parameter  
Data Hold after WR Rising Edge  
WR Rising Edge to ALE/ADV  
Min  
Max  
b
T
T
T
T
15  
20  
ns  
ns  
WHQX  
WHLH  
OSC  
b
a
10  
T
OSC  
OSC  
(3)  
Rising Edge  
b
b
T
T
BHE, INST, HOLD after WR, RD Rising Edge  
T
T
15  
30  
ns  
ns  
WHBX  
WHAX  
OSC  
OSC  
AD8–15 Hold after WR/RD  
Rising Edge  
b
b
T
T
BHE, INST HOLD after RD Rising  
AD8–15 HOLD after RD Rising  
T
T
10  
25  
ns  
ns  
RHBX  
RHAX  
OSC  
OSC  
NOTES:  
1. Typical specification, not guaranteed.  
2. Assuming back-to-back bus cycles.  
e
e
e
125 ns at 8 MHz.  
OSC  
T
OSC  
62.5 ns at 16 MHz; T  
100 ns at 10 MHz; T  
OSC  
System Bus Timing  
270679–4  
10  
AUTOMOTIVE 8XC196KB  
Ready/Buswidth Timing  
270679–5  
HOLD/HLDA Timings  
Symbol  
Description  
Min  
Max  
Units  
Notes  
T
HOLD Setup  
80C196KB  
83C196KB  
1
HVCH  
75  
85  
ns  
b
b
T
T
T
CLKOUT Low to HLDA Low  
CLKOUT Low to BREQ Low  
15  
15  
15  
15  
ns  
ns  
CLHAL  
CLBRL  
HALAZ  
HLDA Low to Address Float  
80C196KB  
83C196KB  
15  
20  
ns  
T
T
T
T
T
T
HLDA Low to BHE, INST, RD, WR Float  
CLKOUT Low to HLDA High  
ns  
ns  
ns  
ns  
ns  
ns  
HALBZ  
CLHAH  
CLBRH  
HAHAX  
HAHBV  
CLLH  
b
b
15  
15  
15  
15  
CLKOUT Low to BREQ High  
b
HLDA High to Address No Longer Float  
HLDA High to BHE, INST, RD, WR Valid  
CLKOUT Low to ALE High  
5
b
20  
b
5
15  
NOTE:  
1. To guarantee recognition at next clock.  
11  
AUTOMOTIVE 8XC196KB  
270679–27  
External Clock Drive  
Symbol  
1/T  
Parameter  
Oscillator Frequency  
Min  
3.5  
62.5  
b
Max  
16  
Units  
MHz  
ns  
XLXL  
T
T
T
T
T
Oscillator Period (T  
High Time  
)
OSC  
286  
XLXL  
T
T
51  
51  
ns  
XHXX  
XLXX  
XLXH  
XHXL  
OSC  
b
Low Time  
ns  
OSC  
b
Rise Time  
T
T
73  
73  
ns  
OSC  
b
Fall Time  
ns  
OSC  
EXTERNAL CLOCK DRIVE WAVEFORMS  
270679–6  
12  
AUTOMOTIVE 8XC196KB  
AC TESTING INPUT, OUTPUT WAVEFORMS  
FLOAT WAVEFORMS  
270679–7  
AC Testing inputs are driven at 2.4V for logic ‘‘1’’ and 0.45V for a  
logic ‘‘0’’. Timing measurements are made at 2.0V for a logic ‘‘1’’  
and 0.8V for logic ‘‘0’’.  
270679–8  
For timing purposes a port pin is no longer floating when a 100  
mV change from load voltage occurs and begins to float when a  
100 mV change from the loading V /V level occurs I /I  
OH OL OL OH  
s
g
15 mA.  
Conditions:  
HÐ High  
LÐ Low  
VÐ Valid  
XÐ No Longer Valid DÐ Data  
ZÐ Floating  
Signals:  
AÐ Address LÐ ALE/ADV  
BÐ BHE RÐ RD  
CÐ CLKOUT WÐ WR/WRH/WRI  
XÐ XTAL1  
GÐBuswidth YРReady  
EXPLANATION OF AC SYMBOLS  
Each symbol is two pairs of letters prefixed by ‘‘t’’ for  
time. The characters in a pair indicate a signal and  
its condition, respectively. Symbols represent the  
time between the two signal/condition points.  
AC CHARACTERISTICSÐSERIAL PORTÐSHIFT REGISTER MODE  
SERIAL PORT TIMINGÐSHIFT REGISTER MODE  
e
eb  
a
40 C to 125 C; V  
e
e
g
5.0V 10%; V  
Test Conditions: T  
0.0V; Load Capacitance  
80 pF  
Unit  
§
§
C
CC  
SS  
Symbol  
Parameter  
Min  
Max  
(9)  
T
T
Serial Port Clock Period  
6 T  
/4 T  
ns  
XLXL  
OSC  
OSC  
OSC  
b
b
a
b
50 ns  
OSC  
Serial Port Clock Falling Edge  
(9)  
to Rising Edge  
4 T  
50/2 T  
50 4 T  
50/2 T  
XLXH  
OSC  
OSC  
b
b
T
QVXH  
T
XHQX  
T
XHQV  
Output Data Setup to Clock Rising Edge  
Output Data Hold after Clock Rising Edge  
2 T  
50  
50  
ns  
ns  
ns  
OSC  
OSC  
2 T  
a
Next Output Data Valid  
after Clock Rising Edge  
2 T  
50  
OSC  
a
OSC  
T
T
T
Input Data Setup to Clock Rising Edge  
Input Data Hold after Clock Rising Edge  
Last Clock Rising to Output Float  
T
50  
ns  
ns  
ns  
DVXH  
(8)  
0
XHDX  
XHQZ  
(8)  
T
OSC  
NOTES:  
8. Parameter not tested.  
t
e
9. Baud Rate Register  
8002H/Baud Rate Register  
8001H.  
13  
AUTOMOTIVE 8XC196KB  
The converter is ratiometric, so the absolute accura-  
cy is directly dependent on the accuracy and stability  
A to D CHARACTERISTICS  
of V  
. V  
must be close to V since it supplies  
There are two modes of A/D operation: with and  
without clock prescaler. The modes are shown in the  
table below. In mode 2, with the clock prescaler dis-  
abled, the maximum XTAL1 frequency is 8.0 MHz.  
Accuracy will degrade at higher frequencies in this  
mode. The frequency divider option is provided to  
obtain higher accuracy outside of the currently spec-  
ified operating conditions.  
REF REF CC  
both the resister ladder and the digital section of the  
converter.  
A/D Converter Specifications  
The specifications given below assume adherence  
to the operating conditions section of this data  
e
sheet. Testing is performed in mode 2 with V  
5.12V and 8 MHz operating clock frequency.  
REF  
WAVEFORMÐSERIAL PORTÐSHIFT REGISTER MODE  
SERIAL PORT WAVEFORMÐSHIFT REGISTER MODE  
270679–28  
Clock Prescaler ON  
e
Clock Prescaler OFF  
e
1
IOC2.4  
0
IOC2.4  
Mode 1Ð 158 States for Execution Mode 2Ð 91 States for Execution  
@
22.75 ms 8 MHz (Maximum)  
@
26.33 ms 12 MHz  
NOTE:  
IOC2.3  
e
0, The No Sample and Hold feature is not available on the 8XC196KB device.  
14  
AUTOMOTIVE 8XC196KB  
(1)  
Parameter  
Resolution  
Typical*  
Minimum  
Maximum  
Units**  
512  
9
1024  
10  
Level  
Bits  
g
Absolute Error  
0
6
LSBs  
LSBs  
LSBs  
LSBs  
LSBs  
LSBs  
g
0.25 0.5  
Full Scale Error  
b
g
0.25 0.5  
Zero Offset Error  
Non-Linearity  
g
1.5 2.5  
g
a
0
4
2
1
l
b
Differential Non-Linearity  
Channel-to-Channel Matching  
Repeatability  
1
g
g
0.1  
0
(1)  
LSBs  
g
0.25  
Temperature Coefficients:  
Offset  
Full Scale  
(1)  
0.009  
0.009  
0.009  
LSB/C  
LSB/C  
LSB/C  
(1)  
(1)  
Differential Non-Linearity  
(1, 2, 4)  
(1, 2)  
dB  
b
Off Isolation  
Feedthrough  
60  
dB  
b
b
60  
60  
(1, 2)  
(1)  
V
Power Supply Rejection  
dB  
CC  
Input Resistance  
1K  
5K  
3
X
DC Input Leakage  
0
mA  
Sample Time (Prescaler on/off)  
Input Capacitance  
15/8  
3
States (3)  
pF  
NOTES:  
*These values are expected for most parts at 25 C but are not tested or guaranteed.  
§
**An ‘‘LSB’’, as used here, has a value of approximately 5 mV. (See Automotive Handbook, for A/D glossary of terms.  
1. These values are not tested in production and are based on theoretical estimates and/or laboratory test.  
2. DC to 100 KHz.  
@ @  
e
3. One state 125 ns 16 MHz; 333 ns 6 MHz.  
4. Multiplexer Break-Before-Make Guaranteed.  
If the first two events into an empty FIFO (not  
including the Holding Register) occur in the same  
internal phase, both are recorded with one time-  
tag. Otherwise, if the second event occurs within  
9 states after the first, its time-tag is one count  
later than the first’s. If this is the ‘‘skipped’’ time  
value, the second event’s time-tag is 2 counts lat-  
er than the first’s.  
80C196KB FUNCTIONAL DEVIATIONS  
The 80C196KB has the following problems.  
1. The HSI unit has two errata: one dealing with res-  
olution and the other with first entries into the  
FIFO.  
The HSI resolution is 9 states instead of 8 states.  
Events on the same line may be lost if they occur  
faster than once every 9 state times.  
If the FIFO and Holding Register are empty, the  
first event will transfer into the Holding Register  
after 8 state times, leaving the FIFO empty again.  
If the second event occurs after this time, it will  
act as a new first event into an empty FIFO.  
There is a mismatch between the 9 state time HSI  
resolution and the 8 state time timer. This causes  
one time value to be unused every 9 timer counts.  
Events may receive a time-tag one count later  
than expected because of this ‘‘skipped’’ time val-  
ue.  
2. If an A/D conversion in progress is aborted by  
starting a new A/D conversion, results of the sec-  
ond conversion may be inaccurate.  
15  
AUTOMOTIVE 8XC196KB  
The work-around is to wait for the conversion in  
progress to finish before starting the second con-  
version. Polling or an interrupt will detect the con-  
version completion.  
4. Make sure all inputs are tied high or low and not  
left floating.  
5. Indexed and indirect operations relative to the  
stack pointer (SP) work differently on the  
80C196KB than on the 8096BH. On the 8096BH,  
the address is calculated based on the un-updat-  
ed version of the stack pointer. The 80C196KB  
3. If the unsigned divide instruction (word or byte) is  
in the queue as HOLD or READY is asserted, the  
result may be incorrect. TechBit (MC1791).  
(B-step only.)  
[
]
and POP nn SP instructions may need to be  
uses the updated version. The offset for POP SP  
[
]
changed by a count of 2.  
DIFFERENCES BETWEEN THE  
80C196KA AND THE 80C196KB  
6. The V  
V
pin on the 8096BH has changed to a  
pin on the 80C196KB.  
PD  
SS  
The 8XC196KB is identical to 8XC196KA except for  
the following differences.  
OTHER DESIGN CONSIDERATIONS  
(KB B-0 to KB C-1)  
1. The NMI pin on the KB ROM (C-1) has a weak  
1. ALE is high after reset on the 80C196KB instead  
of low as on the 80C196KA.  
2. The DJNZW instruction is not guaranteed to work  
on the 80C196KB. (A-step only.)  
pulldown. I  
max is 100 mA. The KB ROM (B-0)  
IH1  
did not have a pulldown on NMI. If KB ROM (B-0)  
designs have NMI tied to V , the NMI pin must  
be tied to V . If NMI is tied to V or is floating,  
CC  
3. The HOLD/HLDA bus protocol is available on the  
80C196KB.  
SS  
SS  
it is okay.  
2. The ALE, RD, and INST pins on the KB ROM  
(C-1) have stronger pullups during RESET than  
CONVERTING FROM OTHER 8096BH  
FAMILY PRODUCTS TO THE  
80C196KB  
b
is 7 mA on the KB  
1.2 mA on the KB  
on the KB ROM (B-0). I  
IL1  
ROM (C-1) compared to  
b
ROM (B-0). Designs which pull these pins low to  
enter ONCE mode must have strong enough pull-  
downs to overcome the pullups.  
The following list of suggestions for designing an  
809XBH system will yield a design that is easily con-  
verted to the 80C196KB.  
3. Pin on the PLCC package on the KB ROM (B-0)  
was the CDE pin. That function did not work so  
the pin was assigned to V . On the KB ROM  
1. Do not base critical timing loops on instruction or  
peripheral execution times.  
SS  
(C-1) this pin is tied directly to V on the device  
SS  
and MUST be tied to V externally.  
SS  
2. Use equate statements to set all timing parame-  
ters, including the baud rate.  
4. Several AC/DC specifications have changed.  
(See Data Sheet Revision History; review them  
carefully.)  
3. Do not base hardware timings on CLKOUT or  
XTAL1. The timings of the 80C196KB are differ-  
ent than those of the 8X9XBH, but they will func-  
tion with standard ROM/EPROM/Peripheral type  
memory systems.  
16  
AUTOMOTIVE 8XC196KB  
b
min/max has changed from 5 ns/15 ns  
21. T  
CLLH  
DATA SHEET REVISION HISTORY  
b
to 10 ns/10 ns.  
This is the -005 revision of the 8XC196KB data  
sheet and is valid for devices marked with a ‘‘F’’ or  
‘‘G’’ at the end of the topside tracking number. The  
following differences exist between the -004 revision  
and the -005 revision:  
22. T  
LHLL  
g
min/max has changed from  
T
20 ns to T  
40 ns to T  
OSC  
OSC  
OSC  
g
12 ns to T  
10 ns.  
OSC  
b
b
23. T  
has changed from T  
AVLL  
LLRL  
RLCL  
OSC  
OSC  
b
30 ns.  
24. T  
has changed from T  
1. All performance related data is now quoted at  
16 MHz. The maximum clock rate has changed  
from 12 MHz to 16 MHz.  
b
35 ns.  
25. T  
min/max has changed from 5 ns/30 ns  
to 4 ns/25 ns.  
2. Max power dissipation changes from 0.43W to  
1.5W.  
b
26. T has changed from T  
RLRH  
5 ns to T  
OSC  
OSC  
b
10 ns.  
3. I  
4. I  
5. I  
6. I  
max has changed from 60 mA to 70 mA.  
typical has changed from 40 mA to 50 mA.  
CC  
27. T  
has changed from 12 ns to 5 ns.  
RLAZ  
CC  
b
min/max has changed from 10 ns/  
28. T  
CHWH  
10 ns to 5 ns/15 ns.  
typical has changed from 1 mA to 2 mA.  
has changed from 25 mA to 35 mA.  
min has changed from 2.4V to 2.5V.  
REF  
IDLE  
b
b
29. T  
min/max has changed from T  
OSC  
WLWH  
30 ns to T  
7. V  
b
IH2  
15 ns.  
OSC  
b
CC  
8. V  
test condition for V  
b
0.3V has changed  
b
has changed from T  
OSC  
15 ns.  
OH1  
30. T  
T
10 ns to  
WHQX  
b
from 7 mA to 15 mA.  
b
OSC  
b
b
9. I has changed from 650 mA to 800 mA.  
TL  
b
a
31. T  
WHLH  
10 ns/T  
10 ns.  
min/max has changed from T  
OSC  
a
b
b
b
15 ns to T  
20 ns/T  
10. I  
has changed from 1.2 mA to 9 mA.  
now only applies to ALE, RD and INST.  
OSC  
OSC  
OSC  
IL1  
IL1  
11. I  
b
b
b
32. T  
WHBX  
T
has changed from T  
15 ns.  
10 ns to  
50 ns to  
50 ns to  
OSC  
OSC  
OSC  
12. R  
max has changed from 100 KX to 50 KX.  
RST  
b
OSC  
13. Added spec for RESET pin hysteresis and I  
for WR, P2.0, and BHE.  
IL2  
33. T  
T
has changed from T  
30 ns.  
WHAX  
b
OSC  
b
OSC  
14. T  
has changed from 2 T  
b
85 ns to  
AVYV  
LLYV  
AVGV  
34. T  
T
has changed from T  
25 ns.  
RHAX  
OSC  
2 T  
75 ns.  
OSC  
b
b
15. T  
has changed from T  
72 ns to T  
OSC  
OSC  
35. Functional deviation number 1 has been re-  
moved (DJWZ is now functional).  
b
60 ns.  
b
b
16. T  
17. T  
18. F  
has changed from 2 T  
b
85 ns to  
OSC  
36. Functional deviation number 3 has been re-  
moved (SIO framing flag now works correctly).  
2 T  
75 ns.  
OSC  
has changed from 3 T  
b
65 ns to  
AVDV  
3 T  
OSC  
37. Functional deviation number 5 has been re-  
moved (SIO RI now correctly generated).  
55 ns.  
OSC  
max has changed from 12 MHz to  
XTAL  
38. Functional deviation number 6 has been cor-  
rected. The divide during HOLD bug has been  
fixed.  
16 MHz.  
19. T  
min has changed from 83 ns to 62.5 ns.  
OSC  
20. T  
min has changed from 40 ns to 20 ns.  
XHCH  
39. The section ‘‘Other Design Considerations KB  
B-0 to KB C-1’’ has been added.  
17  
厂商 型号 描述 页数 下载

INTEL

 		8XC151SA 高性能CHMOS微控制器[ HIGH-PERFORMANCE CHMOS MICROCONTROLLER ] 33 页

INTEL

 		8XC151SB 高性能CHMOS微控制器[ HIGH-PERFORMANCE CHMOS MICROCONTROLLER ] 33 页

INTEL

 		8XC152JA 通用通信控制器8位微控制器[ UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER ] 17 页

INTEL

 		8XC152JB 通用通信控制器8位微控制器[ UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER ] 17 页

INTEL

 		8XC152JC 通用通信控制器8位微控制器[ UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER ] 17 页

INTEL

 		8XC152JD 通用通信控制器8位微控制器[ UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER ] 17 页

INTEL

 		8XC196JQ 商业/ EXPRESS CHMOS单片机[ COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER ] 25 页

INTEL

 		8XC196JR 商业/ EXPRESS CHMOS单片机[ COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER ] 25 页

INTEL

 		8XC196KB16 商业/ EXPRESS CHMOS单片机[ COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER ] 22 页

INTEL

 		8XC196KC 商业/ EXPRESS CHMOS单片机[ COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER ] 25 页

购物指南

支付方式

配送服务

售后服务

发票须知

优惠券使用规则

特色服务

PCBA制造

国产品牌推荐

国产料号替代

质量保证

技术资料

行业资讯

关于我们

关于达普

联系我们

联系我们

服务热线：400-618-9990

企业邮箱：smail@ic72.com

服务时间：周一至周六 8:30-17:30

达普官方微信号

PDF索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

IC型号索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

Copyright 2024 gkzhan.com Al Rights Reserved 京ICP备06008810号-21 京

深圳网络警察报警平台
公共信息安全网络监察
经营性网站备案信息
不良信息举报中心
工商网监电子标识
全国公安机关备案
0.239775s