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8XC151SB

型号：

8XC151SB

描述：

高性能CHMOS微控制器[ HIGH-PERFORMANCE CHMOS MICROCONTROLLER ]

品牌：

INTEL[ INTEL ]

页数：

33 页

PDF大小：

593 K

下载PDF手册
8XC151SA/SB  
HIGH-PERFORMANCE  
CHMOS MICROCONTROLLER  
Commercial/Express  
Y
Y
Y
MCS 51 Microcontroller Compatible  
É
Power Management  
Ð Idle Mode  
Ð Powerdown Mode  
Instruction Set  
Pin Compatible with 44-lead PLCC and  
40-lead PDIP MCS 51 Sockets  
Y
Y
32 Programmable I/O Lines  
Y
Y
Y
Fast Instruction Pipeline  
16-bit Internal Code Fetch  
Seven Maskable Interrupt Sources with  
Four Programmable Priority Levels  
Y
Y
Y
Three Flexible 16-bit Timer/counters  
Hardware Watchdog Timer  
8-bit, Min 2-clock External Code Fetch  
in Page Mode  
Y
User-selectable Configurations:  
Ð External Wait States (0-3 wait states)  
Ð Page Mode  
Programmable Counter Array  
Ð High-speed Output  
Ð Compare/Capture Operation  
Ð Pulse Width Modulator  
Ð Watchdog Timer  
Y
Y
Y
64K External Code Memory Space  
64K External Data Memory Space  
Y
Programmable Serial I/O Port  
Ð Framing Error Detection  
Ð Automatic Address Recognition  
ROM/OTPROM Options:  
8 Kbytes (SA), 16 Kbytes (SB)  
or without ROM/OTPROM  
Y
Y
Y
High-performance CHMOS Technology  
Static Standby to 16-MHz Operation  
Package Options (PDIP, PLCC)  
Y
256 Bytes On-Chip RAM  
The 8XC151SA/SB has an MCS 51 microcontroller compatible instructon set. It is available in 40-pin PDIP and  
44-lead PLCC compatible with the MCS 51 microcontroller. The 8XC151SA/SB has 256 bytes of on-chip RAM  
and is available in 8/16 Kbytes of on-chip ROM/OTPROM or without ROM/OTPROM. A variety of new  
features such as programmable wait states, page mode and extended ALE can be selected using the new  
user-programmable configuration.  
*Other brands and names are the property of their respective owners.  
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or  
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make  
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.  
©
COPYRIGHT INTEL CORPORATION, 1996  
March 1996  
Order Number: 272814-001  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
272814–1  
Figure 1. 8XC151SA/SB Block Diagram  
2
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
TEMPERATURE RANGE  
PROCESS INFORMATION  
With the commercial (standard) temperature option,  
the device operates over the temperature range 0 C  
This device is manufactured on a complimentary  
metal-oxide  
(CHMOS) process. Additional process and reliability  
information is available in Intel’s Components Quali-  
ty and Reliability Handbook (order number 210997).  
high-performance  
semiconductor  
§
a
to 70 C. The express temperature option provides  
§
b
a
40 C to 85 C device operation.  
§
§
All thermal impedance data is approximate for static  
air conditions at 1 watt of power dissipation. Values  
change depending on operating conditions and ap-  
plication requirements. The Intel Packaging Hand-  
book (order number 240800) describes Intel’s ther-  
mal impedance test methodology.  
PROLIFERATION OPTIONS  
Table 1 lists the proliferation options. See Figure 2  
for the 8XC151SA/SB family nomenclature.  
Table 1. Proliferation Options  
8XC151SA/SB  
Table 2. Thermal Characteristics  
g
(0 MHz–16 MHz; 5V 10%)  
Package Type  
44-Lead PLCC  
40-Pin PDIP  
i
i
JC  
JA  
80C151SB  
CPU-only  
46 C/W  
§
45 C/W  
§
16 C/W  
§
16 C/W  
§
83C151SA  
83C151SB  
87C151SA  
87C151SB  
8K ROM  
16K ROM  
8K OTPROM  
16K OTPROM  
PACKAGE OPTIONS  
Table 3 lists the 8XC151SA/SB packages.  
Table 3. Package Information  
Pkg.  
N
Definition  
Temperature  
a
0 C to 70 C  
44-Lead PLCC  
40-Pin Plastic DIP  
44-Lead PLCC  
40-Pin Plastic DIP  
§
§
a
0 C to 70 C  
P
§
§
b
b
a
40 C to 85 C  
TN  
TP  
§
§
a
40 C to 85 C  
§
§
3
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
272814–2  
Figure 2. The 8XC151SA/SB Family Nomenclature  
Table 4. Description of Product Nomenclature  
Parameter  
Options  
Description  
Commercial operating temperature range (0 C to 70 C) with Intel  
standard burn-in.  
Temperature and Burn-in  
Options  
no mark  
§
§
b
Express operating temperature range ( 40 C to 85 C) with Intel  
standard burn-in.  
T
§
§
Packaging Options  
N
44-lead Plastic Leaded Chip Carrier (PLCC)  
40-pin Plastic Dual In-line Package (PDIP)  
Without ROM/OTPROM  
ROM  
P
Program Memory  
Options  
0
3
7
User programmable OTPROM  
CHMOS  
Process Information  
Product Family  
C
151  
SA/SB  
8-bit controller architecture  
Device Memory Options  
256 bytes RAM/8/16 Kbyte ROM/OTPROM or without ROM/  
OTPROM  
Device Speed  
16  
External clock frequency  
4
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
272814–3  
Figure 3. 8XC151SA/SB 44-Lead PLCC Package  
5
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
272814–4  
Figure 4. 8XC151SA/SB 40-Pin PDIP and Ceramic DIP Packages  
6
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
Table 5. PLCC/DIP Signal Assignment Arranged by Functional Categories  
Address & Data  
Input/Output  
Name  
PLCC  
43  
42  
41  
40  
39  
38  
37  
36  
24  
25  
26  
27  
28  
29  
30  
31  
DIP  
39  
38  
37  
36  
35  
34  
33  
32  
21  
22  
23  
24  
25  
26  
27  
28  
Name  
PLCC  
2
DIP  
1
AD0/P0.0  
AD1/P0.1  
AD2/P0.2  
AD3/P0.3  
AD4/P0.4  
AD5/P0.5  
AD6/P0.6  
AD7/P0.7  
A8/P2.0  
P1.0/T2  
P1.1/T2EX  
P1.2/ECI  
P1.3/CEX0  
P1.4/CEX1  
P1.5/CEX2  
P1.6/CEX3  
P1.7/CEX4  
P3.0/RXD  
P3.1/TXD  
P3.4/T0  
3
2
4
3
5
4
6
5
7
6
8
7
9
8
11  
13  
16  
17  
10  
11  
14  
15  
A9/P2.1  
A10/P2.2  
A11/P2.3  
A12/P2.4  
A13/P2.5  
A14/P2.6  
A15/P2.7  
P3.5/T1  
Power & Ground  
Name  
PLCC  
44  
DIP  
40  
Ð
V
CC  
V
V
V
V
12  
CC2  
SS  
Processsor Control  
PLCC  
22  
20  
Ð
Name  
P3.2/INT0  
P3.3/INT1  
DIP  
12  
13  
31  
9
1
SS1  
SS2  
Ý
Ý
14  
15  
35  
10  
21  
20  
23, 34  
35  
Ð
Ý
EA /V  
31  
PP  
Ý
EA /V  
PP  
Bus Control & Status  
PLCC  
RST  
Name  
DIP  
16  
17  
30  
29  
XTAL1  
XTAL2  
18  
19  
Ý
P3.6/WR  
18  
19  
33  
32  
Ý
P3.7/RD  
Ý
ALE/PROG  
Ý
PSEN  
7
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
Table 6. Signal Assignments Arranged by Package Number  
PLCC  
1
DIP  
Ð
1
Name  
PLCC  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
DIP  
Ð
Name  
V
V
SS2  
SS1  
2
P1.0/T2  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
Ð
A8/P2.0  
3
2
P1.1/T2EX  
P1.2/ECI  
P1.3/CEX0  
P1.4/CEX1  
P1.5/CEX2  
P1.6/CEX3  
P1.7/CEX4  
RST  
A9/P2.1  
4
3
A10/P2.2  
A11/P2.3  
A12/P2.4  
A13/P2.5  
A14/P2.6  
A15/P2.7  
5
4
6
5
7
6
8
7
9
8
Ý
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
9
PSEN  
Ý
10  
Ð
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
P3.0/RXD  
ALE/PROG  
V
V
SS2  
CC2  
Ý
EA /V  
pp  
P3.1/TXD  
P3.2/INT0  
P3.3/INT1  
P3.4/T0  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
Ý
Ý
AD7/P0.7  
AD6/P0.6  
AD5/P0.5  
AD4/P0.4  
AD3/P0.3  
AD2/P0.2  
AD1/P0.1  
AD0/P0.0  
P3.5/T1  
Ý
P3.6/WR  
Ý
P3.7/RD  
XTAL2  
XTAL1  
V
V
CC  
SS  
8
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
SIGNAL DESCRIPTIONS  
Table 7. Signal Descriptions  
Signal  
Name  
Multiplexed  
With  
Type  
Description  
²
A15:8  
O
Address Lines. Upper address lines for the external bus.  
P2.7:0  
P0.7:0  
²
AD7:0  
I/O  
Address/Data Lines. Multiplexed lower address lines and data lines  
for external memory.  
Ý
PROG  
ALE  
O
Address Latch Enable. ALE signals the start of an external bus  
cycle and indicates that valid address information is available on lines  
A15:8 and AD7:0. An external latch can use ALE to demultiplex the  
address from the address/data bus.  
CEX4:0  
I/O  
I
Programmable Counter Array (PCA) Input/Output Pins. These  
are input signals for the PCA capture mode and output signals for the  
PCA compare mode and PCA PWM mode.  
P1.6:3  
P1.7  
Ý
EA  
External Access. Directs program memory accesses to on-chip or  
V
PP  
e
Ý
off-chip code memory. For EA  
0, all program memory accesses  
1, an access is to on-chip ROM/OTPROM if  
the address is within the range of the on-chip ROM/OTPROM;  
e
Ý
are off-chip. For EA  
Ý
otherwise the access is off-chip. The value of EA is latched at  
reset. For devices without on-chip ROM/OTPROM, EA must be  
Ý
strapped to ground.  
ECI  
I
I
PCA External Clock Input. External clock input to the 16-bit PCA  
timer.  
P1.2  
Ý
INT1:0  
External Interrupts 0 and 1. These inputs set bits IE1:0 in the TCON  
register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by  
P3.3:2  
Ý
a falling edge on INT1 /INT0 . If bits INT1:0 are clear, bits IE1:0  
are set by a low level on INT1:0  
Ý
Ý
.
Ý
PROG  
P0.7:0  
I
Programming Pulse. The programming pulse is applied to this pin  
for programming the on-chip OTPROM.  
ALE  
I/O  
I/O  
Port 0. This is an 8-bit, open-drain, bidirectional I/O port.  
AD7:0  
P1.0  
P1.1  
Port 1. This is an 8-bit, bidirectional I/O port with internal pullups.  
T2  
T2EX  
ECI  
P1.2  
P1.7:3  
CEX3:0  
CEX4  
P2.7:0  
I/O  
Port 2. This is an 8-bit, bidirectional I/O port with internal pullups.  
A15:8  
²
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (compatible with  
44-lead PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page-mode operation, port 0 carries  
the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0).  
9
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
Table 7. Signal Descriptions (Continued)  
Signal  
Multiplexed  
With  
Type  
Description  
Name  
P3.0  
P3.1  
I/O  
Port 3. This is an 8-bit, bidirectional I/O port with internal pullups.  
RXD  
TXD  
Ý
P3.3:2  
P3.5:4  
P3.6  
INT1:0  
T1:0  
Ý
WR  
Ý
RD  
P3.7  
Ý
PSEN  
O
Program Store Enable. Read signal output. This output is asserted  
for a memory address range that depends on bits RD0 and RD1 in  
configuration byte UCONFIG0.  
Ð
Ý
RD  
O
I
Read. Read signal output to external data memory.  
P3.7  
Ð
RST  
Reset. Reset input to the chip. Holding this pin high for 64 oscillator  
periods while the oscillator is running resets the device. The port pins  
are driven to their reset conditions when a voltage greater than V  
applied, whether or not the oscillator is running. This pin has an  
internal pulldown resistor, which allows the device to be reset by  
is  
IH1  
connecting a capacitor between this pin and V  
.
CC  
Asserting RST when the chip is in idle mode or powerdown mode  
returns the chip to normal operation.  
RXD  
T1:0  
T2  
I/O  
I
Receive Serial Data. RXD sends and receives data in serial I/O  
mode 0 and receives data in serial I/O modes 1, 2, and 3.  
P3.0  
P3.5:4  
P1.0  
Timer 1:0 External Clock Inputs. When timer 1:0 operates as a  
counter, a falling edge on the T1:0 pin increments the count.  
I/O  
Timer 2 Clock Input/Output. For the timer 2 capture mode, this  
signal is the external clock input. For the clock-out mode, it is the  
timer 2 clock output.  
T2EX  
TXD  
I
Timer 2 External Input. In timer 2 capture mode, a falling edge  
initiates a capture of the timer 2 registers. In auto-reload mode, a  
falling edge causes the timer 2 registers to be reloaded. In the up-  
down counter mode, this signal determines the count direction:  
P1.1  
e
e
1
up, 0  
down.  
O
Transmit Serial Data. TXD outputs the shift clock in serial I/O mode  
0 and transmits serial data in serial I/O modes 1, 2, and 3.  
P3.1  
a
Supply Voltage. Connect this pin to the 5V supply voltage.  
V
V
PWR  
PWR  
Ð
Ð
CC  
Secondary Supply Voltage 2. This supply voltage connection is  
provided to reduce power supply noise. Connection of this pin to the  
CC2  
a
5V supply voltage is recommended. However, when using the  
8XC151SA/SB as a pin-for-pin replacement for the 8XC51FX, V  
SS2  
can be unconnected without loss of compatibility. (Not available on  
DIP)  
Ý
EA  
V
I
Programming Supply Voltage. The programming supply voltage is  
applied to this pin for programming the on-chip OTPROM.  
PP  
²
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (compatible with  
44-lead PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page-mode operation, port 0 carries  
the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0).  
10  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
Table 7. Signal Descriptions (Continued)  
Signal  
Name  
Multiplexed  
Type  
Description  
With  
V
V
GND  
GND  
Circuit Ground. Connect this pin to ground.  
Ð
SS  
Secondary Ground. This ground is provided to reduce ground bounce  
and improve power supply bypassing. Connection of this pin to ground  
is recommended. However, when using the 8XC151SA/SB as a pin-  
SS1  
for-pin replacement for the 8XC51BH, V  
without loss of compatibility. (Not available on DIP)  
can be unconnected  
SS1  
V
GND  
Secondary Ground 2. This ground is provided to reduce ground  
bounce and improve power supply bypassing. Connection of this pin to  
ground is recommended. However, when using the 8XC151SA/SB as  
SS2  
a pin-for-pin replacement for the 8XC51FX, V  
without loss of compatibility. (Not available on DIP)  
can be unconnected  
SS2  
Ý
WR  
O
I
Write. Write signal output to external memory.  
P3.6  
XTAL1  
Input to the On-chip, Inverting, Oscillator Amplifier. To use the  
internal oscillator, a crystal/resonator circuit is connected to this pin. If  
an external oscillator is used, its output is connected to this pin. XTAL1  
is the clock source for internal timing.  
XTAL2  
O
Output of the On-chip, Inverting, Oscillator Amplifier. To use the  
internal oscillator, a crystal/resonator circuit is connected to this pin. If  
an external oscillator is used, leave XTAL2 unconnected.  
Ð
²
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (compatible with  
44-lead PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page-mode operation, port 0 carries  
the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0).  
11  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
ELECTRICAL CHARACTERISTICS  
NOTICE: This document contains information on  
products in the design phase of development. Do not  
finalize a design with this information. Revised infor-  
mation will be published when the product is avail-  
able. Verify with your local Intel Sales office that you  
have the latest data sheet before finalizing a design.  
ABSOLUTE MAXIMUM RATINGS*  
Ambient Temperature under Bias:  
CommercialÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0 C to 70 C  
a
§
§
*WARNING: Stressing the device beyond the ‘‘Absolute  
Maximum Ratings’’ may cause permanent damage.  
These are stress ratings only. Operation beyond the  
‘‘Operating Conditions’’ is not recommended and ex-  
tended exposure beyond the ‘‘Operating Conditions’’  
may affect device reliability.  
b
a
Express ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40 C to 85 C  
§
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C  
§
b
a
§
§
Voltage on EA /V Pin to V ÀÀÀÀÀ0V to 13.0V  
a
Ý
PP  
SS  
b
a
Voltage on Any other Pin to V ÀÀÀ 0.5V to 6.5V  
SS  
I
per I/O Pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA  
OL  
Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W  
NOTE:  
Maximum power dissipation is based on package  
heat-transfer limitations, not device power con-  
sumption.  
OPERATING CONDITIONS*  
T
(Ambient Temperature Under Bias):  
CommercialÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0 C to 70 C  
A
a
§
§
b
a
Express ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40 C to 85 C  
§
§
(Digital Supply Voltage) ÀÀÀÀÀÀÀÀÀÀ4.5V to 5.5V  
V
V
CC  
ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0V  
SS  
12  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
DC CHARACTERISTICS  
Parameter values apply to all devices unless otherwise indicated.  
e
b
4.5V 5.5V  
Table 8. DC Characteristics at V  
CC  
Symbol  
Parameter  
Min  
Typical  
Max  
Units Test Conditions  
b
b
V
V
V
V
V
Input Low Voltage  
Ý
0.5  
0.2V  
0.2V  
0.1  
0.3  
V
IL  
CC  
(except EA  
)
b
Input Low Voltage  
Ý
0
V
V
V
IL1  
IH  
CC  
(EA  
)
a
a
0.5  
Input High Voltage  
(except XTAL1, RST)  
0.2V  
0.9  
V
CC  
V
CC  
CC  
a
0.5  
Input High Voltage  
(XTAL1, RST)  
0.7V  
IH1  
OL  
CC  
e
e
e
Output Low Voltage  
(Port 1, 2, 3)  
0.3  
0.45  
1.0  
V
V
V
I
I
I
100 mA  
1.6 mA  
3.5 mA  
OL  
OL  
OL  
(Note 1, Note 2)  
e
e
e
V
V
Output Low Voltage  
(Port 0, ALE, PSEN  
0.3  
0.45  
1.0  
I
I
I
200 mA  
3.2 mA  
7.0 mA  
OL1  
OH  
OL  
OL  
OL  
Ý
)
(Note 1, Note 2)  
b
b
b
e b  
e b  
e b  
Output High Voltage  
(Port 1, 2, 3, ALE,  
V
V
V
0.3  
I
I
I
10 mA  
30 mA  
60 mA  
CC  
CC  
CC  
OH  
OH  
OH  
0.7  
1.5  
Ý
PSEN  
)
(Note 3)  
NOTES:  
1. Under steady-state (non-transient) conditions, I must be externally limited as follows:  
OL  
Maximum I per port pin: 10 mA  
OL  
Maximum I per 8-bit port:  
OL  
port 0  
26 mA  
15 mA  
ports 1–3  
Maximum Total I for  
OL  
all output pins 71 mA  
exceeds the test conditions, V may exceed the related specification. Pins are not guaranteed to sink current  
If I  
OL  
greater than the listed test conditions.  
OL  
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4V on the low-level outputs of ALE and  
ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these  
pins change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these  
signals may exceed 0.8V. It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input  
logic.  
Ý
on ALE and PSEN to drop below the specification when the  
3. Capacitive loading on ports 0 and 2 causes the V  
address lines are stabilizing.  
OH  
e
e
4. Typical values are obtained using V  
5.0, T  
25 C and are not guaranteed.  
§
CC  
A
13  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
e
b
5.5V (Continued)  
Table 8. DC Characteristics at V  
4.5V  
CC  
Symbol  
Parameter  
Min  
Typical  
Max  
Units  
Test Conditions  
b
b
b
e b  
e b  
e b  
V
Output High Voltage  
(Port 0 in External  
Address)  
V
V
V
0.3  
0.7  
1.5  
V
I
I
I
200 mA  
3.2 mA  
7.0 mA  
OH1  
CC  
OH  
OH  
OH  
CC  
CC  
b
b
b
e b  
e b  
e b  
V
Output High Voltage  
(Port 2 in External  
Address during Page  
Mode)  
V
0.3  
0.7  
1.5  
V
I
I
I
200 mA  
3.2 mA  
7.0 mA  
OH2  
CC  
CC  
CC  
OH  
OH  
OH  
V
V
b
g
e
k
I
I
I
Logical 0 Input Cur-  
rent (Port 1, 2, 3)  
50  
10  
mA  
mA  
mA  
V
0.45V  
IL  
IN  
k
V
CC  
Input Leakage Cur-  
rent (Port 0)  
0.45  
V
LI  
IN  
b
e
2.0V  
Logical 1-to-0 Transi-  
tion Current (Port 1,  
2, 3)  
650  
V
TL  
IN  
R
C
RST Pulldown Resistor  
Pin Capacitance  
40  
225  
kX  
RST  
e
10  
(Note 4)  
pF  
F
T
16 MHz  
25 C  
IO  
OSC  
e
§
A
k
I
I
I
Powerdown Current  
Idle Mode Current  
Operating Current  
10  
(Note 4)  
20  
mA  
mA  
mA  
PD  
e
e
13  
(Note 4)  
20  
F
F
16 MHz  
16 MHz  
DL  
CC  
OSC  
OSC  
71  
(Note 4)  
85  
NOTES:  
1. Under steady-state (non-transient) conditions, I must be externally limited as follows:  
OL  
Maximum I per port pin: 10 mA  
OL  
Maximum I per 8-bit port:  
OL  
port 0  
26 mA  
15 mA  
ports 1–3  
Maximum Total I for  
OL  
all output pins 71 mA  
exceeds the test conditions, V may exceed the related specification. Pins are not guaranteed to sink current  
If I  
OL  
greater than the listed test conditions.  
OL  
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4V on the low-level outputs of ALE and  
ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these  
pins change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these  
signals may exceed 0.8V. It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input  
logic.  
Ý
on ALE and PSEN to drop below the specification when the  
3. Capacitive loading on ports 0 and 2 causes the V  
address lines are stabilizing.  
OH  
e
e
4. Typical values are obtained using V  
5.0, T  
25 C and are not guaranteed.  
§
CC  
A
14  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
272814–5  
All other 8XC151SA/SB pins are unconnected.  
Figure 5. I Test Condition, Powerdown Mode, V  
e
CC  
b
5.5V  
2.0V  
PD  
15  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
state, and Notes 4 and 5 mark parameters affected  
AC Characteristics  
Ý
Ý
Ý
by a PSEN /RD /WR wait state.  
Table 8 lists AC timing parameters for the  
8XC151SA/SB with no wait states. External wait  
Figures 5–11 show the bus cycles with the timing  
parameters.  
Ý
Ý
/
states can be added by extending PSEN /RD  
Ý
WR and/or by extending ALE. In the table, Notes  
3 and 5 mark parameters affected by an ALE wait  
e
Table 9. AC Characteristics (Capacitive Loading  
50 pF)  
@
Max F  
(1)  
F
OSC  
Variable  
OSC  
Symbol  
Parameter  
Units  
Min  
N/A  
N/A  
Max  
N/A  
N/A  
Min  
Max  
16  
F
XTAL1 Frequency  
1/F  
0
MHz  
ns  
OSC  
OSC  
T
OSC  
@
12 MHz  
16 MHz  
83.3  
62.5  
@
T
ALE Pulse Width  
@
ns  
(3)  
LHLL  
AVLL  
12 MHz  
16 MHz  
68.3  
47.5  
@
a
(1 2M)  
b
T
15  
OSC  
T
Address Valid to ALE Low  
@
ns  
(3)  
12 MHz  
16 MHz  
58.3  
37.5  
@
a
(1 2M)  
b
T
25  
OSC  
T
T
Address Hold after ALE Low  
@
ns  
LLAX  
12 MHz  
16 MHz  
10  
10  
@
10  
Ý
RD or PSEN Pulse Width  
Ý
(2)  
ns  
(4)  
RLRH  
@
12 MHz  
16 MHz  
151.6  
110  
@
a
2(1 N)  
b
T
T
15  
OSC  
Ý
WR Pulse Width  
T
ns  
(4)  
WLWH  
@
12 MHz  
16 MHz  
151.6  
110  
@
a
2(1 N)  
b
15  
OSC  
Ý
Ý
ALE Low to RD or PSEN Low  
T
T
(2)  
ns  
LLRL  
LHAX  
@
12 MHz  
16 MHz  
58.3  
37.5  
@
b
Tosc  
25  
ALE High to Address Hold  
@
ns  
(3)  
12 MHz  
16 MHz  
83.3  
62.5  
@
a
(1 2M)  
T
OSC  
NOTES:  
1. 16 MHz.  
Ý
Ý
.
3. In the formula, M Number of wait states (0 or 1) for ALE.  
2. Specifications for PSEN are identical to those for RD  
e
e
Ý
Ý
Ý
.
4. In the formula, N Number of wait states (0, 1, 2, or 3) for RD /PSEN /WR  
5. ‘‘Typical’’ specifications are untested and not guaranteed.  
16  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
e
Table 9. AC Characteristics (Capacitive Loading  
50 pF) (Continued)  
(1) Variable  
@
Max F  
Min  
F
OSC  
OSC  
Symbol  
Parameter  
Units  
Max  
Min  
Max  
Ý
(2) RD /PSEN Low to valid Data/Instruction In  
Ý
T
RLDV  
ns  
(4)  
@
12 MHz  
16 MHz  
111.6  
70  
@
a
2(1 N)  
b
T
OSC  
55  
Ý Ý  
(2) RD /PSEN Data/Instruction Hold  
T
T
T
RHDX  
0
0
ns  
ns  
Ý
Ý
after RD and PSEN High  
e
e
Typ. 0  
(5)  
Ý
Ý
(2) RD /PSEN Low to Address Float  
Typ.  
0
2
2
RLAZ  
(5)  
Ý
Ý
Instruction Float after RD /PSEN High  
ns  
ns  
RHDZ1  
@
12 MHz  
16 MHz  
0
0
@
0
Ý
Ý
Data Float after RD /PSEN High  
T
RHDZ2  
@
12 MHz  
16 MHz  
151.6  
110  
@
2T  
OSC  
b
15  
Ý
RD /PSEN High to ALE High (Instruction)  
Ý
T
T
T
T
ns  
ns  
ns  
RHLH1  
RHLH2  
WHLH  
AVDV1  
@
12 MHz  
16 MHz  
0
0
@
0
Ý
RD /PSEN High to ALE High (Data)  
Ý
@
12 MHz  
16 MHz  
156.6  
115  
@
b
10  
2T  
OSC  
Ý
WR High to ALE High  
@
12 MHz  
16 MHz  
166.6  
125  
@
2T  
OSC  
Address (P0) Valid to Valid Data/Instruction In  
@
ns  
(3)  
12 MHz  
16 MHz  
253.2  
170  
@
a
4(1 M/2)  
b
T
80  
OSC  
T
Address (P2) Valid to Valid Data/Instruction In  
@
ns  
(3)  
AVDV2  
AVDV3  
12 MHz  
16 MHz  
268.2  
185  
@
a
4(1 M/2)  
b
T
65  
OSC  
T
Address (P0) Valid to Valid Instruction In  
@
ns  
12 MHz  
16 MHz  
116.6  
75  
@
2T  
OSC  
b
50  
NOTES:  
1. 16 MHz.  
Ý
Ý
.
3. In the formula, M Number of wait states (0 or 1) for ALE.  
2. Specifications for PSEN are identical to those for RD  
e
e
Ý
Ý
Ý
.
4. In the formula, N Number of wait states (0, 1, 2, or 3) for RD /PSEN /WR  
5. ‘‘Typical’’ specifications are untested and not guaranteed.  
17  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
e
Table 9. AC Characteristics (Capacitive Loading  
50 pF) (Continued)  
@
Max F  
(1)  
F
Variable  
OSC  
OSC  
Min  
Symbol  
Parameter  
Units  
Min  
Max  
Max  
Ý
Ý
Address Valid to RD /PSEN Low  
T
AVRL  
(2)  
ns  
(3)  
@
12 MHz  
16 MHz  
126.6  
85  
@
a
2(1 M)  
b
T
T
T
40  
OSC  
Ý
Address (P0) Valid to WR Low  
T
T
ns  
(3)  
AVWL1  
AVWL2  
@
12 MHz  
16 MHz  
126.6  
85  
@
a
2(1 M)  
b
40  
OSC  
Ý
Address (P2) Valid to WR Low  
ns  
(3)  
@
12 MHz  
16 MHz  
141.6  
100  
@
a
2(1 M)  
b
25  
OSC  
Ý
Data Hold after WR High  
T
T
ns  
WHQX  
@
12 MHz  
16 MHz  
58.3  
37.5  
@
b
T
T
25  
OSC  
Ý
Data Valid to WR High  
@
ns  
(4)  
QVWH  
12 MHz  
16 MHz  
146.6  
105  
@
a
2(1 N)  
b
20  
OSC  
Ý
WR High to Address Hold  
T
ns  
WHAX  
@
12 MHz  
16 MHz  
146.6  
105  
@
b
20  
2T  
OSC  
NOTES:  
1. 16 MHz.  
Ý
Ý
.
3. In the formula, M Number of wait states (0 or 1) for ALE.  
2. Specifications for PSEN are identical to those for RD  
e
e
Ý
Ý
Ý
.
4. In the formula, N Number of wait states (0, 1, 2, or 3) for RD /PSEN /WR  
5. ‘‘Typical’’ specifications are untested and not guaranteed.  
18  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
SYSTEM BUS TIMINGS  
272814–6  
²
The value of this parameter depends on wait states. See the table of AC characteristics.  
Figure 6. External Read Data Bus Cycle in Nonpage Mode  
19  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
272814–7  
²
The value of this parameter depends on wait states. See the table of AC characteristics.  
Figure 7. External Instruction Bus Cycle in Nonpage Mode  
20  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
272814–8  
²
The value of this parameter depends on wait states. See the table of AC characteristics.  
Figure 8. External Write Data Bus Cycle in Nonpage Mode  
21  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
272814–9  
²
The value of this parameter depends on wait states. See the table of AC characteristics.  
Figure 9. External Read Data Bus Cycle in Page Mode  
22  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
272814–10  
²
The value of this parameter depends on wait states. See the table of AC characteristics.  
Figure 10. External Write Data Bus Cycle in Page Mode  
23  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
272814–11  
²
²²  
The value of this parameter depends on wait states. See the table of AC characteristics.  
A page hit (i.e., a code fetch to the same 256-byte ‘‘page’’ as the previous code fetch) requires one state (2T  
);  
OSC  
a page miss requires two states (4T  
During a sequence of page hits, PSEN remains low until the end of the last page-hit cycle.  
).  
OSC  
Ý
²²²  
Figure 11. External Instruction Bus Cycle in Page Mode  
24  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
AC CharacteristicsÐSerial Port, Shift Register Mode  
Table 10. Serial Port Timing Shift Register Mode  
Symbol  
Parameter  
Min  
12T  
Max  
Units  
ns  
T
T
T
T
T
Serial Port Clock Cycle Time  
XLXL  
OSC  
b
Output Data Setup to Clock Rising Edge  
Output Data Hold after Clock Rising Edge  
Input Data Hold after Clock Rising Edge  
Clock Rising Edge to Input Data Valid  
10T  
133  
117  
ns  
QVSH  
XHQX  
XHDX  
XHDV  
OSC  
OSC  
b
2T  
ns  
0
ns  
b
10T  
133  
ns  
OSC  
272814–12  
²
TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit.  
Figure 12. Serial Port Waveform ÐShift Register Mode  
25  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
External Clock Drive  
Table 11. External Clock Drive  
Symbol  
1/T  
Parameter  
Oscillator Frequency (F  
High Time  
Min  
Max  
Units  
MHz  
ns  
)
OSC  
16  
CLCL  
T
T
T
T
20  
20  
CHCX  
Low Time  
ns  
CLCX  
CLCH  
CHCL  
Rise Time  
10  
10  
ns  
Fall Time  
ns  
272814–13  
Figure 13. External Clock Drive Waveforms  
272814–14  
0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made  
at a min of V for logic 1 and V for a logic 0.  
b
AC inputs during testing are driven at V  
CC  
IH OL  
Figure 14. AC Testing Input, Output Waveforms  
26  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
272814–15  
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float  
e
g
when a 100 mV change from the loading V /V level occurs with I /I  
OH OL  
20 mA.  
OL OH  
Figure 15. Float Waveforms  
272814–16  
Figure 16. Setup for Programming and Verifying Nonvolatile Memory  
27  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
Information in Figures 17 and 18 define the configu-  
PROGRAMMING AND VERIFYING  
NONVOLATILE MEMORY  
ration bits. Figure 19 shows the waveforms for the  
programming and verification cycles, and Table 12  
lists the timing specifications. The signature bytes of  
the 83C151SA/SB ROM versions and the  
87C151SA/SB OTPROM versions are factory pro-  
grammed. Table 13 lists the addresses and the con-  
tents of the signature bytes.  
The 87C151SA/SB has several areas of nonvolatile  
memory that can be programmed and/or verified:  
on-chip code memory (8/16 Kbytes), lock bits (3  
bits), encryption array (128 bytes), and signature  
bytes (3 bytes).  
Factory-programmed ROM and OTPROM versions  
of 8XC151SA/SB use configuration byte information  
Figure 16 shows the setup for programming and/or  
verifying the nonvolatile memory. Table 11 lists the  
programming and verification operations and indi-  
cates which operations apply to the different ver-  
sions of the 87C151SA/SB. It also specifies the sig-  
supplied in a  
8XC151SA/SB  
separate hexadecimal disk file.  
devices without internal  
ROM/OTPROM arrays fetch configuration byte in-  
formation from external application memory based  
on an internal address range of FFF9:8H.  
Ý
nals on the programming input (PROG ) and the  
ports. The ROM/OTPROM mode (port 0) specifies  
the operation (program or verify) and the base ad-  
dress of the memory area. The addresses (ports 1  
and 3) are relative to the base address. (On-chip  
memory for a 16-Kbyte ROM/OTPROM device is lo-  
cated at address range 0000H–3FFFH. The other  
areas of the ROM/OTPROM are outside the memo-  
ry address space and are accessible only during pro-  
gramming and verification.)  
NOTE:  
The V source in Figure 16 must be well regu-  
PP  
lated and free of glitches. The voltage on the V  
PP  
pin must not exceed the specified maximum,  
even under transient conditions.  
28  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
Table 12. Programming and Verification Modes Mode  
8XC151SA/SB  
Addresses  
Ý
Mode  
PROG  
P0  
P2  
Notes  
P1 (high), P3 (low)  
e
e
X
7
X
3
Program On-Chip Code  
Memory  
Y
5 Pulses  
High  
68H  
28H  
Data 0000H–3FFFH (16K)  
0000H–1FFFH (8K)  
1
Verify On-Chip Code  
Memory  
Y
Y
Data 0000H–3FFFH (16K)  
0000H–1FFFH (8K)  
Program Configuration  
Bytes  
2
2
Verify Configuration  
Bytes  
Program Lock Bits  
Verify Lock Bits  
Y
Y
Y
25 Pulses 6BH  
High 2BH Data 0000H  
25 Pulses 6CH Data 0000H–007FH  
XX  
0001H–0003H  
1, 3  
4
Y
Y
Program Encryption  
Array  
1
Verify Signature Bytes  
Y
High  
29H  
Data 0030H, 0031H, 0060H  
NOTES:  
1. The PROG pulse waveform is shown in Figure 19.  
Ý
2. Factory-programmed ROM and OTPROM versions of 8XC151SA/SB use configuration byte information supplied in a  
separate hexadecimal disk file. 8XC151SA/SB devices without internal ROM/OTPROM arrays fetch configuration byte  
information from external application memory based on an internal address range of FFF9:8H.  
3. When programming the lock bits, the data bits on port 2 are don’t care. Identify the lock bits with the address as follows:  
LB3 - 0003H, LB2 - 0002H, LB1 - 0001H.  
4. The three lock bits are verified in a single operation. The states of the lock bits appear simultaneously at port 2 as  
e
follows: LB3 - P2.3, LB2 - P2.2. LB1 - P2.1. High  
programmed.  
29  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
Address FFF8H  
UCONFIG0  
7
0
Ý
Ý
Ý
Ý
PAGE  
Ð
WSA1  
WSA0  
XALE  
Ð
Ð
Ð
Bit  
Bit  
Function  
Number  
Mnemonic  
7
Ð
Reserved  
Wait State Select for external code  
Ý
Ý
6:5  
WSA1  
WSA0  
Ý
Ý
WSA1  
WSA0  
Description  
No wait states  
Insert 1 wait state  
(see Note)  
1
1
0
0
1
0
1
0
Insert 2 wait states  
Insert 3 wait states  
Ý
4
1
XALE  
Extend Ale:  
If this bit is set, the time of the ALE pulse is T  
. Clearing this bit  
, which adds  
OSC  
to 3T  
extends the time of the ALE pulse from T  
one external wait state.  
OSC  
OSC  
Ý
PAGE  
Page Mode Select:  
Clear this bit for page-mode (A15:8/D7:0 on P2, and A7:0 on P0). Set  
this bit for nonpage-mode (A15:8 on P2, and A7:0/D7:0 on P0  
(compatible with MCS 51 microcontrollers)).  
NOTE:  
Factory-programmed ROM and OTPROM versions of 8XC151SA/SB use configuration byte information supplied in a  
separate hexadecimal disk file. 8XC151SA/SB devices without internal ROM/OTPROM arrays fetch configuration byte  
information from external application memory based on an internal address range of FFF9:8H.  
Figure 17. Configuration Byte 0  
30  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
Address FFF9H  
0
UCONFIG1  
7
Ý
Ý
Ð
Ð
Ð
Ð
Ð
WSB1  
WSB0  
Ð
Bit  
Bit  
Function  
Number  
Mnemonic  
7:5  
2:1  
Ð
Reserved; set these bits when writing to UCONFIG1.  
Wait States for external data  
Ý
Ý
WSB1  
WSB0  
,
Ý
Ý
WSB0  
WSB1  
Description  
1
1
0
0
1
0
1
0
No wait states  
Insert 1 wait state  
Insert 2 wait states  
Insert 3 wait states  
NOTE:  
Factory-programmed ROM and OTPROM versions of 8XC151SA/SB use configuration byte information supplied in a  
separate hexadecimal disk file. 8XC151SA/SB devices without internal ROM/OTPROM arrays fetch configuration byte  
information from external application memory based on an internal address range of FFF9:8H.  
Figure 18. Configuration Byte 1  
31  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
272814–17  
Figure 19. Timing for Programming and Verification of Nonvolatile Memory  
32  
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
Table 13. Nonvolatile Memory Programming and Verification Characteristics at  
e
b
21 27 C, V  
e
e
0V  
SS  
T
A
5V, and V  
§
CC  
Symbol  
Definition  
Min  
Max  
13.5  
75  
Units  
D.C. Volts  
mA  
V
PP  
Programming Supply Voltage  
Programming Supply Current  
Oscillator Frequency  
12.5  
I
PP  
F
T
T
T
T
T
T
T
T
T
T
T
T
4.0  
6.0  
MHz  
OSC  
Ý
Address Setup to PROG Low  
48T  
48T  
48T  
48T  
48T  
AVGL  
GHAX  
DVGL  
GHDX  
EHSH  
SHGL  
GHSL  
GLGH  
AVQV  
ELQV  
EHQZ  
GHGL  
OSC  
Ý
Address Hold after PROG  
OSC  
OSC  
OSC  
OSC  
Ý
Data Setup to PROG Low  
Ý
Data Hold after PROG  
ENABLE High to V  
PP  
Ý
Setup to PROG Low  
V
V
10  
ms  
ms  
ms  
PP  
PP  
Ý
Hold after PROG  
10  
90  
Ý
PROG Width  
110  
Address to Data Valid  
48T  
OSC  
ENABLE Low to Data Valid  
Data Float after ENABLE  
48To  
SC  
0
48T  
OSC  
Ý
Ý
PROG High to PROG Low  
10  
ms  
NOTE:  
Notation for timing parameters:  
e
e
e
e
e
e
e
e
e
e
Ý
A
Address  
Data out  
D
S
Data  
E
V
Enable  
Valid  
G
PROG  
H
Z
High  
L
Low  
e
Floating  
Q
Supply (V  
)
PP  
X
No Longer Valid  
Table 14. Contents of the Signature Bytes  
ADDRESS  
30H  
CONTENTS  
89H  
DEVICE TYPE  
Indicates Intel Devices  
31H  
48H  
Indicates MCS 151 core product  
Indicates 83C151SB device  
Indicates 87C151SB device  
Indicates 83C151SA device  
Indicates 87C151SA device  
60H  
7BH  
60H  
FBH  
60H  
7AH  
60H  
FAH  
33  
厂商 型号 描述 页数 下载

INTEL

 		8XC151SA 高性能CHMOS微控制器[ HIGH-PERFORMANCE CHMOS MICROCONTROLLER ] 33 页

INTEL

 		8XC152JA 通用通信控制器8位微控制器[ UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER ] 17 页

INTEL

 		8XC152JB 通用通信控制器8位微控制器[ UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER ] 17 页

INTEL

 		8XC152JC 通用通信控制器8位微控制器[ UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER ] 17 页

INTEL

 		8XC152JD 通用通信控制器8位微控制器[ UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER ] 17 页

INTEL

 		8XC196JQ 商业/ EXPRESS CHMOS单片机[ COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER ] 25 页

INTEL

 		8XC196JR 商业/ EXPRESS CHMOS单片机[ COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER ] 25 页

INTEL

 		8XC196KB 先进的16位微控制器CHMOS无ROM或ROM[ ADVANCED 16-BIT CHMOS MICROCONTROLLER ROMless OR ROM ] 17 页

INTEL

 		8XC196KB16 商业/ EXPRESS CHMOS单片机[ COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER ] 22 页

INTEL

 		8XC196KC 商业/ EXPRESS CHMOS单片机[ COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER ] 25 页

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