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8XC196NT

型号:

8XC196NT

描述:

1兆字节的线性地址空间CHMOS单片机[ CHMOS MICROCONTROLLER WITH 1 MBYTE LINEAR ADDRESS SPACE ]

品牌:

INTEL[ INTEL ]

页数:

31 页

PDF大小:

485 K

8XC196NT  
CHMOS MICROCONTROLLER WITH  
1 MBYTE LINEAR ADDRESS SPACE  
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
20 MHz Operation  
Oscillator Fail Detection Circuitry  
Y
Y
High Performance CHMOS 16-Bit CPU  
Up to 32 Kbytes of On-Chip OTPROM  
Up to 1 Kbyte of On-Chip Register RAM  
Up to 512 Bytes of Internal RAM  
Register-Register Architecture  
High Speed Peripheral Transaction  
Server (PTS)  
Two Dedicated 16-Bit High-Speed  
Compare Registers  
Y
Y
10 High Speed Capture/Compare (EPA)  
Full Duplex Synchronous Serial I/O  
Port (SSIO)  
4 Channel/10-Bit A/D with Sample/Hold  
37 Prioritized Interrupt Sources  
Up to Seven 8-Bit (56) I/O Ports  
Full Duplex Serial I/O Port  
Y
Y
Y
Two Flexible 16-Bit Timer/Counters  
Quadrature Counting Inputs  
Flexible 8-/16-Bit External Bus  
(Programmable)  
Dedicated Baud Rate Generator  
Y
Y
Y
Y
Programmable Bus (HOLD/HLDA)  
1.4 ms 16 x 16 Multiply  
2.4 ms 32/16 Divide  
Interprocessor Communication Slave  
Port  
Y
Selectable Bus Timing Modes for  
Flexible External Memory Interfacing  
68-Pin Package  
Reg  
Code  
RAM  
Address  
Space  
Device  
Pins/Package  
OTPROM  
I/O  
EPA  
A/D  
RAM  
8XC196NT  
68P PLCC  
32K  
1K  
512  
1 Mbyte  
56  
10  
4
e
e
X
X
7 OTPROM Device  
0 ROMLESS  
The 8XC196NT 16-bit microcontroller is a high performance member of the MCS 96 microcontroller family.  
É
The 8XC196NT is an enhanced 8XC196KR device with 1 Mbyte of linear address space, 1000 bytes of  
register RAM, 512 bytes of internal RAM, 20 MHz operation and an optional 32 Kbytes of OTPROM. Intel’s  
CHMOS III-E process provides a high performance processor along with low power consumption.  
Ten high-speed capture/compare modules are provided. As capture modules event times with 200 ns resolu-  
tion can be recorded and generate interrupts. As compare modules events such as toggling of a port pin,  
starting an A/D conversion, pulse width modulation, and software timers can be generated. Events can be  
based on the timer or up/down counter.  
*Other brands and names are the property of their respective owners.  
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or  
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make  
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.  
©
COPYRIGHT INTEL CORPORATION, 1995  
September 1994  
Order Number: 272267-004  
8XC196NT  
272267–1  
Figure 1. 8XC196NT Block Diagram  
All thermal impedance data is approximate for static  
air conditions at 1W of power dissipation. Values will  
change depending on operation conditions and ap-  
plication. See the Intel Packaging Handbook (order  
number 240800) for a description of Intel’s thermal  
impedance test methodology.  
PROCESS INFORMATION  
This device is manufactured on P629.5, a CHMOS  
III-E process. Additional process and reliability infor-  
mation is available in Intel’s Components Quality  
and Reliability Handbook, Order Number 210997.  
Table 1. Thermal Characteristics  
Package  
Type  
i
JC  
i
JA  
PLCC  
36.5 C/W  
§
13 C/W  
§
272267–2  
EXAMPLE: N87C196NT is 68-Lead PLCC OTPROM.  
For complete package dimensional data, refer to the Intel Packaging Handbook (Order Number 240800).  
Figure 2. The 8XC186NT Familiy Nomenclature  
2
8XC196NT  
8XC196NT Memory Map  
Description  
Address  
(Note 7)  
FFFFFFH  
FFA000H  
External Memory  
FF9FFFH  
FF2080H  
Internal OTPROM or External Memory (Determined by EA Pin)  
RESET at FF2080H  
FF207FH  
FF2000H  
Reserved Memory (Internal OTPROM or External Memory)  
(Determined by EA Pin)  
FF1FFFH  
FF0600H  
External Memory  
FF05FFH  
FF0400H  
Internal RAM (Identically Mapped into 00400H005FFH)  
External Memory  
FF03FFH  
FF0100H  
FF00FFH  
FF0000H  
Reserved for ICE  
FEFFFFH  
100000H  
External Memory for future devices  
984 Kbytes External Memory  
Internal OTPROM or External Memory (Note 1)  
FFFFFH  
00A000H  
009FFFH  
002080H  
00207FH  
002000H  
Reserved Memory (Internal OTPROM or External Memory)  
(Notes 1, 3, and 6)  
001FFFH  
001FE0H  
Memory Mapped Special Function Registers (SFR’s)  
Internal Special Function Registers (SFR’s) (Note 5)  
External Memory  
001FDFH  
001F00H  
001EFFH  
000600H  
0005FFH  
000400H  
Internal RAM  
(Address with Indirect or Indexed Modes)  
0003FFH  
Upper Register File (Address with Indirect or  
Indexed Modes or through Windows.) (Note 2)  
Register RAM  
000100H  
*
*
0000FFH  
000018H  
Lower Register File  
(Address with Direct,  
Indirect, or Indexed  
Modes.) (Notes 2, 4)  
Register RAM  
CPU SFR’s  
000017H  
000000H  
NOTES:  
e
1. These areas are mapped internal OTPROM if the REMAP bit (CCB2.2) is set and EA  
memory.  
2. Code executed in locations 00000H to 003FFH will be forced external.  
3. Reserved memory locations must contain 0FFH unless noted.  
4. Reserved SFR bit locations must be written with 0.  
5V. Otherwise they are external  
5. Refer to 8XC196NT User’s Guide and Quick Reference for SFR descriptions.  
6. WARNING: The contents or functions of reserved memory locations may change with future revisions of the device.  
Therefore, a program that relies on one or more of these locations may not function properly.  
7. The 8XC196NT internally uses 24 bit address, but only 20 address lines are bonded out allowing 1 Mbyte external  
address space.  
3
8XC196NT  
272267–3  
Figure 3. 68-Pin PLCC Package Diagram  
4
8XC196NT  
PIN DESCRIPTIONS  
Symbol  
Name and Function  
a
Main supply voltage ( 5V).  
V
V
CC  
, V , V  
SS SS1 SS1  
Digital circuit ground (0V). There are multiple V pins, all of which MUST be  
SS  
connected.  
a
V
V
Reference for the A/D converter ( 5V). V  
is also the supply voltage to the  
REF  
REF  
analog portion of the A/D converter and the logic used to read Port 0. Must be  
connected for A/D and Port 0 to function.  
a
Programming voltage for the OTPROM parts. It should be 12.5V for programming.  
It is also the timing pin for the return from powerdown circuit. Connect to V if  
PP  
CC  
powerdown not being used.  
ANGND  
Reference ground for the A/D converter. Must be held at nominally the same  
.
potential as V  
SS  
XTAL1  
Input of the oscillator inverter and the internal clock generator.  
Output of the oscillator inverter.  
XTAL2  
P2.7/CLKOUT  
Output of the internal clock generator. The frequency is (/2 the oscillator frequency.  
It has a 50% duty cycle. Also LSIO pin.  
RESET  
Reset input to and open-drain output from the chip. RESET has an internal pullup.  
P5.7/BUSWIDTH  
Input for bus width selection. If CCR bit 1 is a one and CCR1 bit 2 is a one, this pin  
dyamically controls the Buswidth of the bus cycle in progress. If BUSWIDTH is low,  
an 8-bit cycle occurs, if BUSWIDTH is high, a 16-bit cycle occurs. If CCR bit 1 is ‘‘0’’  
and CCR1 bit 2 is ‘‘1’’, all bus cycles are 8-bit, if CCR bit 1 is ‘‘1’’ and CCR1 bit 2 is  
e
an LSIO pin when not used as BUSWIDTH.  
e
‘‘0’’, all bus cycles are 16-bit. CCR bit 1  
‘‘0’’ and CCR1 bit 2  
‘‘0’’ is illegal. Also  
NMI  
A positive transition causes a non maskable interrupt vector through memory  
location 203EH.  
P5.1/INST/SLPCS  
Output high during an external memory read indicates the read is an instruction  
fetch. INST is valid throughout the bus cycle. INST is active only during external  
memory fetches, during internal OTPROM fetches INST is held low. Also LSIO when  
not INST. SLPCS is the Slave Port Chip Select.  
EA  
Input for memory select (External Access). EA equal to a high causes memory  
accesses to locations 0FF2000H through 0FF9FFFH to be directed to on-chip  
OTPROM. EA equal to a low causes accesses to these locations to be directed to  
e a  
Mode. EA is latched at reset.  
off-chip memory. EA  
12.5V causes execution to begin in the Programming  
HOLD  
HLDA  
BREQ  
Bus Hold Input requesting control of the bus.  
Bus Hold acknowledge output indicating release of the bus.  
Bus Request output activated when the bus controller has a pending external  
memory cycle.  
P5.0/ALE/ADV/  
SLPADDR/  
SLPALE  
Address Latch Enable or Address Valid output, as selected by CCR. Both pin  
options provide a latch to demultiplex the address from the address/data bus. When  
the pin is ADV, it goes inactive (high) at the end of the bus cycle. ADV can be used  
as a chip select for external memory. ALE/ADV is active only during external  
memory accesses. Also LSIO when not used as ALE. SLPADDR is the Slave Port  
Address Control Input and SLPALE is the Slave Port Address Latch Enable Input.  
P5.3/RD/SLPRD  
Read signal output to external memory. RD is active only during external memory  
reads or LSIO when not used as RD. SLPRD is the Slave Port Read Control Input.  
5
8XC196NT  
PIN DESCRIPTIONS (Continued)  
Symbol  
Name and Function  
P5.2/WR/WRL/SLPWR  
Write and Write Low output to external memory, as selected by the CCR, WR  
will go low for every external write, while WRL will go low only for external  
writes where an even byte is being written. WR/WRL is active during external  
memory writes. Also an LSIO pin when not used as WR/WRL. SLPWR is the  
Slave Port Write Control Input  
e
selects the bank of memory that is connected to the high byte of the data bus.  
P5.5/BHE/WRH  
Byte High Enable or Write High output, as selected by the CCR. BHE  
0
e
A0 0 selects that bank of memory that is connected to the low byte. Thus  
accesses to a 16-bit wide memory can be to the low byte only (A0 0,  
e
e
e
e
e
BHE 1), to the high byte only (A0 1, BHE 0) or both bytes (A0 0,  
BHE 0). If the WRH function is selected, the pin will go low if the bus cycle is  
e
writing to an odd memory location. BHE/WRH is only valid during 16-bit  
external memory read/write cycles. Also an LSIO pin when not BHE/WRH.  
P5.6/READY  
Ready input to lengthen external memory cycles, for interfacing with slow or  
dynamic memory, or for bus sharing. If the pin is high, CPU operation continues  
in a normal manner. If the pin is low prior to the falling edge of CLKOUT, the  
memory controller goes into a wait state mode until the next positive transition  
in CLKOUT occurs with READY high. When external memory is not used,  
READY has no effect. The max number of wait states inserted into the bus  
cycle is controlled by the CCR/CCR1. Also an LSIO pin when READY is not  
selected.  
P5.4/SLPINT  
P6.2/T1CLK  
Dual function I/O pin. As a bidirectional port pin or as a system function. The  
system function is a Slave Port Interrupt Output Pin.  
Dual function I/O pin. Primary function is that of a bidirectional I/O pin,  
however, it may also be used as a TIMER1 Clock input. The TIMER1 will  
increment or decrement on both positive and negative edges of this pin.  
P6.3/T1DIR  
Dual function I/O pin. Primary function is that of a bidirectional I/O pin,  
however, it may also be used as a TIMER1 Direction input. The TIMER1 will  
increment when this pin is high and decrements when this pin is low.  
PORT1/EPA0–7  
P6.06.1/EPA8–9  
Dual function I/O port pins. Primary function is that of bidirectional I/O. System  
function is that of High Speed capture and compare. EPA0 and EPA2 have yet  
another function of T2CLK and T2DIR of the TIMER2 timer/counter.  
PORT 0/ACH4–7  
P6.36.7/SSIO  
4-bit high impedance input-only port. These pins can be used as digital inputs  
and/or as analog inputs to the on-chip A/D converter. These pins are also  
used as inputs to OTPROM parts to select the Programming Mode.  
Dual function I/O ports that have a system function as Synchronous Serial I/O.  
Two pins are clocks and two pins are data, providing full duplex capability.  
PORT 2  
8-bit multi-functional port. All of its pins are shared with other functions.  
PORT 3 and 4  
8-bit bidirectional I/O ports with open drain outputs. These pins are shared  
with the multiplexed address/data bus which has strong internal pullups.  
EPORT  
8-bit bidirectional standard and I/O port. These bits are shared with the  
extended address bus, A16A19. Pin function is selected on a per pin basis.  
INTOUT  
Interrupt Output. This active-low output indicates that a pending interrupt  
requires use of the external bus.  
SLP0SLP7  
Slave Port Address/Data Bus  
6
8XC196NT  
ABSOLUTE MAXIMUM RATINGS*  
NOTICE: This data sheet contains information on  
products in the sampling and initial production phases  
of development. The specifications are subject to  
change without notice. Verify with your local Intel  
Sales office that you have the latest data sheet be-  
fore finalizing a design.  
b
a
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 60 C to 150 C  
§
§
Voltage from V or EA to  
V
PP  
or ANGND ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 0.5V to 13.0V  
b a  
SS  
Voltage from Any Other Pin  
to V or ANGND ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 0.5 to 7.0V  
This includes V on ROM and CPU devices.  
*WARNING: Stressing the device beyond the ‘‘Absolute  
Maximum Ratings’’ may cause permanent damage.  
These are stress ratings only. Operation beyond the  
‘‘Operating Conditions’’ is not recommended and ex-  
tended exposure beyond the ‘‘Operating Conditions’’  
may affect device reliability.  
b
a
SS  
PP  
Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0.5W  
OPERATING CONDITIONS  
Symbol  
Parameter  
Ambient Temperature Under Bias  
Digital Supply Voltage  
Min  
0
Max  
Units  
a
T
A
70  
C
§
V
V
4.50  
4.50  
4
5.50  
5.50  
20  
V
CC  
Analog Supply Voltage  
Oscillator Frequency  
V
REF  
OSC  
F
MHz (Note 4)  
NOTE:  
ANGND and V should be nominally at the same potential.  
SS  
DC CHARACTERISTICS (Under Listed Operating Conditions)  
Symbol  
Parameter  
Supply Current  
CC  
Min  
Typ  
Max  
Units  
mA XTAL1  
Test Conditions  
e
20 MHz,  
I
V
90  
CC  
e
e
e
5.5V  
REF  
V
CC  
V
V
PP  
(While device in Reset)  
I
I
A/D Reference Supply Current  
Idle Mode Current  
5
mA  
REF  
e
20 MHz,  
40  
mA XTAL1  
IDLE  
e
e
e
e
V
V
V
5.5V  
5.5V  
CC  
CC  
PP  
REF  
(6)  
(11)  
e
e
I
Powerdown Mode Current  
50  
75  
mA  
V
V
V
V
PD  
PP  
REF  
(10)  
(10)  
b
V
V
V
V
V
Input Low Voltage (all pins)  
Input High Voltage  
0.5V  
0.3 V  
For PORT0  
For PORT0  
IL  
CC  
a
a
a
0.7 V  
V
V
V
0.5  
0.5  
0.5  
V
IH  
CC  
CC  
CC  
CC  
CC  
CC  
(1)  
Input High Voltage XTAL1  
Input High Voltage on RESET  
0.7 V  
0.7 V  
V
XTAL1 Input Pin Only  
IH1  
IH2  
OL  
V
RESET input pin only  
(3,5)  
e
e
e
Output Low Voltage  
(Outputs Configured as  
Complementary)  
0.3  
0.45  
1.5  
V
V
V
I
I
I
200 mA  
3.2 mA  
7.0 mA  
OL  
OL  
OL  
(3,5)  
200mA  
b
b
b
e b  
e b  
e b  
V
Output High Voltage  
(Outputs Configured as  
Complementary)  
V
CC  
V
CC  
V
CC  
0.3  
0.7  
1.5  
V
V
V
I
I
I
OH  
OH  
OH  
OH  
3.2 mA  
7.0 mA  
k
k
g
b
I
I
I
Input Leakage Current (Std. Inputs)  
Input Leakage Current (Port 0)  
Logical 0 Input Current  
10  
mA  
mA  
mA  
V
V
V
V
V
CC  
LI  
SS  
CC  
IN  
IN  
k
k
V
g
3
V
LI1  
IL  
IN  
REF  
(1)  
0.45V  
e
70  
7
8XC196NT  
DC CHARACTERISTICS (Under Listed Operating Conditions) (Continued)  
Symbol  
Parameter  
Min  
Typ  
Max  
Units  
Test Conditions  
V
V
Output Low Voltage in RESET  
0.8  
V
V
(Note 7)  
(7)  
OL1  
OH1  
e
0.8 mA  
SLPINT (P5.4) and HLDA (P2.6)  
Output High Voltage in RESET  
2.0  
I
OH  
(1)  
b
e b  
V
Output High Voltage in RESET  
V
1V  
V
pF  
X
I
6 mA  
1.0 MHz  
(Note 6)  
OH2  
CC  
OH  
e
C
Pin Capacitance (Any pin to V  
Weak Pullup Resistance  
Reset Pullup  
)
10  
f
test  
S
SS  
R
R
150K  
WPU  
RST  
65K  
180K  
X
NOTES:  
1. All BD (bidirectional) pins except INST and CLKOUT. INST and CLKOUT are excluded due to their not being weakly  
pulled high in reset. BD pins include Port1, Port2, Port3, Port4, Port5, Port6 and EPORT except SPLINT (P5.4) and HLDA  
(P2.6).  
2. Standard input pins include XTAL1, EA, RESET, and Port 1/2/5/6 and EPORT when setup as inputs.  
3. All bidirectional I/O pins when configured as Outputs (Push/Pull).  
4. Device is static and should operate below 1 Hz, but only tested down to 4 MHz.  
5. Maximum I /I  
currents per pin will be characterized and published at a later date.  
6. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and  
OL OH  
e
7. Violating these specifications in reset may cause the device to enter test modes (P5.4 and P2.6).  
e
V
CC  
V
REF  
5.5V.  
e
9. Pullup present during return from powerdown condition.  
8. TBD  
To Be Determined.  
10. When P0 is used as analog inputs, refer to A/D specifications.  
k
11. For temperatures 100 C typical is 10 mA.  
§
8
8XC196NT  
8XC196NT ADDITIONAL BUS TIMING MODES  
The 8XC196NT device has 3 additional bus timing  
modes for external memory interfacing.  
MODE 1:  
Mode 1 is the long R/W mode. This mode advances  
RD and WR signals by 1 T  
RD/WR low time. ALE is also advanced by 0.5 T  
creating a 2 T  
OSC  
OSC  
OSC  
MODE 3:  
but ALE high time remains 1 T  
.
OSC  
Mode 3 is the standard timing mode. Use this mode  
for systems that emulate the 8XC196KR bus tim-  
ings.  
MODE 2:  
Mode 2 is the long R/W mode with Early Address.  
Mode 2 is similar to Mode 1 with respect to RD, WR,  
and ALE signals. Additionally, the address is output  
MODE 0:  
Mode 0 is the standard timing mode, but 1 (mini-  
mum) wait state is always inserted in external bus  
cycles.  
on the bus 0.5 T  
earlier in the bus cycle.  
OSC  
272267–4  
Figure 4. Detailed MODE 1, 2, 3, Comparison  
9
8XC196NT  
Conditions:  
HÐHigh  
LÐLow  
Signals:  
EXPLANATION OF AC SYMBOLS  
AÐAddress  
BÐBHE  
BRÐBREQ  
HAÐHLDA  
LÐALE/ADV  
QÐData Out  
Each symbol is two pairs of letters prefixed by ‘‘T’’  
for time. The characters in a pair indicate a signal  
and its condition, respectively. Symbols represent  
the time between the two signal/condition points.  
VÐValid  
XÐNo Longer CÐCLKOUT RDÐRD  
Valid  
ZÐFloating  
DÐDATA  
GÐBuswidth XÐXTAL1  
HÐHOLD YÐREADY  
WÐWR/WRH/WRI  
BUS MODE 0 and 3ÐAC CHARACTERISTICS (Over Specified Operating Conditions)  
e
e
Test Conditions: Capacitance Load on All Pins  
100 pF, Rise and Fall Times  
10 ns.  
The system must meet these specifications to work with the 8XC196NT.  
Symbol  
Parameter  
Min  
0
Max  
Units  
(3)  
ns  
b
T
T
T
T
T
T
T
T
T
T
T
Address Valid to Ready Setup  
Non READY Time  
2 T  
75  
75  
55  
AVYV  
YLYH  
CLYX  
AVGV  
LLGV  
CLGX  
AVDV  
RLDV  
CLDV  
RHDZ  
RHDX  
OSC  
No Upper Limit  
ns  
(1)  
ns  
b
READY Hold after CLKOUT Low  
Address Valid to BUSWIDTH Setup  
ALE Low to BUSWIDTH Setup  
BUSWIDTH Hold after CLKOUT Low  
Address Valid to Input Data Valid  
RD active to input Data Valid  
CLKOUT Low to Input Data Valid  
End of RD to Input Data Float  
Data Hold after RD High  
T
30  
OSC  
(2, 3)  
ns  
b
2 T  
OSC  
(2, 3)  
ns  
b
T
60  
OSC  
0
ns  
(2)  
ns  
b
3 T  
OSC  
(2)  
ns  
b
T
T
30  
OSC  
OSC  
b
60  
ns  
ns  
ns  
T
OSC  
0
NOTES:  
1. If Max is exceeded, additional wait states will occur.  
c
e
2. If wait states are used, add 2 T  
n, where n  
number of wait states.  
OSC  
3. If mode 0 is selected, one wait state minimum is always added. If additional wait states are required, add 2 T  
specification.  
to the  
OSC  
10  
8XC196NT  
BUS MODE 0 and 3ÐAC CHARACTERISTICS (Over Specified Operating Conditions)  
e
e
Test Conditions: Capacitance Load on All Pins  
100 pF, Rise and Fall Times  
10 ns.  
The 8XC196NT will meet these specifications  
Symbol  
Parameter  
Min  
4.0  
50  
Max  
20  
Units  
(1)  
MHz  
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Frequency on XTAL1  
XTAL  
OSC  
XTAL1 Period (1/F  
)
250  
110  
40  
ns  
ns  
ms  
ns  
ns  
ns  
ns  
XTAL  
a
XTAL1 High to CLKOUT High or Low  
20  
XHCH  
OFD  
(6)  
Clock Failure to Reset Pulled Low  
4
CLKOUT Period  
2 T  
OSC  
CLCL  
CHCL  
CLLH  
LLCH  
LHLH  
LHLL  
b
10  
25  
a
CLKOUT High Period  
T
10  
T
30  
10  
OSC  
OSC  
b
a
a
CLKOUT Low to ALE/ADV High  
ALE/ADV Low to CLKOUT High  
ALE/ADV Cycle Time  
15  
15  
b
(5)  
ns  
4 T  
OSC  
b
b
b
b
a
ALE/ADV High Time  
T
T
T
T
10  
15  
40  
40  
T
ns  
ns  
ns  
ns  
ns  
OSC  
OSC  
OSC  
OSC  
OSC  
Address Valid to ALE Low  
Address Hold After ALE/ADV Low  
ALE/ADV Low to RD Low  
RD Low to CLKOUT Low  
RD Low Period  
AVLL  
LLAX  
LLRL  
b
a
5
35  
RLCL  
RLRH  
RHLH  
RLAZ  
LLWL  
CLWL  
QVWH  
CHWH  
WLWH  
WHQX  
WHLH  
WHBX  
WHAX  
RHBX  
RHAX  
(5)  
ns  
b
T
5
OSC  
(3)  
ns  
a
RD High to ALE/ADV High  
RD Low to Address Float  
ALE/ADV Low to WR Low  
CLKOUT Low to WR Low  
Data Valid before WR High  
CLKOUT High to WR High  
WR Low Period  
T
OSC  
T
25  
OSC  
a
5
ns  
ns  
ns  
ns  
ns  
b
T
T
10  
23  
OSC  
b
a
a
10  
25  
15  
b
OSC  
b
10  
b
b
b
b
b
b
b
(5)  
ns  
T
T
T
T
T
T
T
30  
35  
10  
10  
30  
10  
30  
OSC  
OSC  
OSC  
OSC  
OSC  
OSC  
OSC  
Data Hold after WR High  
WR High to ALE/ADV High  
BHE, INST Hold after WR High  
AD815 Hold after WR High  
BHE, INST Hold after RD High  
AD815 Hold after RD High  
ns  
(3)  
ns  
a
T
15  
OSC  
ns  
(4)  
ns  
ns  
(4)  
ns  
NOTES:  
1. Testing performed at 8.0 MHz, however, the device is static by design and will typically operate below 1 Hz.  
2. Typical specifications, not guaranteed.  
3. Assuming back-to-back bus cycles.  
4. 8-bit bus only.  
c
e
number of wait states. If mode 0 (1 automatic wait state added)  
5. If wait states are used, add 2 T  
operation is selected, add 2 T  
6. T  
n, where n  
to specification.  
OSC  
OSC  
is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. The OFD circuitry is enabled by  
OFD  
programming the UPROM location 0778H with the value 0004H. NT/NQ customer QROM codes need to equate location  
2016H to the value 0CDEH if the oscillator fail detect (OFD) function is desired. Intel manufacturing uses location 2016H  
as a flag to determine whether or not to program the Clock Detect Enable (CDE) bit. Programming the CDE bit  
enables oscillator fail detection.  
11  
8XC196NT  
BUS MODE 0 and 3Ð8XC196NT SYSTEM BUS TIMING  
272267–5  
*If mode 0 operation is selected, add 2 T  
to this time.  
OSC  
12  
8XC196NT  
8XC196NT MODE 0 and 3ÐREADY TIMINGS (ONE WAIT STATE)  
272267–6  
*If mode 0 selected, one wait state is always added. If additional wait states are required, add 2 T  
to these specifica-  
OSC  
tions.  
MODE 0 and 3Ð8XC196NT BUSWIDTH TIMINGS  
272267–7  
*If mode 0 selected, add 2 T  
to these specifications.  
OSC  
13  
8XC196NT  
BUS MODE 1ÐAC CHARACTERISTICS (Over Specified Operating Conditions)  
e
e
Test Conditions: Capacitance Load on All Pins  
100 pF, Rise and Fall Times  
10 ns.  
The system must meet these specifications to work with the 8XC196NT.  
Symbol  
Parameter  
Min  
0
Max  
Units  
ns  
b
75  
T
T
T
T
T
T
T
T
T
T
T
Address Valid to Ready Setup  
Non READY Time  
2 T  
AVYV  
YLYH  
CLYX  
AVGV  
LLGV  
CLGX  
AVDV  
RLDV  
CLDV  
RHDZ  
RHDX  
OSC  
No Upper Limit  
ns  
(1)  
ns  
b
30  
READY Hold after CLKOUT Low  
Address Valid to BUSWIDTH Setup  
ALE Low to BUSWIDTH Setup  
BUSWIDTH Hold after CLKOUT Low  
Address Valid to Input Data Valid  
RD active to input Data Valid  
CLKOUT Low to Input Data Valid  
End of RD to Input Data Float  
Data Hold after RD High  
T
OSC  
b
2 T  
75  
ns  
ns  
ns  
OSC  
b
1.5 T  
60  
OSC  
0
(2)  
ns  
b
b
3 T  
2 T  
60  
44  
OSC  
OSC  
(2)  
ns  
b
T
60  
ns  
ns  
ns  
OSC  
T
OSC  
0
NOTES:  
1. If Max is exceeded, additional wait states will occur.  
c
e
2. If wait states are used, add 2 T  
n, where n  
number of wait states.  
OSC  
14  
8XC196NT  
BUS MODE 1ÐAC CHARACTERISTICS (Over Specified Operating Conditions)  
e
e
Test Conditions: Capacitance Load on All Pins  
100 pF, Rise and Fall Times  
10 ns.  
The 8XC196NT will meet these specifications  
Symbol  
Parameter  
Min  
8.0  
50  
Max  
20  
Units  
(1)  
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Frequency on XTAL1  
MHz  
XTAL  
XTAL1 Period (1/F  
)
125  
110  
ns  
ns  
ns  
ns  
ns  
ns  
OSC  
XTAL  
a
XTAL1 High to CLKOUT High or Low  
CLKOUT Period  
20  
XHCH  
CLCL  
CHCL  
CHLH  
CLLL  
2 T  
OSC  
b
a
CLKOUT High Period  
T
10  
T
27  
OSC  
OSC  
b
a
CLKOUT HIGH to ALE/ADV High  
CLKOUT LOW to ALE/ADV Low  
ALE/ADV Cycle Time  
0.5 T  
0.5 T  
15  
0.5 T  
15  
15  
OSC  
OSC  
OSC  
OSC  
b
a
25  
4 T  
0.5 T  
(5)  
ns  
LHLH  
LHLL  
OSC  
b
a
10  
ALE/ADV High Time  
T
20  
T
T
ns  
ns  
ns  
ns  
ns  
OSC  
OSC  
b
b
b
Address Valid to ALE Low  
Address Hold After ALE/ADV Low  
ALE/ADV Low to RD Low  
RD Low to CLKOUT Low  
RD Low Period  
0.5 T  
0.5 T  
0.5 T  
20  
25  
15  
AVLL  
LLAX  
LLRL  
OSC  
OSC  
OSC  
b
OSC  
a
30  
T
10  
RLCL  
RLRH  
RHLH  
RLAZ  
LLWL  
CLWL  
QVWH  
CHWH  
WLWH  
WHQX  
WHLH  
WHBX  
WHIX  
WHAX  
RHBX  
RHIX  
OSC  
(5)  
ns  
b
2 T  
20  
OSC  
(3)  
ns  
a
25  
RD High to ALE/ADV High  
RD Low to Address Float  
ALE/ADV Low to WR Low  
CLKOUT Low to WR Low  
Data Valid before WR High  
CLKOUT High to WR High  
WR Low Period  
0.5 T  
0.5 T  
OSC  
OSC  
a
5
ns  
ns  
ns  
ns  
ns  
b
0.5 T  
10  
OSC  
b
a
T
15  
T
25  
OSC  
OSC  
b
2 T  
23  
OSC  
b
a
15  
10  
(5)  
ns  
b
2 T  
15  
OSC  
b
Data Hold after WR High  
WR High to ALE/ADV High  
BHE Hold after WR High  
INST Hold after WR High  
AD815 Hold after WR High  
BHE Hold after RD High  
INST Hold after RD High  
AD815 Hold after RD High  
0.5 T  
0.5 T  
12  
10  
ns  
OSC  
OSC  
(3)  
ns  
b
a
15  
0.5 T  
OSC  
b
T
15  
ns  
OSC  
b
b
0.5 T  
0.5 T  
15  
30  
OSC  
OSC  
(4)  
ns  
b
T
32  
ns  
OSC  
b
b
0.5 T  
0.5 T  
32  
30  
OSC  
OSC  
(4)  
ns  
RHAX  
NOTES:  
1. Testing performed at 8.0 MHz, however, the device is static by design and will typically operate below 1 Hz.  
2. Typical specifications, not guaranteed.  
3. Assuming back-to-back bus cycles.  
4. 8-bit bus only.  
c
e
number of wait states.  
5. If wait states are used, add 2 T  
n, where n  
OSC  
15  
8XC196NT  
MODE 1Ð8XC196NT SYSTEM BUS TIMING  
272267–8  
16  
8XC196NT  
MODE 1Ð8XC196NT READY TIMINGS (ONE WAIT STATE)  
272267–9  
MODE 1Ð8XC196NT BUSWIDTH TIMINGS  
27226710  
17  
8XC196NT  
BUS MODE 2ÐAC CHARACTERISTICS (Over Specified Operating Conditions)  
e
e
Test Conditions: Capacitance Load on All Pins  
100 pF, Rise and Fall Times  
10 ns.  
The system must meet these specifications to work with the 8XC196NT.  
Symbol  
Parameter  
Min  
0
Max  
Units  
ns  
b
OSC  
T
T
T
T
T
T
T
T
T
T
T
Address Valid to Ready Setup  
Non READY Time  
2.5 T  
75  
AVYV  
YLYH  
CLYX  
AVGV  
LLGV  
CLGX  
AVDV  
RLDV  
CLDV  
RHDZ  
RHDX  
No Upper Limit  
ns  
(1)  
ns  
b
30  
READY Hold after CLKOUT Low  
Address Valid to BUSWIDTH Setup  
ALE Low to BUSWIDTH Setup  
BUSWIDTH Hold after CLKOUT Low  
Address Valid to Input Data Valid  
RD active to input Data Valid  
CLKOUT Low to Input Data Valid  
End of RD to Input Data Float  
Data Hold after RD High  
T
OSC  
b
b
2.5 T  
1.5 T  
75  
60  
ns  
ns  
ns  
OSC  
OSC  
0
(2)  
ns  
b
3.5 T  
55  
OSC  
(2)  
ns  
b
2 T  
44  
OSC  
b
T
60  
ns  
ns  
ns  
OSC  
0.5 T  
OSC  
0
NOTES:  
1. If Max is exceeded, additional wait states will occur.  
c
e
2. If wait states are used, add 2 T  
n, where n  
number of wait states.  
OSC  
18  
8XC196NT  
BUS MODE 2ÐAC CHARACTERISTICS (Over Specified Operating Conditions)  
e
e
Test Conditions: Capacitance Load on All Pins  
100 pF, Rise and Fall Times  
10 ns.  
The 8XC196NT will meet these specifications  
Symbol  
Parameter  
Min  
8.0  
50  
Max  
20  
Units  
(1)  
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Frequency on XTAL1  
MHz  
XTAL  
XTAL1 Period (1/F  
)
125  
ns  
ns  
ns  
ns  
ns  
ns  
OSC  
XTAL  
a
a
XTAL1 High to CLKOUT High or Low  
CLKOUT Period  
20  
85  
XHCH  
CLCL  
CHCL  
CHLH  
CLLL  
2 T  
OSC  
b
a
CLKOUT High Period  
T
10  
T
27  
OSC  
OSC  
b
a
CLKOUT HIGH to ALE/ADV High  
CLKOUT LOW to ALE/ADV Low  
ALE/ADV Cycle Time  
0.5 T  
0.5 T  
15  
0.5 T  
15  
15  
OSC  
OSC  
OSC  
OSC  
b
a
25  
4 T  
0.5 T  
(5)  
ns  
LHLH  
LHLL  
OSC  
b
a
10  
ALE/ADV High Time  
T
T
20  
T
T
ns  
ns  
ns  
ns  
ns  
OSC  
OSC  
OSC  
b
Address Valid to ALE Low  
Address Hold After ALE/ADV Low  
ALE/ADV Low to RD Low  
RD Low to CLKOUT Low  
RD Low Period  
15  
AVLL  
LLAX  
LLRL  
b
0.5 T  
0.5 T  
20  
OSC  
OSC  
b
15  
10  
b
OSC  
a
30  
T
RLCL  
RLRH  
RHLH  
RLAZ  
LLWL  
CLWL  
QVWH  
CHWH  
WLWH  
WHQX  
WHLH  
WHBX  
WHIX  
WHAX  
RHBX  
RHIX  
OSC  
(5)  
ns  
b
2 T  
20  
OSC  
(3)  
ns  
b
a
25  
RD High to ALE/ADV High  
RD Low to Address Float  
ALE/ADV Low to WR Low  
CLKOUT Low to WR Low  
Data Valid before WR High  
CLKOUT High to WR High  
WR Low Period  
0.5 T  
5
0.5 T  
OSC  
OSC  
a
5
ns  
ns  
ns  
ns  
ns  
b
0.5 T  
10  
OSC  
b
a
T
22  
T
25  
OSC  
OSC  
b
2 T  
25  
20  
OSC  
b
a
15  
10  
(5)  
ns  
b
2 T  
OSC  
b
Data Hold after WR High  
WR High to ALE/ADV High  
BHE Hold after WR High  
INST Hold after WR High  
AD815 Hold after WR High  
BHE Hold after RD High  
INST Hold after RD High  
AD815 Hold after RD High  
0.5 T  
0.5 T  
12  
10  
ns  
OSC  
OSC  
(3)  
ns  
b
a
10  
0.5 T  
OSC  
b
T
15  
ns  
OSC  
b
b
0.5 T  
0.5 T  
15  
30  
OSC  
OSC  
(4)  
ns  
b
T
32  
ns  
OSC  
b
b
0.5 T  
0.5 T  
32  
30  
OSC  
OSC  
(4)  
ns  
RHAX  
NOTES:  
1. Testing performed at 8.0 MHz, however, the device is static by design and will typically operate below 1 Hz.  
2. Typical specifications, not guaranteed.  
3. Assuming back-to-back bus cycles.  
4. 8-bit bus only.  
c
e
number of wait states.  
5. If wait states are used, add 2 T  
n, where n  
OSC  
19  
8XC196NT  
MODE 2Ð8XC196NT SYSTEM BUS TIMING  
27226711  
20  
8XC196NT  
MODE 2Ð8XC196NT READY TIMINGS (ONE WAIT STATE)  
27226712  
MODE 2Ð8XC196NT BUSWIDTH TIMINGS  
27226713  
21  
8XC196NT  
BUS MODE 0, 1, 2, and 3ÐHOLD/HLDA TIMINGS (Over Specified Operation Conditions)  
e
e
Test Conditions: Capacitance Load on All Pins  
100 pF, Rise and Fall Times  
10 ns.  
Symbol Parameter  
Min  
Max  
Units  
(1)  
ns  
a
b
b
T
T
T
T
T
T
T
T
T
HOLD Setup Time  
65  
15  
15  
HVCH  
a
a
a
a
a
a
CLKOUT Low to HLDA Low  
15  
15  
25  
25  
15  
25  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CLHAL  
CLBRL  
HALAZ  
HALBZ  
CLHAH  
CLBRH  
HAHAX  
HAHBV  
CLKOUT Low to BREQ Low  
HLDA Low to Address Float  
HLDA Low to BHE, INST, RD, WR Weakly Driven  
CLKOUT Low to HLDA High  
b
b
b
b
25  
25  
15  
10  
CLKOUT Low to BREQ High  
HLDA High to Address No Longer Float  
HLDA High to BHE, INST, RD, WR Valid  
NOTE:  
1. To guarantee recognition at next clock.  
8XC196NT HOLD/HLDA TIMINGS  
27226714  
22  
8XC196NT  
AC CHARACTERISTICSÐSLAVE PORT  
e
SLAVE PORT WAVEFORMÐ(SLPL  
0)  
27226715  
e
SLAVE PORT TIMINGÐ(SLPL  
Symbol  
0)  
Parameter  
Min  
50  
Max  
Units  
ns  
T
T
T
T
T
T
T
T
Address Valid to WR Low  
RD High to Address Valid  
RD Low Period  
SAVWL  
SRHAV  
SRLRH  
SWLWH  
SRLDV  
SDVWH  
SWHQX  
SRHDZ  
60  
ns  
T
ns  
OSC  
OSC  
WR Low Period  
T
ns  
RD Low to Output Data Valid  
Input Data Setup to WR High  
WR High to Data Invalid  
RD High to Data Float  
60  
ns  
20  
30  
15  
ns  
ns  
ns  
NOTES:  
1. Test Conditions: F  
e
e
OSC  
e
2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests.  
e
10 ns. Capacitive Pin Load 100 pF.  
20 MHz, T  
50 ns. Rise/Fall Time  
OSC  
3. Specifications above are advanced information and are subject to change.  
23  
8XC196NT  
AC CHARACTERISTICSÐSLAVE PORT (Continued)  
e
SLAVE PORT WAVEFORMÐ(SLPL  
1)  
27226716  
e
SLAVE PORT TIMINGÐ(SLPL  
Symbol  
1)  
Parameter  
Min  
20  
Max  
Units  
ns  
T
T
T
T
T
T
T
T
T
T
T
CS Low to ALE Low  
SELLL  
RD or WR High to CS High  
ALE Low to RD Low  
60  
ns  
SRHEH  
SLLRL  
T
ns  
OSC  
OSC  
RD Low Period  
T
T
ns  
SRLRH  
SWLWH  
SAVLL  
SLLAX  
SRLDV  
SDVWH  
SWHQX  
SRHDZ  
WR Low Period  
ns  
OSC  
20  
Address Valid to ALE Low  
ALE Low to Address Invalid  
RD Low to Output Data Valid  
Input Data Setup to WR High  
WR High to Data Invalid  
RD High to Data Float  
ns  
20  
ns  
60  
ns  
20  
30  
15  
ns  
ns  
ns  
NOTES:  
1. Test Conditions: F  
e
e
OSC  
e
2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests.  
e
10 ns. Capacitive Pin Load 100 pF.  
20 MHz, T  
50 ns. Rise/Fall Time  
OSC  
3. Specifications above are advanced information and are subject to change.  
24  
8XC196NT  
EXTERNAL CLOCK DRIVE  
Symbol  
1/T  
Parameter  
Oscillator Frequency  
Min  
4
Max  
20  
Units  
MHz  
ns  
XLXL  
T
T
T
T
T
Oscillator Period (T  
High Time  
)
OSC  
50  
250  
XLXL  
c
c
0.35  
0.35  
T
T
0.65 T  
0.65 T  
10  
ns  
XHXX  
XLXX  
XLXH  
XHXL  
OSC  
OSC  
OSC  
OSC  
Low Time  
ns  
Rise Time  
ns  
Fall Time  
10  
ns  
EXTERNAL CLOCK DRIVE WAVEFORMS  
27226717  
AC TESTING INPUT, OUTPUT WAVEFORMS  
FLOAT WAVEFORMS  
27226719  
27226718  
AC Testing inputs are driven at 3.5V for a logic ‘‘1’’ and  
0.45V for a logic ‘‘0’’. Timing measurements are made  
at 2.0V for a logic ‘‘1’’ and 0.8V for logic ‘‘0’’.  
For timing purposes a Port Pin is no longer floating  
when a 150 mV change from load voltage occurs and  
begins to float when a 150 mV change from the loading  
s
V /V level occurs I /I  
OH OL OL OH  
15 mA.  
25  
8XC196NT  
WAVEFORMÐSERIAL PORTÐSHIFT REGISTER MODE  
SERIAL PORT WAVEFORMÐSHIFT REGISTER MODE (MODE 0)  
27226720  
AC CHARACTERISTICSÐSERIAL PORT-SHIFT REGISTER MODE  
SERIAL PORT TIMINGÐSHIFT REGISTER MODE (MODE 0)  
e b  
a
40 C to 125 C; V  
e
e
5.0V 10%; V  
SS  
e
g
Test Conditions: T  
0.0V; Load Capacitance  
Min Max  
6 T  
pF  
§
§
Parameter  
A
CC  
Symbol  
Units  
(2)  
t
Serial Port Clock Period (BRR 8002H) Receive Only  
T
T
T
T
T
T
T
T
T
T
ns  
50 ns  
ns  
XLXL  
OSC  
(2)  
t
Serial Port Clock Falling Edge to Rising Edge (BRR 8002H) 4 T  
b
a
50 4 T  
XLXH  
OSC  
OSC  
(2)  
e
Serial Port Clock Period (BRR  
8001H) Transmit Only  
4 T  
OSC  
XLXL  
(2)  
e
b
a
a
Serial Port Clock Falling Edge to Rising Edge (BRR  
Output Data Setup to Clock Rising Edge  
Output Data Hold after Clock Rising Edge  
Next Output Data Valid after Clock Rising Edge  
Input Data Setup to Clock Rising Edge  
Input Data Hold after Clock Rising Edge  
Last Clock Rising to Output Float  
8001H) 2 T  
50 2 T  
50 ns  
ns  
XLXH  
QVXH  
XHQX  
XHQV  
DVXH  
OSC  
OSC  
3 T  
OSC  
b
2 T  
50  
2 T  
200  
ns  
OSC  
50 ns  
ns  
OSC  
a
2 T  
OSC  
0
(1)  
ns  
XHDX  
(1)  
5 T  
ns  
XHQZ  
OSC  
NOTES:  
1. Parameters not tested.  
2. The minimum baud rate register value for Receive is 8002H. The minimum baud rate register value for Transmit is 8001H.  
26  
8XC196NT  
A to D CHARACTERISTICS  
The A/D converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of V  
.
REF  
10-BIT MODE A/D OPERATING CONDITIONS  
Symbol  
Description  
Ambient Temperature  
Digital Supply Voltage  
Analog Supply Voltage  
Sample Time  
Min  
0
Max  
Units  
a
T
A
70  
C
§
V
CC  
4.50  
4.50  
1.0  
10  
5.50  
5.50  
V
(1)  
V
V
REF  
SAM  
CONV  
OSC  
(2)  
T
T
F
ms  
(2)  
Conversion Time  
15  
20  
ms  
Oscillator Frequency  
4.0  
MHz  
NOTES:  
1. V  
must be within 0.5V of V  
.
CC  
REF  
2. The value of AD TIME is selected to meet these specifications.  
Ð
(6)  
10-BIT MODE A/D CHARACTERISTICS (Using Above Operating Conditions)  
(1)  
Parameter  
Typ*  
Min  
Max  
Units*  
1024  
10  
1024  
10  
Level  
Bits  
Resolution  
g
Absolute Error  
0
3.0  
LSBs  
LSBs  
LSBs  
LSBs  
LSBs  
LSBs  
g
0.25 0.5  
Full Scale Error  
g
0.25 0.5  
Zero Offset Error  
Non-Linearity  
g
1.0 2.0  
g
3.0  
b
a
0.75  
Differential Non-Linearity  
Channel-to-Channel Matching  
Repeatability  
0.75  
0
g
g
1.0  
0.1  
(1)  
LSBs  
g
0.25  
0
Temperature Coefficients:  
Offset  
Full Scale  
(1)  
0.009  
0.009  
0.009  
LSB/C  
LSB/C  
LSB/C  
(1)  
(1)  
Differential Non-Linearity  
(1,2,3)  
(1,2)  
dB  
b
Off Isolation  
Feedthrough  
60  
dB  
b
b
60  
60  
(1,2)  
dB  
V
Power Supply Rejection  
CC  
(4)  
Input Resistance  
750  
0
1.2K  
X
g
g
DC Input Leakage  
1.0  
3.0  
mA  
(5)  
V
b
ANGND 0.5  
a
Voltage on Analog Input Pin  
Sampling Capacitor  
V
0.5  
REF  
3.0  
pF  
*An ‘‘LSB’’ as used here has a value of approximately 5 mV.  
NOTES:  
1. These values are expected for most parts at 25 C, but are not tested or guaranteed.  
§
2. DC to 100 KHz.  
3. Multiplexer break-before-make is guaranteed.  
4. Resistance from device pin, through internal MUX, to sample capacitor.  
5. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted.  
6. All conversions performed with processor in IDLE mode.  
27  
8XC196NT  
8-BIT MODE A/D OPERATING CONDITIONS  
Symbol  
Description  
Ambient Temperature  
Digital Supply Voltage  
Analog Supply Voltage  
Sample Time  
Min  
0
Max  
Units  
a
T
A
70  
C
§
V
CC  
4.50  
4.50  
1.0  
7
5.50  
5.50  
V
(1)  
V
V
REF  
SAM  
CONV  
OSC  
(2)  
T
T
F
ms  
(2)  
Conversion Time  
20  
20  
ms  
Oscillator Frequency  
4.0  
MHz  
NOTES:  
1. V  
must be within 0.5V of V  
.
CC  
REF  
2. The value of AD TIME is selected to meet these specifications.  
Ð
(6)  
8-BIT MODE A/D CHARACTERISTICS (Using Above Operating Conditions)  
(1)  
Typ*  
Parameter  
Min  
Max  
Units*  
256  
8
256  
8
Level  
Bits  
Resolution  
g
Absolute Error  
0
1.0  
LSBs  
LSBs  
LSBs  
LSBs  
LSBs  
LSBs  
g
g
Full Scale Error  
0.5  
0.5  
Zero Offset Error  
Non-Linearity  
g
a
0
1.0  
0.5  
1.0  
b
Differential Non-Linearity  
Channel-to-Channel Matching  
Repeatability  
0.5  
g
0
0
(1)  
g
0.25  
LSBs  
Temperature Coefficients:  
Offset  
Full Scale  
(1)  
0.003  
0.003  
0.003  
LSB/C  
LSB/C  
LSB/C  
(1)  
(1)  
Differential Non-Linearity  
(1,2,3)  
(1,2)  
b
Off Isolation  
Feedthrough  
60  
dB  
b
b
60  
60  
dB  
(1,2)  
(4)  
V
Power Supply Rejection  
dB  
CC  
Input Resistance  
750  
0
1.2K  
X
g
g
DC Input Leakage  
1.0  
3.0  
mA  
(5)  
V
b
a
Voltage on Analog Input Pin  
Sampling Capacitor  
ANGND  
0.5  
V
0.5  
REF  
3.0  
pF  
*An ‘‘LSB’’ as used here has a value of approximately 5 mV.  
NOTES:  
1. These values are expected for most parts at 25 C, but are not tested or guaranteed.  
§
2. DC to 100 KHz.  
3. Multiplexer break-before-make is guaranteed.  
4. Resistance from device pin, through internal MUX, to sample capacitor.  
5. Applying voltage beyond these specifications will degrade the accuracy of other channels being converted.  
6. All conversions performed with processor in IDLE mode.  
28  
8XC196NT  
OTPROM SPECIFICATIONS  
OPERATING CONDITIONS  
Symbol  
Description  
Min  
20  
Max  
30  
Units  
T
Ambient Temperature During Programming  
Supply Voltage During Programming  
Reference Supply Voltage During Programming  
Programming Voltage  
C
§
A
(1)  
V
V
V
V
4.5  
5.5  
V
CC  
(1)  
V
4.5  
5.5  
REF  
PP  
(2)  
V
12.25  
12.25  
6.0  
12.75  
12.75  
8.0  
(2)  
V
EA Pin Voltage  
EA  
F
Oscillator Frequency during Auto  
and Slave Mode Programming  
MHz  
OSC  
F
Oscillator Frequency during  
Run-Time Programming  
6.0  
20.0  
MHz  
OSC  
NOTES:  
1. V and V  
2. V and V must never exceed the maximum specification, or the device may be damaged.  
should nominally be at the same voltage during programming.  
REF  
CC  
PP EA  
3. V and ANGND should nominally be at the same potential (0V).  
SS  
e
4. Load capacitance during Auto and Slave Mode programming  
150 pF.  
AC OTPROM PROGRAMMING CHARACTERISTICS (SLAVE MODE)  
Symbol  
Parameter  
Address Setup Time  
Address Hold Time  
Data Setup Time  
Min  
0
Max  
Units  
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
OSC  
T
OSC  
T
OSC  
T
OSC  
T
OSC  
T
OSC  
T
OSC  
T
OSC  
T
OSC  
T
OSC  
T
OSC  
T
OSC  
T
OSC  
T
OSC  
T
OSC  
T
OSC  
T
OSC  
T
OSC  
AVLL  
LLAX  
DVPL  
PLDX  
LLLH  
PLPH  
LHPL  
PHLL  
PHDX  
PHPL  
LHPL  
PLDV  
SHLL  
PHIL  
100  
0
Data Hold Time  
400  
50  
PALE Pulse Width  
(2)  
PROG Pulse Width  
50  
PALE High to PROG Low  
PROG High to next PALE Low  
Word Dump Hold Time  
220  
220  
50  
50  
PROG High to next PROG Low  
PALE High to PROG Low  
PROG Low to Word Dump Valid  
RESET High to First PALE Low  
PROG High to AINC Low  
AINC Pulse Width  
220  
220  
1100  
0
240  
50  
ILIH  
PVER Hold after AINC Low  
AINC Low to PROG Low  
PROG High to PVER Valid  
ILVH  
ILPL  
170  
220  
PHVL  
NOTES:  
1. Run-time programming is done with F  
e
e
12.5V 0.25V. For run-time programming over a full operating range, contact factory.  
e
25 C 5 C and  
C
g
5V 0.5V, T  
g
§
6.0 MHz to 10.0 MHz, V , V , V  
CC PD REF  
§
OSC  
e
g
2. This specification is for the word dump mode. For programming pulses use Modified Quick Pulse Algorithm.  
V
PP  
29  
8XC196NT  
DC OTPROM PROGRAMMING CHARACTERISTICS  
Symbol  
Parameter  
Min  
Max  
Units  
I
V
Programming Supply Current  
PP  
200  
mA  
PP  
NOTE:  
Do not apply V unti V  
damaged.  
is stable and within specifications and the oscillator/clock has stabilized or the device may be  
PP  
CC  
OTPROM PROGRAMMING WAVEFORMS  
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE  
27226721  
NOTE:  
P3.0 must be high (‘‘1’’)  
SLAVE PROGRAMMING MODE IN WORD DUMP MODE WITH AUTO INCREMENT  
27226722  
NOTE:  
P3.0 must be low (‘‘0’’)  
30  
8XC196NT  
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE  
AND AUTO INCREMENT  
27226723  
This data sheet (272267-004) applies to devices  
marked with a ‘‘D’’ at the end of the top side tracking  
number.  
The following are differences between the 272267-  
003 and 272267-004 datasheets:  
1. Changed all references of ‘‘EPROM’’ to  
‘‘OTPROM’’.  
2. Added all the Slave Port pins to the package  
diagram and pin descriptions.  
8XC196NT Design Considerations  
1. When operating in bus timing modes 1 or 2, the  
upper and lower address/data lines must be  
latched. Even in 8-bit bus mode, the upper ad-  
dress lines must be latched. In modes 0 and 3,  
the upper address lines DO NOT NEED to be  
latched in 8-bit bus width mode. But in 16-bit  
buswidth mode the upper address lines need to  
be latched.  
3. Added INTOUT pin to pin descriptions.  
4. Changed ILI1 (input leakage current for Port 0)  
g
g
from 1 mA to 3 mA.  
5. Removed T  
from AC characterisics and  
LLYV  
waveform diagrams.  
a
in Mode 0 and 3, changed from 4 ns  
RLCL  
min. to 5 ns min.  
6.  
T
b
7.  
T
b
in Mode 0 and 3, changed from T  
b
WHQX  
30 min. to T  
OSC  
8XC196NT ERRATA see Faxback  
35 min.  
OSC  
Ý
2344  
1. ILLEGAL Opcode interrupt vector.  
8. Clarified the Ready waveform timings for Mode  
*’’.  
a
0 and 3, by adding ‘‘ 2 T  
OSC  
2. Aborted Interrupt vectors to lowest priority.  
3. PTS Request during Interrupt latency.  
b
9.  
T
LHLL  
to T  
in Mode 1, changed from T  
b
10 min.  
OSC  
20 min.  
OSC  
b
b
10. T  
min. to 0.5 T  
in Mode 1, changed from 0.5 T  
b
15  
20  
AVLL  
OSC  
OSC  
20 min.  
OSC  
DATA SHEET REVISION HISTORY  
11. T  
in Mode 1, changed from 0.5 T  
b
LLAX  
min. to 0.5 T  
25 min.  
OSC  
This datasheet applies to devices marked with a ‘‘D’’  
at the end of the topside tracking number. The top-  
side tracking number consists of nine characters  
and is the second line on the top side of the device.  
Datasheets are changed as new device information  
becomes available. Verify with your local Intel sales  
office that you have the latest version before finaliz-  
ing a design or ordering devices.  
b
OSC  
12. T  
LHLL  
to T  
in Mode 2, changed from T  
b
10 min.  
20 min.  
OSC  
13. T  
and T  
for the Serial Port timings  
were changed to reflect the minimum baudrate  
for receive and transmit modes.  
XLXL  
XLXH  
14. Added the 8XC196NT ERRATA section.  
31  
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