8XC196MD
8XC196MC AND 8XC196MD
DIFFERENCES
PI MASK and PI PEND Registers
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The PI MASK/PI PEND registers contain the bits
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for the Compare Module 5 (COMP5) Waveform Gen-
erator (WG), Timer 1 Overflow (TFI), and Timer 2
Overflow (TF2) mask/status flag. The diagram be-
low shows the registers. Notice that the COMP5 bit
is a reserved bit on the 8XC196MC. The 8XC196MC
User’s Manual should be referenced for details
about the Waveform Generator, Compare Modules,
and Timers.
INT MASK1/INT PEND1 Registers
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There are some differences between the
8XC196MC and 8XC196MD INT MASK1/
INT PEND1 registers. The 8XC196MD interrupt
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mask and pending registers are shown below. No-
tice that the CAPCOM5, COMP4, and CAPCOM4
bits are reserved bits on the 8XC196MC. The PI bit
of the INT PEND1 register will be set when a
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Waveform Generator or Compare Module 5 event
occurs and the corresponding bit in the PI MASK
PI MASK (1FBEH) and
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PI PEND (1FBCH, Read Only)
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register is set. The PI interrupt vector can be taken
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7
6
5
4
3
2
1
0
when the PI bit in the INT MASK1 register is set.
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The 8XC196MC User’s Manual should be refer-
enced for details about the interrupts.
RSV
COMP5*
RSV
WG
RSV
TF2
RSV
TF1
e
RSV
RESERVED BIT. MUST WRITE AS 0,
READ AS 1.
THIS BIT RESERVED ON 8XC196MC.
e
*
INT MASK1 (0031H)
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and INT PEND1 (0012H)
Figure 5. Peripheral Interrupt Mask
and Status Registers
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7
6
5
4
3
2
1
0
RSV EXTINT PI CAPCOM5* COMP4* CAPCOM4* COMP3 CAPCOM3
The PI bit in the INT PEND1 register is set if a
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Waveform Generator event or Compare Module 5
event occurs and the corresponding PI MASK bit is
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set. For either of these events to cause an interrupt,
e
RSV
e
RESERVED BIT. MUST WRITE AS 0
THIS BIT RESERVED ON 8XC196MC.
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Figure 3. Interrupt Mask and Status Registers
the PI bit in the INT MASK1 register and the corre-
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sponding event bit in the PI MASK register must be
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set.
PTSSRV and PTSSEL Register
Similarly, the TOVF bit in the INT PEND register is
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set if Timer 1 or Timer 2 overflow and the corre-
sponding bit in the PI MASK register is set. For ei-
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ther of these two events to cause an interrupt, the
TOVF bit in the INT MASK register and the corre-
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sponding event bit in the PI MASK must be set.
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Similarly, there are differences between 8XC196MC
and 8XC196MD PTS registers. The 8XC196MD PTS
registers are shown below. Notice the CAPCOM5,
COMP4, and CAPCOM4 bits are reserved bits on
the 8XC196MC. The PI bit in the PTSSRV will be set
when a Waveform Generator or Compare Module 5
end of PTS interrupt occurs and the corresponding
Upon a PI and/or a TOVF interrupt, it may be neces-
sary to check if the Compare Module 5, the Wave-
form Generator, Timer 1, or Timer 2 event caused
the interrupt. The PI PEND will give this informa-
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tion. However, it should be noted that reading the
bit in the PI MASK register is set. The PI PTS vec-
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tor can be used when the PI bit in the PTSSEL regis-
ter is set. The 8XC196MC User’s Manual should be
referenced for details about the PTS.
PI PEND register will clear the register. So the indi-
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vidual bits in the PI PEND register must be read by
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PTSSEL (0004H) and PTSSRV (0006H)
10
loading PI PEND into another ‘‘shadow’’ register,
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15
14
13
12
11
9
8
then checking the ‘‘shadow’’ register to see what
event occurred.
RSV EXTINT
PI
CAPCOM5* COMP4* CAPCOM4* COMP3 CAPCOM3
7
6
5
4
3
2
1
0
COMP2 CAPCOM2 COMP1 CAPCOM1 COMP0 CAPCOM0 AD DONE TOVF
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e
RSV
e
RESERVED BIT. MUST WRITE AS 0
THIS BIT RESERVED ON 8XC196MC.
*
Figure 4. PTS Select and Service Registers
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