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8P34S1212NLGI8

型号：

8P34S1212NLGI8

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

19 页

PDF大小：

443 K

下载PDF手册

IDT8P34S1212I

Datasheet

1:12 LVDS Output 1.8V Fanout Buffer

Description

Features

The IDT8P34S1212I is a high-performance differential LVDS fanout

buffer. The device is designed for the fanout of high-frequency, very

low additive phase-noise clock and data signals. The

IDT8P34S1212I is characterized to operate from a 1.8V power

supply. Guaranteed output-to-output and part-to-part skew

characteristics make the IDT8P34S1212I ideal for those clock

distribution applications that demand well-defined performance and

repeatability.

• 12 low skew, low additive jitter LVDS output pairs

• Two selectable, differential clock input pairs

• Differential CLK0, CLK1 pairs can accept the following differential

input levels: LVDS, CML

• Maximum input clock frequency: 1.2GHz (maximum)

• LVCMOS/LVTTL interface levels for the control input select pin

• Output skew: 10ps (typical)

Two selectable differential inputs and 12 low skew outputs are

available. The integrated bias voltage reference enables easy

interfacing of single-ended signals to the device inputs. The device is

optimized for low power consumption and low additive phase noise.

• Propagation delay: 340ps (typical)

• Low additive phase jitter, RMS; f_REF= 156.25MHz, V_PP= 1V,

12kHz- 20MHz: 41fs (typical)

• Maximum device current consumption (I_DD): 227mA (maximum)

at 1.89V

• Full 1.8V supply voltage

• Lead-free (RoHS 6), 40-Lead VFQFN packaging

• -40°C to 85°C ambient operating temperature

Block Diagram

Pin Assignment

nQ0

30 29 28 27 26 25 24 23 22 21

nQ1

nQ8

nQ3

IDT8P34S1212I

40-Lead VFQFN

nQ2

nQ3

6.0mm x 6.0mm x 0.90mm

package body

nQ9 35

16 Q2

CLK0

nQ4

Q10

nQ10

Q11

nQ1

4.65mm x 4.65mm ePad Size

NL Package

nCLK0

nQ5

nQ0

f_REF

Top View

nQ11

nQ6

CLK1

nQ7

nCLK1

nQ8

nQ9

SEL

Q10

nQ10

V_REF

Q11

nQ11

November 24, 2017

IDT8P34S1212I Datasheet

Pin Descriptions and Characteristics

Note 1.

Table 1. Pin Descriptions

Number

Name

SEL

Type

Description

Reference select control. See Table 3 for function.

LVCMOS/LVTTL interface levels.

Input

Pulldown

CLK1

nCLK1

Non-inverting differential clock/data input.

Inverting differential clock/data input.

Do not connect.

Pulldown/

Pullup

Input

4, 10

Unused

Power

5, 6, 11, 20,

31, 40

V_DD

Power supply pins.

Bias voltage reference. Provides an input bias voltage for the CLKx, nCLKx

input pairs in AC-coupled applications. Refer to Figures 2B and 2C for

applicable AC-coupled input interfaces.

V_REF

Pulldown/

Pullup

nCLK0

Input

Inverting differential clock/data input.

CLK0

Q0, nQ0

Q1, nQ1

Q2, nQ2

Q3, nQ3

GND

Input

Pulldown

Non-inverting differential clock/data input.

Differential output pair 0. LVDS interface levels.

Differential output pair 1. LVDS interface levels.

Differential output pair 2. LVDS interface levels.

Differential output pair 3. LVDS interface levels.

Power supply ground.

12, 13

14, 15

16, 17

18, 19

21, 30

22, 23

24, 25

26, 27

28, 29

32, 33

34, 35

36, 37

38, 39

Output

Power

Output

Q4, nQ4

Q5, nQ5

Q6, nQ6

Q7, nQ7

Q8, nQ8

Q9, nQ9

Q10, nQ10

Q11, nQ11

Differential output pair 4. LVDS interface levels.

Differential output pair 5. LVDS interface levels.

Differential output pair 6. LVDS interface levels.

Differential output pair 7. LVDS interface levels.

Differential output pair 8. LVDS interface levels.

Differential output pair 9. LVDS interface levels.

Differential output pair 10. LVDS interface levels.

Differential output pair 11. LVDS interface levels.

Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

C_IN

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

Input Pulldown Resistor

Input Pullup Resistor

R_PULLDOWN

R_PULLUP

k

Note 1.

Table 3. SEL Input Function Table

Input

SEL

0 (Default)

Operation

CLK0, nCLK0 is the selected differential clock input.

CLK1, nCLK1 is the selected differential clock input.

1. SEL is an asynchronous control.

November 24, 2017

IDT8P34S1212I Datasheet

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress

specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or

AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Item

Rating

Supply Voltage, V_DD

Inputs, V_I

4.6V

-0.5V to V_DD+ 0.5V

Outputs, I_O

Continuous Current

Surge Current

10mA

15mA

Input Sink/Source, I_REF

±2mA

Maximum Junction Temperature, T_J,MAX

Storage Temperature, T_STG

125°C

-65°C to 150°C

2000V

ESD - Human Body Model^{Note 1.}

ESD - Charged Device Model^{Note 1.}

1500V

According to JEDEC JS-001-2012/JESD11-C101E.

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, V = 1.8V ± 5%, T = -40°C to 85°C

Symbol Parameter

V_DDPower Supply Voltage

Test Conditions

Minimum

Typical

Maximum

Units

1.71

1.8

1.89

Q0 to Q11 terminated 100 between

I_DD

Power Supply Current

185

227

nQx, Qx

Table 4B. LVCMOS/LVTTL DC Characteristics, V = 1.8V ± 5%, T = -40°C to 85°C

Symbol Parameter

Test Conditions

Minimum

0.65 * V_DD

-0.3

Typical

Maximum

V_DD+ 0.3

0.35 * V_DD

150

Units

V_IH

V_IL

I_IH

Input High Voltage

Input Low Voltage

Input High Current

Input Low Current

SEL

V_DD= V_IN= 1.89V

µA

I_IL

V_DD= 1.89V, V_IN= 0V

-10

November 24, 2017

IDT8P34S1212I Datasheet

Table 4C. Differential Inputs Characteristics, V = 1.8V ± 5%, T = -40°C to 85°C

Symbol Parameter

Input High CLK0, CLK1,

Test Conditions

Minimum

Typical

Maximum

Units

I_IH

V_IN= V_DD= 1.89V

150

µA

Current

nCLK0, nCLK1

CLK0, CLK1

V_IN= 0V, V_DD= 1.89V

-10

µA

Input Low

Current

I_IL

nCLK0, nCLK1

-150

Reference Voltage for_NIn_otp_eu_3.t

Bias^{Note 1.}

V_REF

V_PP

I_REF= +100µA, V_DD= 1.8V

V_DD= 1.89V

0.9

0.2

0.9

1.30

1.0

Peak-to-Peak Voltage

Common Mode Input

Voltage^{Note 2. Note 3.}

V_CMR

V_DD– (V_PP/2)

V_REFspecification is applicable to the AC-coupled input interfaces shown in Figures 2B and 2C.

Common mode input voltage is defined as crosspoint voltage.

V_ILshould not be less than -0.3V and V_IHshould not be higher than V_DD

Note 1.

Table 4D. LVDS DC Characteristics, V = 1.8V ± 5%, T = -40°C to 85°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

454

Units

V_OD

V_OD

V_OS

Differential Output Voltage

outputs loaded with 100

247

V_ODMagnitude Change

Offset Voltage

1.00

1.40

V_OS

V_OSMagnitude Change

Output drive current must be sufficient to drive up to 30cm of PCB trace (assume nominal 50 impedance).

November 24, 2017

IDT8P34S1212I Datasheet

AC Electrical Characteristics

Note 1.

Table 5. AC Electrical Characteristics, V = 1.8V ± 5%, T = -40°C to 85°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum Units

Input

CLK[0:1],

f_REF

1.2

GHz

V/ns

Frequency nCLK[0:1]

Input CLK[0:1],

Edge Rate nCLK[0:1]

V/t

1.5

Propagation Delay^{Note 2.}

Note 3.

t_PD

CLK[0:1]; nCLK[0:1] to any Qx, nQx

200

340

450

tsk(o)

tsk(i)

Output Skew^{Note 4. Note 5.}

Input Skew^{Note 5.}

tsk(p)

tsk(pp)

Pulse Skew

f_REF= 100MHz

Part-to-Part Skew^{Note 6.}

250

f_REF= 122.88MHz Square Wave, V_PP= 1V,

Integration Range: 1kHz – 40MHz

225

200

150

_REF= 122.88MHz Square Wave, V_PP= 1V,

Integration Range: 10kHz – 20MHz

f_REF= 122.88MHz Square Wave, V_PP= 1V,

Integration Range: 12kHz – 20MHz

f_REF= 156.25MHz Square Wave, V_PP= 1V,

Integration Range: 1kHz – 40MHz

Buffer Additive Phase

Jitter, RMS; refer to

Additive Phase Jitter

Section

_REF= 156.25MHz Square Wave, V_PP= 1V,

Integration Range: 10kHz – 20MHz

t_JIT

f_REF= 156.25MHz Square Wave, V_PP= 1V,

Integration Range: 12kHz – 20MHz

f_REF= 156.25MHz Square Wave, V_PP= 0.5V,

Integration Range: 1kHz – 40MHz

123

_REF= 156.25MHz Square Wave, V_PP= 0.5V,

Integration Range: 10kHz – 20MHz

f_REF= 156.25MHz Square Wave, V_PP= 0.5V,

Integration Range: 12kHz – 20MHz

10% to 90%,

400

260

outputs loaded with 100 

20% to 80%,

outputs loaded with 100 

t_R/ t_F

Output Rise/ Fall Time

110

MUX_ISOLATIONMux Isolation^{Note 7.}

_REF= 100MHz

72.6

Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equi-

librium has been reached under these conditions.

Measured from the differential input crossing point to the differential output crossing point

Input V_PP= 400mV

Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.

This parameter is defined in accordance with JEDEC Standard 65.

Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and

with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.

Qx, nQx outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information section.

November 24, 2017

IDT8P34S1212I Datasheet

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value of

the fundamental. This ratio is expressed in decibels (dBm) or a ratio

of the power in the 1Hz band to the power in the fundamental. When

the required offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the entire

time record of the signal. It is mathematically possible to calculate an

expected bit error rate given a phase noise plot.

Additive Phase Jitter @ 74fs (typical)

Offset from Carrier Frequency (Hz)

As with most timing specifications, phase noise measurements have

issues relating to the limitations of the measurement equipment. The

noise floor of the equipment can be higher or lower than the noise

floor of the device. Additive phase noise is dependent on both the

noise floor of the input source and measurement equipment.

Measured using a Wenzel Oscillator as the input source.