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8P34S2102

型号：

8P34S2102

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

19 页

PDF大小：

438 K

下载PDF手册
Dual 1:2 LVDS Output 1.8V Fanout Buffer  
Features  
8P34S2102  
Datasheet  
Description  
▪ Dual 1:2 low skew, low additive jitter LVDS fanout buffers  
The 8P34S2102 is a high-performance, low-power, differential  
dual 1:2 LVDS output, 1.8V fanout buffer. The device is designed  
for the fanout of high-frequency, very low additive phase-noise  
clock and data signals. Two independent buffer channels are  
available. Each channel has two low-skew outputs. High isolation  
between channels minimizes noise coupling. AC characteristics  
such as propagation delay are matched between channels.  
Guaranteed output-to-output and part-to-part skew characteristics  
make the 8P34S2102 ideal for those clock distribution  
▪ Matched AC characteristics across both channels  
▪ High isolation between channels  
▪ Low power consumption  
▪ Both differential CLKA, nCLKA and CLKB, nCLKB inputs  
accept LVDS, LVPECL and single-ended LVCMOS  
levels  
▪ Maximum input clock frequency: 2GHz  
▪ Output amplitudes: 350mV, 500mV (selectable)  
▪ Output bank skew: 8ps typical  
applications demanding well-defined performance and  
repeatability. The device is characterized to operate from a 1.8V  
power supply. The integrated bias voltage references enable easy  
interfacing of AC-coupled signals to the device inputs.  
▪ Output skew: 10ps typical  
▪ Low additive phase jitter, RMS: 45fs typical  
(fREF = 156.25MHz, 12kHz - 20MHz)  
▪ Full 1.8V supply voltage mode  
▪ Device current consumption (IDD): 76mA typical  
▪ Lead-free (RoHS 6), 16-lead VFQFN packaging  
▪ -40°C to 85°C ambient operating temperature  
▪ Supports case temperature up to 105°C  
Block Diagram  
VDD  
51k  
QA0  
nQA0  
CLKA  
nCLKA  
QA1  
nQA1  
51k  
51k  
Voltage  
Reference  
VREF  
VDD  
51k  
51k  
QB0  
nQB0  
CLKB  
nCLKB  
QB1  
nQB1  
VDD  
51k  
51k  
SELA  
8P34S2102 transistor count: 293  
©2016 Integrated Device Technology, Inc.  
1
October 20, 2016  
8P34S2102 Datasheet  
Pin Assignments  
Figure 1. Pin Assignments for 3mm x 3mm VFQFN Package – Top View  
11  
10  
9
12  
13  
14  
15  
VREF  
nCLKA  
CLKA  
VDD  
8
7
6
5
QB0  
nQB0  
QB1  
8P34S2102  
nQB1 16  
1
2
3
4
Pin Descriptions  
Table 1. Pin Descriptions  
Number  
Name  
Type[a]  
Power  
Description  
1
2
GND  
SELA  
CLKB  
nCLKB  
VDD  
Power supply ground.  
Input (PU)  
Input (PD)  
Control input. Output amplitude select.  
3
Non-inverting differential clock/data input for channel B.  
4
Input (PD/PU) Inverting differential clock/data input for channel B.  
5
Power  
Power supply pin.  
6
CLKA  
nCLKA  
VREF  
QA0  
Input (PD)  
Non-inverting differential clock/data input for channel A.  
7
Input (PD/PU) Inverting differential clock/data input for channel A.  
8
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Power  
Bias voltage reference for CLKA, nCLKA and CLKB, nCLKB input pairs.  
9
Differential output A0. LVDS interface levels.  
Differential output A0. LVDS interface levels.  
Differential output A1. LVDS interface levels.  
Differential output A1. LVDS interface levels.  
Differential output B0. LVDS interface levels.  
Differential output B0. LVDS interface levels.  
Differential output B1. LVDS interface levels.  
Differential output B1. LVDS interface levels.  
Exposed pad of package. Connect to ground.  
10  
11  
12  
13  
14  
15  
16  
ePad  
nQA0  
QA1  
nQA1  
QB0  
nQB0  
QB1  
nQB1  
GND_EPAD  
[a] Pull-up (PU) and pull-down (PD) resistors are indicated in parentheses. Pull-up and pull-down refers to internal input resistors.  
See Table 4, DC Input Characteristics, for typical values.  
©2016 Integrated Device Technology, Inc.  
2
October 20, 2016  
8P34S2102 Datasheet  
Function Tables  
Table 2. SELA Output Amplitude Selection Table  
SELA  
QA, QB Output Amplitude (mV)  
0
350  
500  
1 (default)  
©2016 Integrated Device Technology, Inc.  
3
October 20, 2016  
8P34S2102 Datasheet  
Absolute Maximum Ratings  
NOTE: The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to  
the device. Functional operation of the 8P34S2102 at absolute maximum ratings is not implied. Exposure to absolute maximum rating  
conditions may affect device reliability.  
Table 3. Absolute Maximum Ratings  
Item  
Rating  
Supply voltage, VDD  
Inputs, VI  
4.6V  
-0.5V to VDD + 0.5V  
Outputs, IO  
Continuous current  
Surge current  
10mA  
15mA  
Input sink/source, IREF  
±2mA  
Maximum Junction Temperature, TJ,MAX  
125°C  
Storage Temperature, TSTG  
ESD - Human Body Model[a]  
-65°C to 150°C  
2000V  
ESD - Charged Device Model[a]  
1500V  
[a] According to JEDEC JS-001-2012/JESD22-C101E.  
DC Electrical Characteristics  
Table 4. DC Input Characteristics  
Symbol  
CIN  
RPULLDOWN  
RPULLUP  
Parameter  
Input capacitance  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
2
pF  
k  
k  
Input pull-down resistor  
Input pull-up resistor  
51  
51  
Table 5. Power Supply DC Characteristics, VDD = 1.8V ± 5%, TA = -40°C to 85°C  
Symbol  
Parameter  
Power supply voltage  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VDD  
1.71  
1.8  
1.89  
V
QA[0:1], QB[0:1]  
outputs terminated  
100between nQx, Qx  
500mV amplitude  
350mV amplitude  
93  
76  
120  
96  
mA  
mA  
Power supply  
current  
IDD  
©2016 Integrated Device Technology, Inc.  
4
October 20, 2016  
8P34S2102 Datasheet  
Table 6. LVCMOS Inputs DC Characteristics, VDD = 1.8V ± 5%, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VIH  
VIL  
IIH  
Input high voltage  
SELA  
SELA  
SELA  
SELA  
0.65 · VDD  
-0.3  
VDD + 0.3  
0.35 · VDD  
10  
V
V
Input low voltage  
Input high current  
Input low current  
VIN = VDD = 1.89V  
µA  
µA  
IIL  
VIN = 0V, VDD = 1.89V  
-150  
Table 7. Differential Inputs Characteristics, VDD = 1.8V ± 5%, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
IIH  
Input high current  
CLKA, nCLKA  
VIN = VDD = 1.89V  
150  
µA  
CLKB, nCLKB  
CLKA, CLKB  
nCLKA, nCLKB  
VIN = 0V, VDD = 1.89V  
VIN = 0V, VDD = 1.89V  
IREF = +100µA, VDD = 1.8V  
-10  
-150  
0.9  
µA  
µA  
V
IIL  
Input low current  
VREF  
Reference voltage[a]  
1.30  
[a] VREF specification is applicable to the AC-coupled input interfaces shown in Figure 5 and Figure 6.  
Table 8. LVDS DC Characteristics, VDD = 1.8V ± 5%, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VOD  
VOS  
VOD Magnitude Change  
VOS Magnitude Change  
50  
50  
mV  
mV  
©2016 Integrated Device Technology, Inc.  
5
October 20, 2016  
8P34S2102 Datasheet  
AC Electrical Characteristics  
Table 9. AC Electrical Characteristics, VDD = 1.8V ± 5%, TA = -40°C to 85°C [a]  
Test Conditions  
Symbol  
fREF  
Parameter  
Minimum Typical  
Maximum  
Units  
Input frequency  
Input edge rate  
2
GHz  
V/ns  
ps  
V/t  
tPD  
1.5  
Propagation delay[b], [c] CLKA to any QAx, CLKB to any nQBx  
Output skew[d], [e]  
100  
225  
10  
8
400  
30  
tsk(o)  
tsk(b)  
tsk(p)  
tsk(pp)  
ps  
Output bank skew[e], [f]  
Pulse skew[g]  
Part-to-part skew[e], [h]  
25  
ps  
fREF = 100MHz  
5
20  
ps  
200  
75  
ps  
Buffer Additive Phase  
Jitter, RMS;  
500mV amplitude;  
refer to Additive Phase  
Jitter  
f
REF = 156.25MHz;  
60  
45  
fs  
Integration range: 1kHz – 40MHz  
tJIT  
fREF = 156.25MHz square wave, VPP = 1V;  
Integration range: 12kHz – 20MHz  
55  
fs  
N(30M) Clock single-side band  
30MHz offset from carrier and noise floor  
< -160  
-71  
dBc/Hz  
dB  
phase noise  
f
QA = 491.52MHz, fQB = 61.44MHz;  
Spurious suppression,  
measured between neighboring outputs  
tJIT, SP  
coupling between  
channels  
f
QA = 491.52MHz, fQB = 15.36MHz;  
-82  
dB  
measured between neighboring outputs  
10% to 90%, outputs loaded with 100  
20% to 80%, outputs loaded with 100  
220  
110  
400  
250  
1.2  
ps  
ps  
V
tR / tF  
VPP  
VPP_DIFF  
Output rise/ fall time  
Input voltage  
amplitude  
CLKA,  
CLKB  
0.15  
0.3  
Differential  
input voltage  
amplitude  
CLKA,  
CLKB  
2.4  
V
V
VCMR  
Common mode  
input voltage[i]  
1.1  
VDD – (VPP/2)  
SELA = 0, outputs loaded with 100  
SELA = 1, outputs loaded with 100  
SELA = 0  
247  
300  
350  
500  
454  
650  
mV  
mV  
V
Differential  
output voltage  
VOD  
0.77  
0.68  
VOS  
Offset voltage  
SELA = 1  
V
[a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device  
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal  
equilibrium has been reached under these conditions.  
[b] Measured from the differential input crossing point to the differential output crossing point.  
[c] Input VPP = 400mV.  
[d] Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross  
points.  
©2016 Integrated Device Technology, Inc.  
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October 20, 2016  
8P34S2102 Datasheet  
[e] This parameter is defined in accordance with JEDEC Standard 65.  
[f] Defined as skew within a bank of outputs at the same voltage and with equal load conditions.  
[g] Output pulse skew is the absolute value of the difference of the propagation delay times: tPLH - tPHL .  
[h] Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and  
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.  
[i]  
Common Mode Input Voltage is defined as the cross-point voltage.  
©2016 Integrated Device Technology, Inc.  
7
October 20, 2016  
8P34S2102 Datasheet  
Additive Phase Jitter  
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase  
Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise  
is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value  
of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental.  
When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the  
fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over  
the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.  
Figure 2. Additive Phase Jitter. Frequency: 156.25MHz, Integration range: 12kHz to 20MHz = 45fs typical  
Offset from Carrier Frequency (Hz)  
As with most timing specifications, phase noise measurements have issues relating to the limitations of the measurement equipment. The  
noise floor of the equipment can be higher or lower than the noise floor of the device. Additive phase noise is dependent on both the  
noise floor of the input source and measurement equipment.  
Measured using a Wenzel 156.25MHz Oscillator as the input source.  
©2016 Integrated Device Technology, Inc.  
8
October 20, 2016  
8P34S2102 Datasheet  
Applications Information  
Recommendations for Unused Input and Output Pins  
Inputs:  
CLK/nCLK Inputs  
For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for  
additional protection, a 1kresistor can be tied from CLK to ground.  
Outputs:  
LVDS Outputs  
All unused LVDS output pairs can be either left floating or terminated with 100across. If they are left floating there should be no trace  
attached.  
VREF  
The unused VREF pin can be left floating. We recommend that there is no trace attached.  
©2016 Integrated Device Technology, Inc.  
9
October 20, 2016  
8P34S2102 Datasheet  
Wiring the Differential Input to Accept Single-Ended Levels  
Figure 3 shows how a differential input can be wired to accept single ended levels. The reference voltage V1 = VDD/2 is generated by the  
bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as  
close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1in the center of the input voltage  
swing. For example, if the input clock swing is 1.8V and VDD = 1.8V, R1 and R2 value should be adjusted to set V1 at 0.9V. The values  
below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output  
impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at  
the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission  
line impedance. For most 50applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading  
for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are  
reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced while  
maintaining an edge rate faster than 1V/ns. The datasheet specifies a lower differential amplitude, however this only applies to differential  
signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD  
+ 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized  
for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal.  
Figure 3. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels  
©2016 Integrated Device Technology, Inc.  
10  
October 20, 2016  
8P34S2102 Datasheet  
1.8V Differential Clock Input Interface  
The CLK /nCLK accepts LVDS, LVPECL and other differential signals. The differential input signal must meet both the VPP and VCMR  
input requirements. Figure 4 to Figure 6 show interface examples for the CLK /nCLK input driven by the most common driver types. The  
input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please  
consult with the vendor of the driver component to confirm the driver termination requirements.  
Figure 4. Differential Input Driven by an LVDS Driver - DC Coupling  
Figure 5. Differential Input Driven by an LVDS Driver - AC Coupling  
Figure 6. Differential Input Driven by an LVPECL Driver - AC Coupling  
©2016 Integrated Device Technology, Inc.  
11  
October 20, 2016  
8P34S2102 Datasheet  
LVDS Driver Termination  
For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90and 132. The actual value  
should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100  
parallel resistor at the receiver and a 100differential transmission-line environment. In order to avoid any transmission-line reflection  
issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS  
compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown  
in Figure 7 can be used with either type of output structure. Figure 8, which can also be used with both output types, is an optional  
termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a  
non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In  
addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for  
compatibility with the output.  
Figure 7. Standard LVDS Termination  
ZO ZT  
LVDS  
Driver  
LVDS  
Receiver  
ZT  
Figure 8. Optional LVDS Termination  
Z
T
T
2
ZO ZT  
LVDS  
LVDS  
Driver  
Receiver  
C
Z
2
©2016 Integrated Device Technology, Inc.  
12  
October 20, 2016  
8P34S2102 Datasheet  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 9. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed  
on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts.  
While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific  
and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis  
and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved  
when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is  
also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to  
avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug  
and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern.  
Note: These recommendations are to be used as a guideline only. For further information, please refer to the application note on the  
Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology.  
Figure 9. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
SOLDER  
SOLDER  
PIN  
EXPOSED HEAT SLUG  
PIN  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
©2016 Integrated Device Technology, Inc.  
13  
October 20, 2016  
8P34S2102 Datasheet  
Case Temperature Considerations  
This device supports applications in a natural convection environment which does not have any thermal conductivity through ambient air.  
The printed circuit board (PCB) is typically in a sealed enclosure without any natural or forced air flow and is kept at or below a specific  
temperature. The device package design incorporates an exposed pad (ePad) with enhanced thermal parameters which is soldered to  
the PCB where most of the heat escapes from the bottom exposed pad. For this type of application, it is recommended to use the  
junction-to-board thermal characterization parameter JB (Psi-JB) to calculate the junction temperature (TJ) and ensure it does not  
exceed the maximum allowed junction temperature in the Absolute Maximum Rating table.  
The junction-to-board thermal characterization parameter, JB, is calculated using the following equation:  
TJ = TCB + JB x PD, where  
TJ = Junction temperature at steady state condition in (oC).  
T
CB = Case temperature (Bottom) at steady state condition in (oC).  
JB = Thermal characterization parameter to report the difference between junction temperature and the temperature of the board  
measured at the top surface of the board.  
PD = power dissipation (W) in desired operating configuration.  
T
J
T
CB  
The ePad provides a low thermal resistance path for heat transfer to the PCB and represents the key pathway to transfer heat away from  
the IC to the PCB. It’s critical that the connection of the exposed pad to the PCB is properly constructed to maintain the desired IC case  
temperature (TCB). A good connection ensures that temperature at the exposed pad (TCB) and the board temperature (TB) are relatively  
the same. An improper connection can lead to increased junction temperature, increased power consumption and decreased electrical  
performance. In addition, there could be long-term reliability issues and increased failure rate.  
Example Calculation for Junction Temperature (TJ): TJ = TCB + JB x PD  
Package type  
Body size (mm)  
ePad size (mm)  
Thermal Via  
16 VFQFN  
3 x 3 x 0.9  
1.7 x 1.7  
2 x 2 Matrix  
1.3oC/W  
105oC  
JB  
TCB  
PD  
0.21W  
For the variables above, the junction temperature is equal to 105.3oC. Since this is below the maximum junction temperature of 125oC,  
there are no long term reliability concerns. In addition, since the junction temperature at which the device was characterized using forced  
convection is 119oC, this device can function without the degradation of the specified AC or DC parameters.  
©2016 Integrated Device Technology, Inc.  
14  
October 20, 2016  
8P34S2102 Datasheet  
Power Considerations  
This section provides information on power dissipation and junction temperature for the 8P34S2102.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The following is the power dissipation for VDD = 1.8V + 5% = 1.89V, which gives worst case results.  
Maximum current at 85°C: VDD_MAX = 112mA.  
▪ Power_MAX = VDD_MAX * IDD_MAX = 1.89V * 112mA = 211.68mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that  
the bond wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow  
and a multi-layer board, the appropriate value is 74.7°C/W per Table 10 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.21168W * 74.7°C/W = 100.8°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the  
type of board (multi-layer).  
Table 10. Thermal Resistance JA for 16-lead VFQFN, Forced Convection  
JA (°C/W) vs. Air Flow (m/s)  
0
1
2
Meters per Second  
16-lead VFQFN Multi-Layer PCB, JEDEC Standard Test Boards  
74.7  
65.3  
58.5  
©2016 Integrated Device Technology, Inc.  
15  
October 20, 2016  
8P34S2102 Datasheet  
Package Drawings  
Figure 10. 16-lead VFQFN Package Outline and Dimensions  
©2016 Integrated Device Technology, Inc.  
16  
October 20, 2016  
8P34S2102 Datasheet  
Package Drawings, continued  
Figure 11. 16-lead VFQFN Package Outline and Dimensions  
©2016 Integrated Device Technology, Inc.  
17  
October 20, 2016  
8P34S2102 Datasheet  
Marking Diagram  
1. “XXX” indicates the last three characters of the Asm lot number.  
2. Line 2:  
▪ “YWW” indicates the date code (Y is the last digit of the year, and  
“WW” is a work week number that the part was assembled.  
▪ “$”: mark code.  
3. Line 3 indicates the truncated part number.  
Ordering Information  
Table 11. Ordering Information  
Part/Order Number  
Marking  
Package  
Shipping Packaging  
Temperature  
8P34S2102NLGI  
8P34S2102NLGI8  
S202I  
S202I  
Tray  
Tape & Reel, Pin 1 Orientation:  
EIA-481-C  
16-lead VFQFN, Lead-Free  
-40°C to 85°C  
8P34S2102NLGI/W  
S202I  
Tape & Reel, Pin 1 Orientation:  
EIA-481-D/E  
Table 12. Pin 1 Orientation in Tape and Reel Packaging  
Part Number Suffix  
Pin 1 Orientation  
Illustration  
8
Quadrant 1 (EIA-481-C)  
/W  
Quadrant 2 (EIA-481-D/E)  
©2016 Integrated Device Technology, Inc.  
18  
October 20, 2016  
8P34S2102 Datasheet  
Revision History  
Revision Date  
Description of Change  
October 20, 2016  
Initial Final datasheet.  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
www.IDT.com/go/support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance spec-  
ifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information  
contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied  
warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of  
IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-  
sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property  
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved.  
©2016 Integrated Device Technology, Inc.  
19  
October 20, 2016  
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