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8P34S1102I

型号：

8P34S1102I

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

16 页

PDF大小：

348 K

下载PDF手册

IDT8P34S1102I

Datasheet

1:2 LVDS Output 1.8V Fanout Buffer

Features

Description

The IDT8P34S1102I is a high-performance differential LVDS fanout

buffer. The device is designed for the fanout of high-frequency, very

low additive phase-noise clock and data signals.

• Two low skew, low additive jitter LVDS output pairs

• One differential clock input pair

• Differential CLK, nCLK pairs can accept the following differential

The IDT8P34S1102I is characterized to operate from a 1.8V power

supply. Guaranteed output-to-output and part-to-part skew

characteristics make the IDT8P34S1102I ideal for those clock

distribution applications demanding well-defined performance and

repeatability. One differential input and two low skew outputs are

available. The integrated bias voltage reference enables easy

interfacing of single-ended signals to the differential device input. The

device is optimized for low power consumption and low additive

phase noise.

input levels: LVDS, CML

• Maximum input clock frequency: 1.2GHz

• Output skew: 3ps (typical)

• Propagation delay: 400ps (maximum)

• Low additive phase jitter, RMS; f_REF= 156.25MHz,

12kHz- 20MHz: 42fs (typical)

• Maximum device current consumption (I_EE): 48mA

• Full 1.8V supply voltage

• Lead-free (RoHS 6), 16-Lead VFQFN packaging

• -40°C to 85°C ambient operating temperature

Block Diagram

Pin Assignment

12 11 10

CLK

nQ0

REF

nCLK

nQ1

nc 14

nc 15

7 nCLK

6 CLK

VDD

GND

V_REF

IDT8P34S1102I

16-lead VFQFN

3mm x 3mm x 0.925mm package body

1.7mm x 1.7mm ePad Size

NL Package

Top View

September 20, 2017

IDT8P34S1102I Datasheet

Pin Description and Pin Characteristic Tables

Note 1.

Table 1. Pin Descriptions

Number

Name

GND

Type

Description

1, 16

Power

Unused

Power

Input

Power supply ground.

Do not connect.

2, 3, 4, 13, 14, 15

V_DD

CLK

Power supply pins.

Pulldown

Non-inverting differential clock/data input.

Pulldown/

Pullup

nCLK

V_REF

Input

Inverting differential clock input.

Bias voltage reference. Provides an input bias voltage for the CLK, nCLK input

pair in AC-coupled applications. Refer to Figures 2B and 2C for applicable

AC-coupled input interfaces.

Output

9, 10

Q0, nQ0

Q1, nQ1

Output

Differential output pair 0. LVDS interface levels.

Differential output pair 1. LVDS interface levels.

11, 12

Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

C_IN

Input Capacitance

R_PULLDOWN

R_PULLUP

Input Pulldown Resistor

Input Pullup Resistor

k

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress

specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or

AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Item

Rating

Supply Voltage, V_DD

Inputs, V_I

4.6V

-0.5V to V_DD+ 0.5V

Outputs, I_O

Continuous Current

Surge Current

10mA

15mA

Input Sink/Source, I_REF

±2mA

Maximum Junction Temperature, T_J,MAX

Storage Temperature, T_STG

125°C

-65°C to 150°C

2000V

ESD - Human Body Model^{Note 1.}

ESD - Charged Device Model^{Note 1.}

1500V

According to JEDEC JS-001-2012/JESD22-C101E.

September 20, 2017

IDT8P34S1102I Datasheet

DC Electrical Characteristics

Table 3A. Power Supply DC Characteristics, V = 1.8V ± 5%, T = -40°C to 85°C

Symbol Parameter

V_DDPower Supply Voltage

Test Conditions

Minimum

Typical

Maximum

Units

1.71

1.8

1.89

I_DD

Power Supply Current

Q0 to Q1 terminated 100 between nQx, Qx

Table 3B. Differential Input Characteristics, V = 1.8V ± 5%, T = -40°C to 85°C

Symbol Parameter

I_IHInput High Current

Test Conditions

Minimum

Typical

Maximum

Units

CLK, nCLK

CLK

V_IN= V_DD= 1.89V

_IN= 0V, V_DD= 1.89V

150

µA

-10

µA

I_IL

Input Low Current

nCLK

-150

Reference Voltage for Input

Bias^{Note 1.}

V_REF

V_PP

I_REF= +100µA, V_DD= 1.8V

V_DD= 1.89V

0.9

0.2

0.9

1.30

1.0

Peak-to-Peak Voltage^Note3.

Common Mode Input Voltage^{Note 2.}

V_CMR

V_DD– (V_PP/2)

Note 3.

V_REFspecification is applicable to the AC-coupled input interfaces shown in Figures 2B and 2C.

Common mode input voltage is defined as crosspoint voltage.

V_ILshould not be less than -0.3V and V_IHshould not be higher than V_DD

Note 1.

Table 3C. LVDS DC Characteristics, V = 1.8V ± 5%, T = -40°C to 85°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V_OD

V_OD

V_OS

Differential Output Voltage

outputs loaded with 100 

247

454

V_ODMagnitude Change

Offset Voltage

1.40

1.0

V_OS

V_OSMagnitude Change

Output drive current must be sufficient to drive up to 30cm of PCB trace (assume nominal 50 impedance)

September 20, 2017

IDT8P34S1102I Datasheet

AC Electrical Characteristics

Note 1.

Table 4. AC Electrical Characteristics, V = 1.8V ± 5%, T = -40°C to 85°

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum Units

f_REF

Input Frequency CLK, nCLK

1.2

GHz

V/ns

V/t

t_PD

Input Edge Rate CLK, nCLK

Propagation Delay^{Note 2. Note 3.}

Output Skew^{Note 4. Note 5.}

Pulse Skew

1.5

CLK, nCLK to any Qx, nQx

150

400

tsk(o)

tsk(p)

f_REF= 100MHz

tsk(pp) Part-to-Part Skew^{Note 6.}

250

f_REF= 122.88MHz Square Wave, V_PP= 1V,

Integration Range: 1kHz – 40MHz

f_REF= 122.88MHz Square Wave, V_PP= 1V,

Integration Range: 10kHz – 20MHz

f_REF= 122.88MHz Square Wave, V_PP= 1V,

Integration Range: 12kHz – 20MHz

f_REF= 156.25MHz Square Wave, V_PP= 1V,

Integration Range: 1kHz – 40MHz

Buffer Additive Phase Jitter,

f_REF= 156.25MHz Square Wave, V_PP= 1V,

Integration Range: 10kHz – 20MHz

t_JIT

RMS; refer to Additive Phase

Jitter Section

f_REF= 156.25MHz Square Wave, V_PP= 1V,

Integration Range: 12kHz – 20MHz

f_REF= 156.25MHz Square Wave, V_PP= 0.5V,

Integration Range: 1kHz – 40MHz

100

f_REF= 156.25MHz Square Wave, V_PP= 0.5V,

Integration Range: 10kHz – 20MHz

_REF= 156.25MHz Square Wave, V_PP= 0.5V,

Integration Range: 12kHz – 20MHz

10% to 90%,

outputs loaded with 100

200

115

400

260

t_R/ t_F

Output Rise/ Fall Time

20% to 80%,

outputs loaded with 100

Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equi-

librium has been reached under these conditions.

Measured from the differential input crossing point to the differential output crossing point.

Input V_PPis 0.4V.

Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.

This parameter is defined in accordance with JEDEC Standard 65.

Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and

with equal load conditions. Using the same type of input on each device, the outputs are measured at the differential cross points.

September 20, 2017

IDT8P34S1102I Datasheet

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value of

the fundamental. This ratio is expressed in decibels (dBm) or a ratio

of the power in the 1Hz band to the power in the fundamental. When

the required offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the entire

time record of the signal. It is mathematically possible to calculate an

expected bit error rate given a phase noise plot.

Additive Phase Jitter @ 50fs (typical)

Offset from Carrier Frequency (Hz)

As with most timing specifications, phase noise measurements have

issues relating to the limitations of the measurement equipment. The

noise floor of the equipment can be higher or lower than the noise

floor of the device. Additive phase noise is dependent on both the

noise floor of the input source and measurement equipment.

Measured using a Wenzel Oscillator as the input source.