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SZESD8351P2

型号：

SZESD8351P2

品牌：

ONSEMI[ ONSEMI ]

页数：

8 页

PDF大小：

282 K

下载PDF手册
ESD8351P2, SZESD8351P2  
ESD Protection Diodes  
Low Capacitance ESD Protection Diode  
for High Speed Data Line  
The ESD8351P2 ESD protection diode is designed to protect high  
speed data lines from ESD. Ultra−low capacitance and low ESD  
clamping voltage make this device an ideal solution for protecting  
voltage sensitive high speed data lines.  
www.onsemi.com  
MARKING  
DIAGRAM  
Features  
• Low Capacitance (0.55 pF Max, I/O to GND)  
SOD−923  
CASE 514AB  
AC M  
• Protection for the Following IEC Standards:  
IEC 61000−4−2 (Level 4)  
ISO 10605  
AC  
M
= Specific Device Code  
= Date Code  
• Low ESD Clamping Voltage  
• SZ Prefix for Automotive and Other Applications Requiring Unique  
Site and Control Change Requirements; AEC−Q101 Qualified and  
PPAP Capable  
X2DFN2  
CASE 714AB  
(In Development)  
XX M  
G
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS  
Compliant  
XX = Specific Device Code  
Typical Applications  
• USB 2.0  
M
= Date Code  
G
= Pb−Free Package  
• eSATA  
PIN CONFIGURATION  
AND SCHEMATIC  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
J
Rating  
Symbol  
Value  
−55 to +125  
−55 to +150  
260  
Unit  
°C  
Operating Junction Temperature Range  
Storage Temperature Range  
T
J
1
2
T
stg  
°C  
Cathode  
Anode  
Lead Solder Temperature −  
Maximum (10 Seconds)  
T
L
°C  
IEC 61000−4−2 Contact (ESD)  
IEC 61000−4−2 Air (ESD)  
ISO 10605 330 pF / 2 kW Contact  
ESD  
ESD  
ESD  
15  
15  
30  
kV  
kV  
kV  
=
Maximum Peak Pulse Current  
I
pp  
5.0  
A
8/20 ms @ T = 25°C  
A
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
See Application Note AND8308/D for further description of  
survivability specs.  
This document contains information on some products that are still under development.  
ON Semiconductor reserves the right to change or discontinue these products without  
notice.  
© Semiconductor Components Industries, LLC, 2017  
1
Publication Order Number:  
April, 2017 − Rev. 3  
ESD8351P2/D  
ESD8351P2, SZESD8351P2  
ELECTRICAL CHARACTERISTICS  
I
(T = 25°C unless otherwise noted)  
A
I
PP  
Symbol  
Parameter  
Working Peak Voltage  
R
V
RWM  
DYN  
I
R
Maximum Reverse Leakage Current @ V  
RWM  
V
V
BR  
V
BR  
Breakdown Voltage @ I  
V
V
V
RWM HOLD  
C
T
I
I
V
R
T
C
I
T
Test Current  
I
V
Holding Reverse Voltage  
Holding Reverse Current  
Dynamic Resistance  
Maximum Peak Pulse Current  
HOLD  
HOLD  
HOLD  
I
R
DYN  
R
DYN  
−I  
PP  
I
PP  
V
C
= V  
+ (I * R  
)
HOLD  
PP  
DYN  
V
C
Clamping Voltage @ I  
PP  
V
C
= V  
+ (I * R  
)
HOLD  
PP  
DYN  
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)  
A
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
Reverse Working Voltage  
V
RWM  
I/O Pin to GND  
ESD8351P2T5G  
ESD8351N2T5G  
3.3  
3.7  
V
Breakdown Voltage  
V
BR  
I = 1 mA, I/O Pin to GND  
T
5.5  
7.0  
7.8  
V
Reverse Leakage Current  
I
R
V
RWM  
V
RWM  
= 3.3 V, I/O Pin to GND  
= 3.7 V, I/O Pin to GND  
ESD8351P2T5G  
ESD8351N2T5G  
500  
1.0  
nA  
mA  
Holding Reverse Voltage  
Holding Reverse Current  
V
I/O Pin to GND  
I/O Pin to GND  
1.15  
20  
V
mA  
V
HOLD  
I
HOLD  
Clamping Voltage  
TLP (Note 2)  
See Figures 1 through 11  
V
C
5.7  
6.5  
10  
I
PP  
= 8 A  
IEC 61000−4−2 Level 2 equivalent  
( 4 kV Contact, 4 kV Air)  
I
PP  
= 16 A  
8.3  
5.7  
IEC 61000−4−2 Level 4 equivalent  
( 8 kV Contact, 15 kV Air)  
Clamping Voltage (Note 3)  
Dynamic Resistance  
V
C
6.5  
V
W
t = 8 x 20 ms  
p
I
PP  
= 5 A  
R
Pin1 to Pin2  
Pin2 to Pin1  
0.44  
0.37  
DYN  
Junction Capacitance  
C
V
R
V
R
= 0 V, f = 1 Mhz  
= 0 V, f = 2.5 Ghz  
0.37  
0.35  
0.55  
0.45  
pF  
J
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
1. For test procedure see Figures 8 and 9 and application note AND8307/D.  
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.  
TLP conditions: Z = 50 W, t = 100 ns, t = 4 ns, averaging window; t = 30 ns to t = 60 ns.  
0
p
r
1
2
3. Non−repetitive current pulse at T = 20°C, per IEC 61000−4−5 waveform.  
A
www.onsemi.com  
2
 
ESD8351P2, SZESD8351P2  
10  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
9
8
7
6
5
4
3
2
0.1  
0
1
0
0
0.5  
1.0  
1.5  
V
2.0  
(V)  
2.5  
3.0  
3.5  
1
1.5  
2
2.5  
3
3.5  
(A)  
4
4.5  
5
5.5  
6
I
Bias  
pk  
Figure 1. CV Characteristics  
Figure 2. Clamping Voltage vs Peak Pulse  
Current ( tp = 8/20 ms)  
2.0  
2
m1  
m2  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0
−2  
−4  
−6  
−8  
−10  
−12  
−14  
0.2  
0
1E7  
1E8  
1E9  
1E10 3E10  
1
2
3
4
5
6
7
8
9
10  
FREQUENCY (Hz)  
FREQUENCY  
Figure 3. RF Insertion Loss  
Figure 4. Capacitance over Frequency  
20  
10  
20  
18  
16  
14  
12  
10  
8
10  
18  
16  
14  
12  
10  
8
8
6
4
8
6
4
6
6
4
2
0
4
2
0
2
0
2
0
0
2
4
6
8
10 12 14 16 18 20  
0
2
4
6
8
10 12 14 16 18 20  
V , VOLTAGE (V)  
C
V , VOLTAGE (V)  
C
Figure 5. Positive TLP I−V Curve  
Figure 6. Negative TLP I−V Curve  
www.onsemi.com  
3
ESD8351P2, SZESD8351P2  
Latch−Up Considerations  
stable operating point of the circuit and the system is  
therefore latch−up free. In the non−latch up free load line  
case, the IV characteristic of the snapback protection device  
ON Semiconductor’s 8000 series of ESD protection  
devices utilize a snap−back, SCR type structure. By using  
this technology, the potential for a latch−up condition was  
taken into account by performing load line analysis of  
common high speed serial interfaces. Example load lines for  
latch−up free applications and applications with the  
potential for latch−up are shown below with a generic IV  
characteristic of a snapback, SCR type structured device  
overlaid on each. In the latch−up free load line case, the IV  
characteristic of the snapback protection device intersects  
intersects the load−line in two points (V  
, I  
OPA OPA  
) and  
(V , I ). Therefore in this case, the potential for  
OPB OPB  
latch−up exists if the system settles at (V  
, I  
) after a  
OPB OPB  
transient. Because of this, ESD8351P2 should not be used  
for HDMI applications – ESD8104 or ESD8040 have been  
designed to be acceptable for HDMI applications without  
latch−up. Please refer to Application Note AND9116/D for  
a more in−depth explanation of latch−up considerations  
using ESD8000 series devices.  
the load−line in one unique point (V , I ). This is the only  
OP OP  
I
I
I
SSMAX  
I
SSMAX  
I
I
OPB  
I
OP  
V
OPA  
V
OP  
V
DD  
V
ESD8351P2 Latch*up free:  
USB 2.0 LS/FS, USB 2.0 HS, USB 3.0 SS,  
DisplayPort  
V
V
V
DD  
OPB  
OPA  
ESD8351P2 Potential Latch*up:  
HDMI 1.4/1.3a TMDS  
Figure 7. Example Load Lines for Latch−up Free Applications and Applications with the Potential for Latch−up  
Table 1. SUMMARY OF SCR REQUIREMENTS FOR LATCH−UP FREE APPLICATIONS  
VBR (min)  
(V)  
IH (min)  
(mA)  
VH (min)  
(V)  
ON Semiconductor ESD8000 Series  
Recommended PN  
Application  
HDMI 1.4/1.3a TMDS  
USB 2.0 LS/FS  
USB 2.0 HS  
3.465  
3.301  
0.482  
2.800  
3.600  
54.78  
1.76  
N/A  
1.0  
1.0  
1.0  
1.0  
1.0  
ESD8104, ESD8040  
ESD8004, ESD8351P2  
ESD8004, ESD8351P2  
USB 3.0 SS  
N/A  
ESD8004, ESD8006, ESD8351P2  
ESD8004, ESD8006, ESD8351P2  
DisplayPort  
25.00  
www.onsemi.com  
4
ESD8351P2, SZESD8351P2  
IEC61000−4−2 Waveform  
IEC 61000−4−2 Spec.  
I
peak  
First Peak  
Current  
(A)  
100%  
90%  
Test Volt-  
age (kV)  
Current at  
30 ns (A)  
Current at  
60 ns (A)  
Level  
1
2
3
4
2
4
6
8
7.5  
15  
4
8
2
4
6
8
I @ 30 ns  
22.5  
30  
12  
16  
I @ 60 ns  
10%  
t
P
= 0.7 ns to 1 ns  
Figure 8. IEC61000−4−2 Spec  
Oscilloscope  
ESD Gun  
TVS  
50 W  
Cable  
50 W  
Figure 9. Diagram of ESD Clamping Voltage Test Setup  
The following is taken from Application Note  
AND8308/D − Interpretation of Datasheet Parameters  
for ESD Devices.  
systems such as cell phones or laptop computers it is not  
clearly defined in the spec how to specify a clamping voltage  
at the device level. ON Semiconductor has developed a way  
to examine the entire voltage waveform across the ESD  
protection diode over the time domain of an ESD pulse in the  
form of an oscilloscope screenshot, which can be found on  
the datasheets for all ESD protection diodes. For more  
information on how ON Semiconductor creates these  
screenshots and how to interpret them please refer to  
AND8307/D.  
ESD Voltage Clamping  
For sensitive circuit elements it is important to limit the  
voltage that an IC will be exposed to during an ESD event  
to as low a voltage as possible. The ESD clamping voltage  
is the voltage drop across the ESD protection diode during  
an ESD event per the IEC61000−4−2 waveform. Since the  
IEC61000−4−2 was written as a pass/fail spec for larger  
www.onsemi.com  
5
ESD8351P2, SZESD8351P2  
50 W Coax  
Cable  
Transmission Line Pulse (TLP) Measurement  
L
Attenuator  
S
Transmission Line Pulse (TLP) provides current versus  
voltage (I−V) curves in which each data point is obtained  
from a 100 ns long rectangular pulse from a charged  
transmission line. A simplified schematic of a typical TLP  
system is shown in Figure 10. TLP I−V curves of ESD  
protection devices accurately demonstrate the product’s  
ESD capability because the 10s of amps current levels and  
under 100 ns time scale match those of an ESD event. This  
is illustrated in Figure 11 where an 8 kV IEC 61000−4−2  
current waveform is compared with TLP current pulses at  
8 A and 16 A. A TLP I−V curve shows the voltage at which  
the device turns on as well as how well the device clamps  
voltage over a range of current levels.  
÷
50 W Coax  
Cable  
I
M
V
M
10 MW  
DUT  
V
C
Oscilloscope  
Figure 10. Simplified Schematic of a Typical TLP  
System  
Figure 11. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms  
ORDERING INFORMATION  
†
Device  
Package  
Shipping  
ESD8351P2T5G,  
SZESD8351P2T5G*  
SOD−923  
(Pb−Free)  
8000 / Tape & Reel  
8000 / Tape & Reel  
ESD8351N2T5G  
(In Development)  
X2DFN2  
(Pb−Free)  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
*SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP  
Capable.  
www.onsemi.com  
6
 
ESD8351P2, SZESD8351P2  
PACKAGE DIMENSIONS  
SOD−923  
CASE 514AB  
ISSUE C  
NOTES:  
−X−  
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.  
D
2. CONTROLLING DIMENSION: MILLIMETERS.  
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.  
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF  
BASE MATERIAL.  
−Y−  
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO-  
TRUSIONS, OR GATE BURRS.  
E
1
2
MILLIMETERS  
DIM MIN NOM MAX  
INCHES  
NOM MAX  
2X b  
MIN  
0.08 X  
Y
A
b
c
0.34  
0.15  
0.07  
0.75  
0.55  
0.95  
0.37  
0.20  
0.12  
0.80  
0.60  
0.40  
0.25  
0.17  
0.85  
0.65  
1.05  
0.013 0.015 0.016  
0.006 0.008 0.010  
0.003 0.005 0.007  
0.030 0.031 0.033  
0.022 0.024 0.026  
0.037 0.039 0.041  
0.007 REF  
TOP VIEW  
D
E
A
H
1.00  
E
L
0.19 REF  
0.10  
L2 0.05  
0.15  
0.002 0.004 0.006  
c
H
SOLDERING FOOTPRINT*  
E
SIDE VIEW  
1.20  
2X  
2X  
0.25  
0.36  
2X  
L
PACKAGE  
OUTLINE  
DIMENSIONS: MILLIMETERS  
2X  
L2  
See Application Note AND8455/D for more mounting details  
BOTTOM VIEW  
*For additional information on our Pb−Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
www.onsemi.com  
7
ESD8351P2, SZESD8351P2  
PACKAGE DIMENSIONS  
X2DFN2 1.0x0.6, 0.65P  
CASE 714AB  
ISSUE O  
NOTES:  
0.10  
C
1. DIMENSIONING AND TOLERANCING PER  
ASME Y14.5M, 1994.  
2. CONTROLLING DIMENSION: MILLIMETERS.  
3. EXPOSED COPPER ALLOWED AS SHOWN.  
A B  
E
D
PIN 1  
INDICATOR  
MILLIMETERS  
DIM MIN  
MAX  
0.40  
0.05  
0.55  
A
A1  
b
0.34  
−−−  
0.45  
0.05  
C
TOP VIEW  
D
E
e
1.00 BSC  
0.60 BSC  
0.65 BSC  
NOTE 3  
A
0.10  
0.10  
C
L
0.20  
0.30  
C
A1  
RECOMMENDED  
SEATING  
PLANE  
C
SIDE VIEW  
SOLDER FOOTPRINT*  
1.20  
2X  
0.60  
e
2X  
0.47  
b
e/2  
M
0.05  
C A B  
PIN 1  
1
DIMENSIONS: MILLIMETERS  
2X  
L
*For additional information on our Pb−Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
M
0.05  
C A B  
BOTTOM VIEW  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent  
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.  
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,  
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or  
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer  
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such  
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This  
literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
N. American Technical Support: 800−282−9855 Toll Free  
USA/Canada  
Europe, Middle East and Africa Technical Support:  
Phone: 421 33 790 2910  
Japan Customer Focus Center  
Phone: 81−3−5817−1050  
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Order Literature: http://www.onsemi.com/orderlit  
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Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada  
Email: orderlit@onsemi.com  
For additional information, please contact your local  
Sales Representative  
ESD8351P2/D  
◊
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