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SZESD7016

型号：

SZESD7016

描述：

低电容ESD保护的USB3.0[ Low Capacitance ESD Protection USB3.0 ]

品牌：

ONSEMI[ ONSEMI ]

页数：

8 页

PDF大小：

437 K

下载PDF手册
ESD7016, SZESD7016  
Low Capacitance ESD  
Protection USB3.0  
The ESD7016 transient voltage suppressor is specifically designed  
to protect USB3.0 interfaces by integrating two Superspeed pairs, D+,  
D−, and Vbus lines into a single protection product. Ultra−low  
capacitance and low ESD clamping voltage make this device an ideal  
solution for protecting voltage sensitive high speed data lines. The  
flow−through style package allows for easy PCB layout and matched  
trace lengths necessary to maintain consistent impedance between  
high speed differential lines.  
http://onsemi.com  
MARKING  
DIAGRAM  
UDFN8  
CASE 517CB  
6M MG  
G
Features  
1
• Low Capacitance (0.15 pF Typical, I/O to GND)  
6M = Specific Device Code  
• Protection for the Following IEC Standards:  
M
G
= Date Code  
= Pb−Free Package  
(Note: Microdot may be in either location)  
IEC 61000−4−2 (Level 4)  
• Low ESD Clamping Voltage  
• SZ Prefix for Automotive and Other Applications Requiring Unique  
Site and Control Change Requirements; AEC−Q101 Qualified and  
PPAP Capable  
• This is a Pb−Free Device  
PIN CONFIGURATION  
AND SCHEMATIC  
I/O 1  
I/O 2  
Typical Applications  
• USB 3.0  
Vbus or Ground  
I/O 3  
N/C  
N/C  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
J
Rating  
Symbol  
Value  
−55 to +125  
−55 to +150  
260  
Unit  
°C  
I/O 4  
Operating Junction Temperature Range  
Storage Temperature Range  
T
J
T
stg  
°C  
I/O 5  
I/O 6  
Lead Solder Temperature −  
T
L
°C  
Maximum (10 Seconds)  
IEC 61000−4−2 Contact (ESD)  
IEC 61000−4−2 Air (ESD)  
ESD  
ESD  
15  
15  
kV  
kV  
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
ORDERING INFORMATION  
Device  
Package  
Shipping  
ESD7016MUTAG  
UDFN8  
(Pb−Free)  
3000 / Tape &  
Reel  
SZESD7016MUTAG  
UDFN8  
(Pb−Free)  
3000 / Tape &  
Reel  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
May, 2013 − Rev. 3  
ESD7016/D  
ESD7016, SZESD7016  
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)  
A
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
V
Reverse Working Voltage  
Breakdown Voltage  
V
RWM  
I/O Pin to GND  
I = 1 mA, I/O Pin to GND  
5.0  
V
BR  
5.5  
V
T
Reverse Leakage Current  
Clamping Voltage (Note 1)  
Clamping Voltage (Note 2)  
I
V
= 5 V, I/O Pin to GND  
1.0  
10  
mA  
V
R
RWM  
V
I
PP  
= 1 A, I/O Pin to GND (8 x 20 ms pulse)  
C
C
C
V
V
IEC61000−4−2, 8 kV Contact  
See Figures 1 and 2  
V
Clamping Voltage  
TLP (Note 3)  
See Figures 6 through 9  
I
PP  
I
PP  
=
=
8 A  
16 A  
14.6  
20.5  
Junction Capacitance  
C
V
V
= 0 V, f = 1 MHz between I/O Pins and GND  
= 0 V, f = 1 MHz between I/O Pins and GND  
0.15  
0.03  
0.20  
pF  
pF  
J
R
Junction Capacitance  
Difference  
DC  
J
R
1. Surge current waveform per Figure 5.  
2. For test procedure see Figures 3 and 4 and application note AND8307/D.  
3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.  
TLP conditions: Z = 50 W, t = 100 ns, t = 4 ns, averaging window; t = 30 ns to t = 60 ns.  
0
p
r
1
2
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
0
−10  
−20  
−30  
−40  
−50  
−60  
−70  
−80  
−90  
−10  
−100  
−20  
−20  
0
20  
40  
60  
TIME (ns)  
80  
100  
120  
140  
0
20  
40  
60  
80  
100  
120 140  
TIME (ns)  
Figure 1. IEC61000−4−2 +8 KV Contact  
Figure 2. IEC61000−4−2 −8 KV Contact  
Clamping Voltage  
Clamping Voltage  
http://onsemi.com  
2
 
ESD7016, SZESD7016  
IEC61000−4−2 Waveform  
IEC 61000−4−2 Spec.  
I
peak  
Test  
Voltage  
(kV)  
First Peak  
Current  
(A)  
100%  
90%  
Current at  
30 ns (A)  
Current at  
60 ns (A)  
Level  
1
2
3
4
2
4
6
8
7.5  
15  
4
8
2
4
6
8
I @ 30 ns  
22.5  
30  
12  
16  
I @ 60 ns  
10%  
t
P
= 0.7 ns to 1 ns  
Figure 3. IEC61000−4−2 Spec  
Oscilloscope  
ESD Gun  
TVS  
50 W  
Cable  
50 W  
Figure 4. Diagram of ESD Clamping Voltage Test Setup  
The following is taken from Application Note  
AND8308/D − Interpretation of Datasheet Parameters  
for ESD Devices.  
systems such as cell phones or laptop computers it is not  
clearly defined in the spec how to specify a clamping voltage  
at the device level. ON Semiconductor has developed a way  
to examine the entire voltage waveform across the ESD  
protection diode over the time domain of an ESD pulse in the  
form of an oscilloscope screenshot, which can be found on  
the datasheets for all ESD protection diodes. For more  
information on how ON Semiconductor creates these  
screenshots and how to interpret them please refer to  
AND8307/D and AND8308/D.  
ESD Voltage Clamping  
For sensitive circuit elements it is important to limit the  
voltage that an IC will be exposed to during an ESD event  
to as low a voltage as possible. The ESD clamping voltage  
is the voltage drop across the ESD protection diode during  
an ESD event per the IEC61000−4−2 waveform. Since the  
IEC61000−4−2 was written as a pass/fail spec for larger  
100  
t
r
PEAK VALUE I  
@ 8 ms  
RSM  
90  
80  
70  
60  
50  
40  
30  
20  
PULSE WIDTH (t ) IS DEFINED  
P
AS THAT POINT WHERE THE  
PEAK CURRENT DECAY = 8 ms  
HALF VALUE I /2 @ 20 ms  
RSM  
t
P
10  
0
0
20  
40  
t, TIME (ms)  
60  
80  
Figure 5. 8 X 20 ms Pulse Waveform  
http://onsemi.com  
3
ESD7016, SZESD7016  
22  
20  
18  
16  
14  
12  
10  
8
−22  
−20  
−18  
−16  
−14  
−12  
−10  
−8  
6
−6  
4
−4  
2
−2  
0
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26  
VOLTAGE (V)  
0
2
4
6
8
10 12 14 16 18 20 22 24 26  
VOLTAGE (V)  
Figure 6. Positive TLP I−V Curve  
Figure 7. Negative TLP I−V Curve  
50 W Coax  
Cable  
Transmission Line Pulse (TLP) Measurement  
L
Attenuator  
S
Transmission Line Pulse (TLP) provides current versus  
voltage (I−V) curves in which each data point is obtained  
from a 100 ns long rectangular pulse from a charged  
transmission line. A simplified schematic of a typical TLP  
system is shown in Figure 8. TLP I−V curves of ESD  
protection devices accurately demonstrate the product’s  
ESD capability because the 10s of amps current levels and  
under 100 ns time scale match those of an ESD event. This  
is illustrated in Figure 9 where an 8 kV IEC 61000−4−2  
current waveform is compared with TLP current pulses at  
8 A and 16 A. A TLP I−V curve shows the voltage at which  
the device turns on as well as how well the device clamps  
voltage over a range of current levels.  
÷
50 W Coax  
Cable  
I
M
V
M
10 MW  
DUT  
V
C
Oscilloscope  
Figure 8. Simplified Schematic of a Typical TLP  
System  
Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms  
http://onsemi.com  
4
 
ESD7016, SZESD7016  
Without ESD7016  
With ESD7016  
Figure 10. USB3.0 Eye Diagram with and without ESD7016, 5 Gb/s  
4
2
ESD7016  
IO−GND  
0
−2  
−4  
−6  
−8  
−10  
1.E+06  
1.E+07  
1.E+08  
1.E+09  
1.E+10  
FREQUENCY (Hz)  
Figure 11. ESD7016 Insertion Loss  
http://onsemi.com  
5
ESD7016, SZESD7016  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
Pin 1 Pin 2 Pin 4 Pin 5  
Pin 7  
Pin 8  
Pinout Option 1:  
USB 3.0 Type A  
Connector  
2 Ground connections between high  
speed pairs to minimize crosstalk.  
StdA_SSTX+  
Vbus  
StdA_SSTX−  
D−  
GND_DRAIN  
D+  
GND  
Pin 3  
GND  
Pin 6  
StdA_SSRX+  
=
GND  
StdA_SSRX−  
I/O  
I/O  
VBUS  
Pin 3 Pin 4 Pin 5  
I/O  
I/O  
I/O  
Pin 7  
I/O  
Pin 8  
Pinout Option 2:  
Pin 1 Pin 2  
USB 3.0 Type A  
Connector  
Single ground connection and Vbus  
protection for fully integrated solution.  
StdA_SSTX+  
Vbus  
StdA_SSTX−  
D−  
Vbus  
GND_DRAIN  
D+  
GND  
Pin 6  
StdA_SSRX+  
=
GND  
StdA_SSRX−  
Figure 12. USB3.0 Type A Connector Layout Diagrams  
http://onsemi.com  
6
ESD7016, SZESD7016  
USB 3.0 Micro B  
Connector  
Vbus  
ESD9X  
D−  
D+  
ID  
GND  
ESD7016  
ID  
N/C  
N/C  
MicB_SSTX−  
MicB_SSTX+  
GND_DRAIN  
MicB_SSRX−  
MicB_SSRX+  
Figure 13. USB3.0 Micro B Connector Layout Diagram  
http://onsemi.com  
7
ESD7016, SZESD7016  
PACKAGE DIMENSIONS  
UDFN8, 3.3x1.0, 0.4P  
CASE 517CB  
ISSUE O  
NOTES:  
L
L
1. DIMENSIONING AND TOLERANCING PER  
ASME Y14.5M, 1994.  
2. CONTROLLING DIMENSION: MILLIMETERS.  
3. DIMENSION b APPLIES TO PLATED  
TERMINAL AND IS MEASURED BETWEEN  
0.15 AND 0.20 MM FROM TERMINAL TIP.  
D
A B  
E
PIN ONE  
REFERENCE  
L1  
DETAIL A  
2X  
0.10  
C
ALTERNATE  
MILLIMETERS  
CONSTRUCTIONS  
DIM MIN  
MAX  
0.55  
0.05  
A
A1  
A3  
b
0.45  
0.00  
0.13 REF  
0.10  
C
2X  
TOP VIEW  
EXPOSED Cu  
MOLD CMPD  
A
0.15  
0.25  
DETAIL B  
(A3)  
0.05  
0.05  
C
D
D2  
E
3.30 BSC  
0.25  
0.45  
1.00 BSC  
DETAIL B  
E2  
e
G2  
L
0.45  
0.55  
C
ALTERNATE  
0.40 BSC  
1.19 BSC  
0.20 0.30  
CONSTRUCTION  
SEATING  
PLANE  
A1  
C
SIDE VIEW  
L1  
L2  
−−−  
0.30  
0.15  
0.40  
8X b  
M
0.10  
0.05  
C A B  
e/2  
e
DETAIL A  
RECOMMENDED  
SOLDERING FOOTPRINT*  
M
NOTE 3  
C
8
1
2X  
0.65  
1.66  
2X  
0.50  
L2  
7X  
L
2X  
D2  
2X  
E2  
G2  
BOTTOM VIEW  
M
M
0.10  
0.05  
C A B  
C
1.20  
7X  
0.40  
8X  
0.25  
0.40  
0.50  
PITCH  
DIMENSION: MILLIMETERS  
*For additional information on our Pb−Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice  
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All  
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights  
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should  
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,  
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal  
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
N. American Technical Support: 800−282−9855 Toll Free  
USA/Canada  
Europe, Middle East and Africa Technical Support:  
Phone: 421 33 790 2910  
Japan Customer Focus Center  
Phone: 81−3−5817−1050  
ON Semiconductor Website: www.onsemi.com  
Order Literature: http://www.onsemi.com/orderlit  
Literature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada  
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada  
Email: orderlit@onsemi.com  
For additional information, please contact your local  
Sales Representative  
ESD7016/D  
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