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8S89831I

型号：

8S89831I

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

21 页

PDF大小：

355 K

下载PDF手册
Differential LVPECL-To-LVPECL/ECL  
Fanout Buffer  
8S89831I  
Data Sheet  
General Description  
Features  
The 8S89831I is a high speed 1-to-4 Differential- to-LVPECL/ECL  
Fanout Buffer. The 8S89831I is optimized for high speed and very  
low output skew, making it suitable for use in demanding applications  
such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre  
Channel. The internally terminated differential input and VREF_AC pin  
allow other differential signal families such as LVDS, LVHSTL and  
CML to be easily interfaced to the input with minimal use of external  
components. The device also has an output enable pin which may be  
useful for system test and debug purposes. The 8S89831I is  
packaged in a small 3mm x 3mm 16-pin VFQFN package which  
makes it ideal for use in space-constrained applications.  
• Four LVPECL/ECL outputs  
• IN, nIN input can accept the following differential input levels:  
LVPECL, LVDS, CML, SSTL  
• 50internal input termination to VT  
• Output frequency: >2.1GHz  
• Output skew: 30ps (maximum)  
• Part-to-part skew: 185ps (maximum)  
• Additive phase jitter, RMS: 0.31ps (typical)  
• Propagation Delay: 570ps (maximum)  
• LVPECL mode operating voltage supply range:  
V
CC = 2.5V 5%, 3.3V 5%, VEE = 0V  
• ECL mode operating voltage supply range:  
CC = 0V, VEE = -3.3V 5%, -2.5V 5%  
V
• -40°C to 85°C ambient operating temperature  
• Available in lead-free (RoHS 6) package  
Block Diagram  
Pin Assignment  
Pullup  
EN  
Q0  
D
Q
16 15 14 13  
nQ0  
1
2
3
Q1  
nQ1  
Q2  
12  
11  
10  
IN  
VT  
Q1  
IN  
VT  
VREF_AC  
nIN  
50Ω  
50Ω  
nQ1  
nQ2  
4
9
nIN  
5
6
7
8
Q2  
VREF_AC  
nQ2  
8S89831I  
16-Lead VFQFN  
Q3  
3mm x 3mm x 0.925mm package body  
nQ3  
K Package  
Top View  
©2016 Integrated Device Technology, Inc  
1
Revision A January 27, 2016  
8S89831I Data Sheet  
Table 1. Pin Descriptions  
Number  
1, 2  
Name  
Type  
Output  
Description  
Q1, nQ1  
Q2, nQ2  
Q3, nQ3  
Differential output pair. LVPECL/ECL interface levels.  
Differential output pair. LVPECL/ECL interface levels.  
Differential output pair. LVPECL/ECL interface levels.  
3, 4  
Output  
Output  
5, 6  
7, 14  
8
Vcc  
Power  
Power supply pins.  
Synchronizing clock enable. When LOW, Qx outputs will go LOW and nQx outputs will  
go HIGH on the next LOW transition at IN input. Input threshold is VCC/2. Includes a  
37kpull-up resistor. Default state is HIGH when left floating. The internal latch is  
clocked on the falling edge of the input signal IN. LVTTL / LVCMOS interface levels.  
EN  
Input  
Pullup  
9
nIN  
VREF_AC  
VT  
Input  
Output  
Input  
Inverting differential LVPECL clock input. RT = 50termination to VT.  
Reference voltage for AC-coupled applications.  
10  
11  
Termination input. IREF_AC (max.) < 2mA.  
Non-inverting LVPECL differential clock input.  
RT = 50termination to VT.  
12  
IN  
Input  
13  
VEE  
Power  
Output  
Negative supply pin.  
15, 16  
Q0, nQ0  
Differential output pair. LVPECL/ECL interface levels.  
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
RPULLUP  
Input Pullup Resistor  
37  
k  
©2016 Integrated Device Technology, Inc  
2
Revision A January 27, 2016  
8S89831I Data Sheet  
Function Tables  
Table 3A. Control Input Function Table  
Input  
EN  
0
Outputs  
Q0:Q3  
Disabled; LOW  
Enabled  
nQ0:nQ3  
Disabled; HIGH  
Enabled  
1
NOTE: After EN switches, the clock outputs are disabled or  
enabled following a falling input clock edge as shown in Figure 1.  
EN  
VCC/2  
tS  
VCC/2  
tH  
nIN  
IN  
VIN  
tPD  
→
←
nQx  
Qx  
VOUT  
Figure 1. EN Timing Diagram  
Table 3B. Truth Table  
Inputs  
Outputs  
IN  
0
nIN  
1
EN  
1
Q0:Q3  
nQ0:nQ3  
0
1
0
1
0
1
1
X
X
0
0 (NOTE 1)  
1(NOTE 1)  
NOTE 1: On the next negative transition of the input signal (IN).  
©2016 Integrated Device Technology, Inc  
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Revision A January 27, 2016  
8S89831I Data Sheet  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.  
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond  
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for  
extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VCC  
Negative Supply Voltage, VEE  
Inputs, VI (LVPECL mode)  
Inputs, VI (ECL mode)  
4.6V (LVPECL mode, VEE = 0V)  
-4.6V (ECL mode, VCC = 0V)  
-0.5V to VCC + 0.5V  
0.5V to VEE – 0.5V  
Outputs, IO  
Continuous Current  
Surge Current  
50mA  
100mA  
Input Current, IN, nIN  
50mA  
VT Current, IVT  
100mA  
VREF_AC Input Sink/Source Current, IREF_AC  
Operating Temperature Range, TA  
Package Thermal Impedance, JA, (Junction-to-Ambient)  
Storage Temperature, TSTG  
2mA  
-40°C to +85°C  
74.7C/W (0 mps)  
-65C to 150C  
DC Electrical Characteristics  
Table 4A. Power Supply DC Characteristics, VCC = 2.5V 5%, 3.3V 5%, TA = -40°C to 85°C  
Symbol Parameter  
VCC Positive Supply Voltage  
IEE Power Supply Current  
Test Conditions  
Minimum  
Typical  
Maximum  
3.465  
45  
Units  
V
2.375  
3.3  
mA  
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 2.5V 5%, 3.3V 5%, TA = -40°C to 85°C  
Symbol  
VIH  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
VCC + 0.3  
0.8  
Units  
V
Input High Voltage  
Input Low Voltage  
Input High Current  
Input Low Current  
2.2  
0
VIL  
V
IIH  
VCC = VIN = 3.465V  
10  
µA  
µA  
IIL  
VCC = 3.465V, VIN = 0V  
-150  
©2016 Integrated Device Technology, Inc  
4
Revision A January 27, 2016  
8S89831I Data Sheet  
Table 4C. Differential DC Characteristics, VCC = 2.5V 5%, 3.3V 5%, TA = -40°C to 85°C  
Symbol  
RIN  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
60  
Units  
Differential Input Resistance  
Input High Voltage  
Input Low Voltage  
(IN, nIN)  
(IN, nIN)  
(IN, nIN)  
IN to VT, nIN to VT  
40  
1.2  
0
50  
VIH  
VCC  
V
VIL  
VIH – 0.15  
1.2  
V
VIN  
Input Voltage Swing  
Differential Input Voltage Swing  
Input Current; NOTE 1  
Bias Voltage  
0.15  
0.3  
V
VDIFF_IN  
IIN  
V
(IN, nIN)  
35  
mA  
V
VREF_AC  
VCC – 1.45  
VCC – 1.37  
VCC – 1.32  
NOTE 1: Guaranteed by design.  
Table 4D. LVPECL DC Characteristics, VCC = 2.5V 5%, 3.3V 5%, TA = -40°C to 85°C  
Symbol  
VOH  
Parameter  
Test Conditions  
Minimum  
VCC – 1.175  
VCC – 2.0  
0.6  
Typical  
Maximum  
VCC – 0.85  
VCC – 1.575  
1.0  
Units  
Output High Voltage; NOTE 1  
Output Low Voltage; NOTE 1  
Output Voltage Swing  
V
V
V
V
VOL  
VOUT  
VDIFF_OUT Differential Output Voltage Swing  
1.2  
2.0  
NOTE 1: Outputs terminated with 50to VCC – 2V.  
©2016 Integrated Device Technology, Inc  
5
Revision A January 27, 2016  
8S89831I Data Sheet  
AC Electrical Characteristics  
Table 5. AC Characteristics, VCC = 0V; VEE = -3.3V 5%, -2.5V 5% or VCC = 2.5V 5%, 3.3V 5%, VEE = 0V,  
TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Output Swing 450mV  
Input Swing: 150mV  
Input Swing: 800mV  
Minimum  
2.1  
Typical  
Maximum  
Units  
GHz  
ps  
fMAX  
Output Frequency  
300  
570  
510  
30  
Propagation Delay; (Differential);  
NOTE 1  
tPD  
255  
ps  
tsk(o)  
Output Skew; NOTE 2, 4  
ps  
tsk(pp)  
Part-to-Part Skew; NOTE 3, 4  
185  
ps  
Buffer Additive Jitter; RMS; refer  
to Additive Phase Jitter Section  
155.52MHz, Integration Range:  
12kHz – 20MHz  
tjit  
0.31  
ps  
ps  
Clock Enable  
EN to IN/nIN  
Setup Time  
tS  
300  
Clock Enable  
EN to IN/nIN  
Hold Time  
tH  
300  
100  
ps  
ps  
tR / tF  
Output Rise/Fall Time  
20% to 80%  
250  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE: All parameters characterized at 1GHz unless otherwise noted.  
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.  
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential  
cross points.  
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using  
the same type of inputs on each device, the outputs are measured at the differential cross points.  
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.  
©2016 Integrated Device Technology, Inc  
6
Revision A January 27, 2016  
8S89831I Data Sheet  
Parameter Measurement Information  
V
CC  
2V  
nIN  
IN  
VIN  
VIH  
Cross Points  
VIL  
SCOPE  
V
Qx  
CC  
V
EE  
nQx  
VEE  
nIN  
IN  
V
,
IN  
-0.375V to -1.465V  
VOUT  
Single-Ended Voltage Swing  
Output Load AC Test Circuit  
nIN  
IN  
V
,
DIFF_IN  
VDIFF_OUT  
Part 1  
nQx  
Differential Voltage Swing = 2 x VIN  
Qx  
Part 2  
nQy  
Differential Input Level  
Qy  
tsk(pp)  
nQx  
Qx  
Part-to-Part Skew  
nQy  
Qy  
Output Skew  
VDIFF_IN, VDIFF_OUT  
VIN, VOUT  
1600mV  
(typical)  
800mV  
(typical)  
nIN  
IN  
nQ0:nQ3  
Single-ended & Differential Input Voltage Swing  
Q0:Q3  
tPD  
Propagation Delay  
©2016 Integrated Device Technology, Inc  
7
Revision A January 27, 2016  
8S89831I Data Sheet  
Parameter Measurement Information, continued  
nIN  
nQ0:nQ3  
80%  
80%  
tR  
IN  
VOUT  
20%  
20%  
EN  
Q0:Q3  
tSET-UP  
tHOLD  
tF  
Setup & Hold Time  
Output Rise/Fall Time  
Application Information  
Recommendations for Unused Output Pins  
Outputs:  
LVPECL Outputs  
All unused LVPECL outputs can be left floating. We recommend that  
there is no trace attached. Both sides of the differential output pair  
should either be left floating or terminated.  
©2016 Integrated Device Technology, Inc  
8
Revision A January 27, 2016  
8S89831I Data Sheet  
3.3V Differential Input with Built-In 50Termination Interface  
The IN /nIN with built-in 50terminations accept LVDS, LVPECL,  
LVHSTL, CML, SSTL and other differential signals. Both signals must  
meet the VIN and VIH input requirements. Figures 2A to 2D show  
interface examples for the IN/nIN input with built-in 50terminations  
driven by the most common driver types. The input interfaces  
suggested here are examples only. If the driver is from another  
vendor, use their termination recommendation. Please consult with  
the vendor of the driver component to confirm the driver termination  
requirements.  
Figure 2A. IN/nIN Input with Built-In 50  
Figure 2B. IN/nIN Input with Built-In 50  
Driven by an LVDS Driver  
Driven by an LVPECL Driver  
3.3V  
3.3V  
Zo = 50Ω  
Zo = 50Ω  
R1  
R2  
25  
25  
IN  
VT  
nIN  
Receiver  
With  
SSTL  
Built-In  
50Ω  
Figure 2C. IN/nIN Input with Built-In 50  
Figure 2D. IN/nIN Input with Built-In 50  
Driven by a CML Driver with Open Collector  
Driven by an SSTL Driver  
©2016 Integrated Device Technology, Inc  
9
Revision A January 27, 2016  
8S89831I Data Sheet  
2.5V LVPECL Input with Built-In 50Termination Interface  
The IN /nIN with built-in 50terminations accept LVDS, LVPECL,  
CML, SSTL and other differential signals. Both signals must meet the  
VIN and VIH input requirements. Figures 3A to 3D show interface  
examples for the IN/nIN with built-in 50termination input driven by  
the most common driver types. The input interfaces suggested here  
are examples only. If the driver is from another vendor, use their  
termination recommendation. Please consult with the vendor of the  
driver component to confirm the driver termination requirements.  
Figure 3A. IN/nIN Input with Built-In 50  
Figure 3B. IN/nIN Input with Built-In 50  
Driven by an LVDS Driver  
Driven by an LVPECL Driver  
2.5V  
2.5V  
Zo = 50Ω  
Zo = 50Ω  
R1  
R2  
25Ω  
25Ω  
IN  
VT  
nIN  
Receiver  
With  
SSTL  
Built-In  
50Ω  
Figure 3C. IN/nIN Input with Built-In 50  
Figure 3D. IN/nIN Input with Built-In 50  
Driven by a CML Driver with Open Collector  
Driven by an SSTL Driver  
©2016 Integrated Device Technology, Inc  
10  
Revision A January 27, 2016  
8S89831I Data Sheet  
Termination for 3.3V LVPECL Outputs  
transmission lines. Matched impedance techniques should be used  
to maximize operating frequency and minimize signal distortion.  
Figures 4A and 4B show two different layouts which are  
recommended only as guidelines. Other suitable clock layouts may  
exist and it would be recommended that the board designers  
simulate to guarantee compatibility across all printed circuit and clock  
component process variations.  
The clock layout topology shown below is a typical termination for  
LVPECL outputs. The two different layouts mentioned are  
recommended only as guidelines.  
The differential outputs are low impedance follower outputs that  
generate ECL/LVPECL compatible outputs. Therefore, terminating  
resistors (DC current path to ground) or current sources must be  
used for functionality. These outputs are designed to drive 50  
3.3V  
R3  
R4  
125  
125  
3.3V  
3.3V  
Z
o = 50  
+
_
Input  
Zo = 50  
R1  
84  
R2  
84  
Figure 4A. 3.3V LVPECL Output Termination  
Figure 4B. 3.3V LVPECL Output Termination  
©2016 Integrated Device Technology, Inc  
11  
Revision A January 27, 2016  
8S89831I Data Sheet  
Termination for 2.5V LVPECL Outputs  
Figure 5A and Figure 5B show examples of termination for 2.5V  
LVPECL driver. These terminations are equivalent to terminating 50  
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground  
level. The R3 in Figure 5B can be eliminated and the termination is  
shown in Figure 5C.  
2.5V  
VCC = 2.5V  
2.5V  
2.5V  
VCC = 2.5V  
50Ω  
R1  
R3  
250Ω  
250Ω  
+
50Ω  
50Ω  
50Ω  
+
–
–
2.5V LVPECL Driver  
R1  
R2  
50Ω  
50Ω  
2.5V LVPECL Driver  
R2  
R4  
62.5Ω  
62.5Ω  
R3  
18Ω  
Figure 5A. 2.5V LVPECL Driver Termination Example  
Figure 5B. 2.5V LVPECL Driver Termination Example  
2.5V  
VCC = 2.5V  
50Ω  
+
50Ω  
–
2.5V LVPECL Driver  
R1  
R2  
50Ω  
50Ω  
Figure 5C. 2.5V LVPECL Driver Termination Example  
©2016 Integrated Device Technology, Inc  
12  
Revision A January 27, 2016  
8S89831I Data Sheet  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 6. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally/  
Electrically Enhance Leadframe Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
SOLDER  
SOLDER  
PIN  
PIN  
EXPOSED HEAT SLUG  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
©2016 Integrated Device Technology, Inc  
13  
Revision A January 27, 2016  
8S89831I Data Sheet  
Schematic Example  
Figure 7 shows a schematic example of the 8S89831I. This  
schematic provides examples of input and output handling. The  
8S89831I input has built-in 50termination resistors. The input can  
directly accept various types of differential signal without AC couple.  
For AC couple termination, the 8S89831I also provides the  
VREF_AC pin for proper offset level after the AC couple. This  
example shows the 8S89831I input driven by a 2.5V LVPECL driver  
with AC couple. The 8S89831I outputs are LVPECL driver. In this  
example, we assume the traces are long transmission line and the  
receiver is high input impedance without built-in matched load. An  
example of 3.3V LVPECL termination is shown in this schematic.  
Additional termination approaches are shown in the LVPECL  
Termination Application Note.  
3.3V  
3.3V  
3.3V  
C2  
R3  
R5  
Zo = 50  
Zo = 50  
133  
133  
0.1u  
-
+
2.5V  
C5  
Zo = 50  
9
4
3
2
1
R4  
82.5  
R6  
82.5  
nIN  
VREF_AC  
VT  
IN  
nQ2  
Q2  
nQ1  
Q1  
10  
11  
12  
Zo = 50  
LVPECL  
C6  
C7  
0.1u  
3.3V  
R1  
100  
R2  
100  
U1  
ICS8S89831i  
3.3V  
R7  
R9  
Zo = 50  
Zo = 50  
133  
133  
3.3V  
-
+
C1  
0.1u  
R8  
82.5  
R10  
82.5  
Figure 7. 8S89831I Application Schematic Example  
©2016 Integrated Device Technology, Inc  
14  
Revision A January 27, 2016  
8S89831I Data Sheet  
Power Considerations  
This section provides information on power dissipation and junction temperature for the 8S89831I.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the 8S89831I is the sum of the core power plus the power dissipation in the load(s).  
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.  
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 45mA = 155.925mW  
Power (outputs)MAX = 32.94mW/Loaded Output pair  
If all outputs are loaded, the total power is 4 * 32.94mW = 131.76mW  
•
Power Dissipation for internal termination RT  
Power (RT)MAX = (VIN_MAX)2 / RT_MIN = (1.2V)2 / 80= 18mW  
Total Power_MAX (3.3V, with all outputs switching) = 155.925mW + 131.76mW + 18mW = 305.685mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 74.7°C/W per Table 6 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.306W * 74.7°C/W = 107.9°C. This is well below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 6. Thermal Resistance JA for 16 Lead VFQFN, Forced Convection  
JA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
74.7°C/W  
65.3°C/W  
58.5°C/W  
©2016 Integrated Device Technology, Inc  
15  
Revision A January 27, 2016  
8S89831I Data Sheet  
3. Calculations and Equations.  
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.  
The LVPECL output driver circuit and termination are shown in Figure 8.  
VCC  
Q1  
VOUT  
RL  
50Ω  
VCC - 2V  
Figure 8. LVPECL Driver Circuit and Termination  
To calculate worst case power dissipation into the load, use the following equations which assume a 50load, and a termination voltage of  
VCC – 2V.  
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.85V  
(VCC_MAX – VOH_MAX) = 0.85V  
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.575V  
(VCC_MAX – VOL_MAX) = 1.575V  
Pd_H is power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =  
[(2V – 0.85V)/50] * 0.85V = 19.55mW  
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =  
[(2V – 1.575V)/50] * 1.575V = 13.39mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.94mW  
©2016 Integrated Device Technology, Inc  
16  
Revision A January 27, 2016  
8S89831I Data Sheet  
Reliability Information  
Table 7. JA vs. Air Flow Table for a 16 Lead VFQFN  
JA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
74.7°C/W  
65.3°C/W  
58.5°C/W  
Transistor Count  
The transistor count for 8S89831I is: 328  
This device is pin and function compatible and a suggested replacement for 889831.  
©2016 Integrated Device Technology, Inc  
17  
Revision A January 27, 2016  
8S89831I Data Sheet  
Package Outline and Package Dimensions  
Package Outline - K Suffix for 16 Lead VFQFN  
Seating Plane  
(Ref.)  
ND& NE  
Even  
(ND-1)x e  
(R ef.)  
A1  
Index Area  
L
A3  
E2  
e
N
N
(Typ.)  
2
If ND & NE  
are Even  
1
Anvil  
Singulation  
or  
Sawn  
Singulation  
2
(NE -1)x e  
(Re f.)  
E2  
2
Top View  
D
b
e
Thermal  
Base  
A
(Ref.)  
ND &NE  
Odd  
D2  
2
0. 08  
C
Chamfer 4x  
0.6 x 0.6 max  
OPTIONAL  
D2  
C
Bottom View w/Type A ID  
Bottom View w/Type C ID  
2
1
2
1
CHAMFER  
RADIUS  
N N-1  
N N-1  
4
4
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:  
1. Type A: Chamfer on the paddle (near pin 1)  
2. Type C: Mouse bite on the paddle (near pin 1)  
Table 8. Package Dimensions  
JEDEC Variation: VEED-2/-4  
All Dimensions in Millimeters  
Symbol  
Minimum  
Maximum  
N
16  
A
0.80  
0
1.00  
0.05  
A1  
A3  
0.25 Ref.  
b
ND & NE  
D & E  
D2 & E2  
e
0.18  
0.30  
4
3.00 Basic  
1.00  
0.30  
1.80  
0.50 Basic  
L
0.50  
Reference Document: JEDEC Publication 95, MO-220  
©2016 Integrated Device Technology, Inc  
18  
Revision A January 27, 2016  
8S89831I Data Sheet  
Ordering Information  
Table 9. Ordering Information  
Part/Order Number  
8S89831AKILF  
8S89831AKILFT  
Marking  
831A  
831A  
Package  
“Lead-Free” 16 Lead VFQFN  
“Lead-Free” 16 Lead VFQFN  
Shipping Packaging  
Tube  
Temperature  
-40C to 85C  
-40C to 85C  
Tape & Reel  
©2016 Integrated Device Technology, Inc  
19  
Revision A January 27, 2016  
8S89831I Data Sheet  
Revision History Sheet  
Rev  
Table  
Page  
Description of Change  
Date  
11  
Deleted Differential Input with Built-in 50Termination Unused Input Handling application  
section. This section does not apply when there is only one input.  
A
4/22/10  
1/27/16  
15  
Power Considerations - in Power Dissipation section, corrected Power (RT) calculation.  
Calculation = 18mW from 98mW. Total Power and Junction Temperature calculations  
have also been updated.  
Removed ICS from part numbers where needed.  
General Description - Deleted ICS chip.  
1
A
T9  
19  
Ordering Information - Deleted quantity in tape in reel. Deleted LF note below table.  
Updated header and footer.  
©2016 Integrated Device Technology, Inc  
20  
Revision A January 27, 2016  
8S89831I Data Sheet  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
www.idt.com/go/support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications  
and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein  
is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,  
or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of  
IDT or their respective third party owners.  
For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary.  
Copyright ©2016 Integrated Device Technology, Inc. All rights reserved.  
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