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8S89296NLGI

型号：

8S89296NLGI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

16 页

PDF大小：

353 K

下载PDF手册
8S89296  
LVDS Programmable Delay Line  
Datasheet  
Description  
Features  
▪ One LVDS level output  
The 8S89296 is a high performance LVDS programmable delay line.  
The delay can vary from 2.2ns to 12.5ns in 10ps steps. The 8S89296  
is characterized to operate from a 2.5V power supply and is  
guaranteed over industrial temperature range.  
▪ One differential clock input pair  
▪ Differential input clock (IN, nIN) can accept the following signaling  
levels: LVPECL, LVDS, CML  
The delay of the device varies in discrete steps based on a control  
word. A 10-bit long control word sets the delay in 10ps increments.  
Also, the input pins IN and nIN default to an equivalent low state  
when left floating. The control register can accept CMOS or TTL  
level signals.  
▪ Maximum frequency: 800MHz  
▪ Programmable Delay Range: 2.2ns to 12.5ns in 10ps steps  
▪ D[10:0] can accept LVPECL, LVCMOS or LVTTL levels  
▪ Full 2.5V supply voltages  
▪ -40°C to 85°C ambient operating temperature  
▪ Available in lead-free (RoHS 6) package  
Block Diagram  
Figure 1: Block Diagram  
IN  
0
1
0
1
0
1
0
1
0
1
nIN  
nEN  
512  
GD  
256  
GD  
128  
GD  
64  
GD  
32  
GD  
GD = Gate Delay  
0
1
0
1
0
1
0
1
0
1
16  
GD  
8
GD  
4
GD  
2
GD  
1
GD  
FTUNE  
D[9:0]  
Q
0
1
LEN  
10-bit  
Latch  
SETMIN  
1
GD  
nQ  
SETMAX  
D[10]  
LEN  
CASCADE  
Latch  
nCASCADE  
VBB  
VCF  
VEF  
Transistor count: 8686  
February 14, 2017  
©2017 Integrated Device Technology, Inc.  
1
8S89296 Datasheet  
Pin Assignments  
Figure 2: Pin Assignments for 5mm x 5mm 32-Lead Package  
32 31 30 29 28 27 26 25  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
D8  
D9  
GND  
D0  
D10  
IN  
VDD  
Q
8S89296  
nQ  
nIN  
VBB  
VEF  
VCF  
VDD  
18 VDD  
17  
F
TUNE  
9
10 11 12 13 14 15 16  
Pin Description and Pin Characteristic Tables  
Table 1: Pin Descriptions  
Number  
Name  
Type[a]  
Description  
1
D8  
Input (PD)  
Parallel data input D8.  
Single-ended LVCMOS, LVTTL, LVPECL interface levels.  
2
3
D9  
Input (PD)  
Input (PD)  
Parallel data input D9.  
Single-ended LVCMOS, LVTTL, LVPECL interface levels.  
D10  
Parallel data input D10.  
Single-ended LVCMOS, LVTTL, LVPECL interface levels.  
4
5
6
IN  
Input (PD)  
Input (PU/ PD)  
Output  
Non-inverting differential input.  
Inverting differential input.  
nIN  
VBB  
Reference voltage output. This pin can be used to re-bias AC-coupled inputs to IN  
and nIN. When used, de-couple to VDD using a 0.01F capacitor. If not used, leave  
floating.  
7
8
VEF  
VCF  
Output  
Input  
Reference voltage output. See Table 4.  
Reference voltage input. The voltage driven on VCF sets the logic transition  
threshold for D[10:0].  
9
GND  
LEN  
Power  
Power supply ground.  
10  
Input (PD)  
D inputs LOAD and HOLD control input. When HIGH, latches the D[10:0] bits. When  
LOW, the D[10:0] latches are transparent. Single-ended LVPECL interface levels.  
See Table 3.  
©2017 Integrated Device Technology, Inc.  
2
February 14, 2017  
8S89296 Datasheet  
Table 1: Pin Descriptions  
Number  
Name  
Type[a]  
Description  
11  
SETMIN  
Input (PD)  
Minimum delay set logic input. When HIGH, D[10:0] registers are reset. When LOW,  
the delay is set by SETMAX or D[10:0]. Default is LOW when left floating.  
Single-ended LVPECL interface levels. See Table 5.  
12  
SETMAX  
Input (PD)  
Maximum delay set logic input. When SETMAX is set HIGH and SETMIN is set  
LOW, D[10:0] = 1111111111. When SETMAX is LOW, the delay is set by SETMIN or  
D[10:0]. Default is LOW when left floating. Single-ended LVPECL interface levels.  
See Table 5.  
13  
14  
15  
16  
VDD  
nCASCADE  
CASCADE  
nEN  
Power  
Output  
Positive supply pin.  
LVDS inverted output.  
LVDS non-inverted output.  
Output  
Input (PD)  
Single-ended control enable pin. When LOW, Q is delayed from IN.  
When HIGH, Q is a differential LOW. Default is LOW when left floating.  
Single-ended LVPECL interface levels. See Table 2.  
17  
FTUNE  
Analog Input  
Fine tune delay control input. By varying the input voltage, it provides an additional  
delay.  
18  
19  
20  
21  
22  
23  
VDD  
VDD  
nQ  
Power  
Power  
Positive supply pin.  
Positive supply pin.  
Output  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
Positive supply pin.  
Q
Output  
VDD  
D0  
Power  
Input (PD)  
Parallel data input D0.  
Single-ended LVCMOS, LVTTL, LVPECL interface levels.  
24  
25  
GND  
D1  
Power  
Power supply ground.  
Input (PD)  
Parallel data input D1.  
Single-ended LVCMOS, LVTTL, LVPECL interface levels.  
26  
27  
D2  
D3  
Input (PD)  
Input (PD)  
Parallel data input D2.  
Single-ended LVCMOS, LVTTL, LVPECL interface levels.  
Parallel data input D3.  
Single-ended LVCMOS, LVTTL, LVPECL interface levels.  
28  
29  
GND  
D4  
Power  
Power supply ground.  
Input (PD)  
Parallel data input D4.  
Single-ended LVCMOS, LVTTL, LVPECL interface levels.  
30  
31  
32  
D5  
D6  
D7  
Input (PD)  
Input (PD)  
Input (PD)  
Parallel data input D5.  
Single-ended LVCMOS, LVTTL, LVPECL interface levels.  
Parallel data input D6.  
Single-ended LVCMOS, LVTTL, LVPECL interface levels.  
Parallel data input D7.  
Single-ended LVCMOS, LVTTL, LVPECL interface levels.  
a. Pull-up (PU) and pull-down (PD) resistors are indicated in parentheses. Pullup and Pulldown refer to internal input resistors. See Table 7,  
Pin Characteristics, for typical values.  
©2017 Integrated Device Technology, Inc.  
3
February 14, 2017  
8S89296 Datasheet  
Figure 3: Propagation Delay vs. FTUNE Voltage Graph  
Ftune Voltage (V)  
Function Tables  
Table 2: Delay Enable  
nEN  
Q, nQ  
IN, nIN delayed  
Q = LOW, nQ = HIGH  
0 (default)  
1
Table 3: Digital Control Latch  
LEN  
Latch Action  
0 (default)  
1
Pass through D[10:0]  
Latched D[10:0]  
Table 4: VCF Connection for D[10:0] Logic Interface  
Input  
VCF Connection  
D[10:0] Logic Interface  
[a]  
VCF  
VCF  
VCF  
VEF  
LVPECL  
LVCMOS  
LVTTL  
No Connect  
1.5V source  
a. Connect VCF (pin 8) to VEF (pin 7).  
©2017 Integrated Device Technology, Inc.  
4
February 14, 2017  
8S89296 Datasheet  
Table 5: Theoretical Delta Delay Values[a]  
Programmable Delay[b] (ps)  
D[9:0] Value  
XXXXXXXXXX  
0000000000  
0000000001  
0000000010  
0000000011  
0000000100  
0000000101  
0000000110  
0000000111  
0000001000  
0000010000  
0000100000  
0001000000  
0010000000  
0100000000  
1000000000  
1111111111  
XXXXXXXXXX  
SETMIN  
SETMAX  
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
0
0 (default)  
10  
20  
30  
40  
50  
60  
70  
80  
160  
320  
640  
1280  
2560  
5120  
10230  
10240  
a. Refer to Table 13, AC Characteristics, for typical step delay values.  
b. Inherent propagation delay not included.  
Propagation delay = inherent propagation delay programmable delay.  
Inherent Propagation delay equals the propagation delay with the programmable delay = 0ps.  
©2017 Integrated Device Technology, Inc.  
5
February 14, 2017  
8S89296 Datasheet  
Absolute Maximum Ratings  
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device.  
Functional operation of the 8S89296 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect  
device reliability.  
Table 6: Absolute Maximum Ratings Table  
Item  
Rating  
Supply voltage, VDD  
Inputs, VI  
4.6V  
-0.5V to VDD 0.5V  
Outputs, IO (LVDS)  
Continuous current  
Surge current  
10mA  
15mA  
Junction temperature, TJ  
Storage temperature, TSTG  
125C  
-65C to 150C  
DC Electrical Characteristics  
Table 7: DC Input Characteristics  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
CIN  
Input capacitance  
2
pF  
k  
k  
RPULLUP  
RPULLDOWN  
Input pull-up resistor  
Input pull-down resistor  
50  
50  
Table 8: Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
2.5  
Maximum  
Units  
VDD  
IDD  
Positive supply voltage  
Power supply current  
2.375  
2.625  
158  
V
No load, maximum VDD  
mA  
Table 9: LVCMOS/LVTTL DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VIH  
VIL  
IIH  
Input high voltage  
Input low voltage  
Input high current  
Input low current  
1.7  
VDD 0.3  
0.7  
V
V
-0.3  
D[10:0] VDD = VIN = 2.625V  
D[10:0] VDD = 2.625V, VIN = 0V  
150  
µA  
µA  
IIL  
-10  
©2017 Integrated Device Technology, Inc.  
6
February 14, 2017  
8S89296 Datasheet  
Table 10: LVPECL Differential DC Characteristics, VDD = 2.5V ± 5%, GND = 0V, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
IIH  
Input high current IN, nIN  
VDD = VIN = 2.625V  
150  
µA  
µA  
µA  
V
IN  
Input low current  
nIN  
VDD = 2.625V, VIN = 0V  
VDD = 2.625V, VIN = 0V  
-10  
-150  
IIL  
VPP  
VCMR  
VBB  
Peak-to-peak voltage  
Common mode range[a]  
Output voltage reference  
Mode connection  
0.15  
1.3  
GND 0.95  
VDD – 1.55  
VDD – 1.55  
VDD  
V
IBB = 150µA  
IEF = 150µA  
VDD – 1.35  
VDD – 1.35  
VDD – 1.15  
VDD – 1.15  
V
VEF  
V
a. Common mode input voltage is defined as VIH.  
Table 11: LVPECL Single-Ended DC Characteristics, VDD = 2.5V ± 5%, GND = 0V, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VIH  
Input  
D[10:0], LEN, nEN,  
VDD – 1.2  
VDD – 0.940  
V
high voltage[a] SETMIN, SETMAX  
VIL  
IIH  
IIL  
Input  
D[10:0], LEN, nEN,  
VDD – 1.870  
VDD – 1.45  
150  
V
low voltage[a] SETMIN, SETMAX  
Input  
high current  
D[10:0], LEN, nEN, VDD = VIN = 2.625V  
SETMIN, SETMAX  
µA  
µA  
Input  
low current  
D[10:0], LEN, nEN, VDD = 2.625V, VIN = 0V  
SETMIN, SETMAX  
-10  
a. To enable LVPECL interface levels on pins D[10:0], pin 7 must be connected to pin 8. See Table 4.  
Table 12: LVDS DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VOD  
Differential output voltage  
VOD magnitude change  
Offset voltage  
350  
650  
50  
mV  
mV  
V
VOD  
VOS  
1.10  
1.30  
50  
VOS  
VOS magnitude change  
mV  
©2017 Integrated Device Technology, Inc.  
7
February 14, 2017  
8S89296 Datasheet  
AC Electrical Characteristics  
Table 13: AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C[a], [b]  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
fOUT  
Output frequency  
Q, nQ output  
IN to Q, nQ  
IN to Q, nQ  
nEN to Q, nQ  
800  
2700  
15000  
3200  
MHz  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
%
Dx = 0  
1700  
9500  
1700  
8000  
2200  
12500  
2400  
tPD  
Propagation delay  
Dx = 1023  
Dx = 0  
tPD_RANGE Programmable propagation range  
tPD_MAX – tPD_MIN  
D0 = HIGH  
D1 = HIGH  
D2 = HIGH  
D3 = HIGH  
D4 = HIGH  
D5 = HIGH  
D6 = HIGH  
D7 = HIGH  
D8 = HIGH  
D9 = HIGH  
D[9:0] = HIGH  
15  
25  
45  
85  
165  
330  
645  
1270  
2540  
5075  
10135  
±10  
-20  
t  
Step Delay  
INL  
tS  
Integral non-linearity[c]  
Setup time  
D to LEN  
D to IN, nIN  
nEN to IN, IN  
LEN to D  
-80  
-35  
-175  
-575  
250  
225  
240  
tH  
Hold time  
IN, nIN to nEN  
nEN to IN, nIN  
SETMAX to LEN  
SETMIN to LEN  
Q, nQ  
tR  
Release time  
tR / tF  
odc  
Output rise/fall time  
Output duty cycle  
20% to 80% at 100MHz  
70  
40  
300  
60  
a. Characterized up to fOUT = 800MHz unless noted otherwise.  
b. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal  
equilibrium has been reached under these conditions.  
c. Deviation from a linear delay (actual Min. to Max.) in the 1024 programmable steps.  
©2017 Integrated Device Technology, Inc.  
8
February 14, 2017  
8S89296 Datasheet  
Applications Information  
Recommendations for Unused Input Pins  
Inputs:  
LVCMOS Control Pins  
All control pins have internal pulldown resistors; additional resistance is not required but can be added for additional protection. A 1kresistor  
can be used.  
Wiring the Differential Input to Accept Single-Ended Levels  
Figure 4 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VDD/2 is generated by the  
bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to  
the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For  
example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for  
when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the  
driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate  
the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most  
50applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker  
LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the  
differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower  
differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL  
cannot be less than -0.3V and VIH cannot be more than VDD 0.3V. Suggest edge rate faster than 1V/ns. Though some of the recommended  
components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet  
specifications are characterized and guaranteed by using a differential signal.  
Figure 4: Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels  
©2017 Integrated Device Technology, Inc.  
9
February 14, 2017  
8S89296 Datasheet  
2.5V LVPECL Clock Input Interface  
The IN/nIN accepts LVPECL, LVDS, CML and other differential signals. Both differential signals must meet the VPP and VCMR input  
requirements. Figure 5 to Figure 9 show interface examples for the IN/nIN input driven by the most common driver types. The input interfaces  
suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor  
of the driver component to confirm the driver termination requirements.  
Figure 5. IN/nIN Input Driven by a CML Driver  
Figure 6. ON/nIN Input Driven by a  
2.5V LVPECL Driver  
2.5V  
2.5V  
2.5V  
2.5V  
2.5V  
2.5V  
R1  
50  
R2  
50  
R3  
125  
R4  
125  
Zo = 50Ω  
Zo = 50Ω  
Zo = 50Ω  
Zo = 50Ω  
IN  
IN  
nIN  
nIN  
LVPECL  
Differential  
Inputs  
LVPECL  
Differential  
Inputs  
CML  
LVPECL  
R1  
84  
R2  
84  
Figure 7. IN/nIN Input Driven by a 2.5V LVDS Driver Figure 8. IN/nIN Input Driven by a  
Built-In Pullup CML Driver  
2.5V  
2.5V  
Zo = 50Ω  
2.5V  
C1  
C2  
2.5V  
Zo = 50Ω  
IN  
R5  
100  
VBB  
nIN  
IN  
Zo = 50Ω  
R1  
100  
LVPECL  
Differential  
Inputs  
LVDS  
R1  
1k  
R2  
1k  
nIN  
Zo = 50Ω  
LVPECL  
Differential  
Inputs  
CML Built-In Pullup  
C3  
0.1µF  
Figure 9. IN/nIN Input Driven by a  
2.5V LVPECL Driver with AC Couple  
2.5V  
2.5V  
C1  
C2  
Zo = 50Ω  
Zo = 50Ω  
2.5V LVPECL  
IN  
VBB  
nIN  
LVPECL  
Differential  
Inputs  
R5  
100 - 200  
R6  
100 - 200  
R1  
50  
R2  
50  
©2017 Integrated Device Technology, Inc.  
10  
February 14, 2017  
8S89296 Datasheet  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the  
Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package,  
as shown in Figure 10. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the  
exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB  
between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts.  
While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder  
joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be  
connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and  
dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or  
testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array  
of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended  
that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking  
inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land.  
Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations  
are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s  
Thermally/ Electrically Enhance Lead-frame Base Package, Amkor Technology.  
Figure 10: P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
SOLDER  
SOLDER  
PIN  
EXPOSED HEAT SLUG  
PIN  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
©2017 Integrated Device Technology, Inc.  
11  
February 14, 2017  
8S89296 Datasheet  
LVDS Driver Termination  
For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90and 132. The actual value should  
be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100parallel  
resistor at the receiver and a 100differential transmission-line environment. In order to avoid any transmission-line reflection issues, the  
components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant  
devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 11 can  
be used with either type of output structure. Figure 12, which can also be used with both output types, is an optional termination with center tap  
capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is  
recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are  
LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output.  
Figure 11: Standard LVDS Termination  
ZO ZT  
LVDS  
Driver  
LVDS  
Receiver  
ZT  
Figure 12: Optional LVDS Termination  
Z
T
T
2
ZO ZT  
LVDS  
LVDS  
Driver  
Receiver  
C
Z
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©2017 Integrated Device Technology, Inc.  
12  
February 14, 2017  
8S89296 Datasheet  
Power Considerations  
This section provides information on power dissipation and junction temperature for the 8S89296.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the 8S89296 is the sum of the core power plus the power dissipated in the load(s).  
The following is the power dissipation for VDD = 2.5V 0.125V = 2.625V, which gives worst case results.  
The maximum current at -40°C is as follows:  
IDD_MAX = 158mA  
▪ Power_MAX = VDD_MAX IDD_MAX = 2.625V 158mA = 415mW  
The maximum current at 85°C is as follows:  
IDD_MAX = 150mA  
Power_MAX = VDD_MAX IDD_MAX = 2.625V 150mA = 394mW  
2. Junction Temperature.  
Junction temperature, TJ, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the  
bond wire and bond pad temperature remains below 125°C.  
The equation for TJ is as follows: Tj = JA Pd_total TA  
TJ = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 39.5°C/W per Table 14 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C 0.394W 39.5°C/W = 100.6°C. This is below the limit of 125°C.  
This calculation is only an example. TJ will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 14: Thermal Resistance JA for 32 Lead VFQFN, Forced Convection  
JA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
39.5°C/W  
34.5°C/W  
31.0°C/W  
©2017 Integrated Device Technology, Inc.  
13  
February 14, 2017  
8S89296 Datasheet  
Package Outline and Package Dimensions  
Figure 13: 32-Lead VFQFN Package  
©2017 Integrated Device Technology, Inc.  
14  
February 14, 2017  
8S89296 Datasheet  
Package Outline and Package Dimensions, continued  
Figure 14: 32-Lead VFQFN Package  
©2017 Integrated Device Technology, Inc.  
15  
February 14, 2017  
8S89296 Datasheet  
Marking Diagram  
1. Line 1 IDT is the part number prefix.  
2. Line 2 is the part number.  
3. Line 3 is the package code.  
4. Line 4:  
# denotes stepping.  
“YWW” is the last digit of the year and week that the part was assembled.  
“$” denotes mark code.  
Ordering Information  
Part/Order Number  
Marking  
Package  
Shipping Packaging  
Temperature  
8S89296NLGI  
8S89296NLGI8  
IDT8S89296NLGI  
IDT8S89296NLGI  
32 Lead VFQFN, lead-free  
32 Lead VFQFN, lead-free  
Tray  
-40C to 85C  
-40C to 85C  
Tape & Reel  
Revision History  
Revision Date  
Description of Change  
February 14, 2017  
Initial datasheet.  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
www.IDT.com/go/support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,  
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same  
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability  
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not  
convey any license under intellectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-  
sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property  
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.  
©2017 Integrated Device Technology, Inc  
16  
February 14, 2017  
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