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8S89202BKILF

型号：

8S89202BKILF

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

23 页

PDF大小：

430 K

下载PDF手册
Low Skew, 2:1 LVPECL MUX with 1:8  
Fanout and Internal Termination  
8S89202  
DATA SHEET  
General Description  
Features  
The 8S89202 is a high speed 1-to-8 Differential-to-LVPECL Clock  
Divider and is part of the high performance clock solutions from IDT.  
The 8S89202 is optimized for high speed and very low output skew,  
making it suitable for use in demanding applications such as SONET,  
1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally  
terminated differential inputs and VREF_AC pins allow other  
differential signal families such as LVPECL, LVDS and CML to be  
easily interfaced to the input with minimal use of external  
components.  
• Three output banks, consisting of eight LVPECL output pairs total  
• INx, nINx inputs can accept the following differential input levels:  
LVPECL, LVDS, CML  
• Selectable output divider values of ÷1, ÷2 and ÷4  
• Maximum output frequency: 1.5GHz  
• Maximum input frequency: 3GHz  
• Bank skew: 6ps (typical)  
• Part-to-part skew: 250ps (maximum)  
• Additive phase jitter, RMS: 0.166ps (typical)  
• Propagation delay: 854ps (typical)  
The device also has a selectable ÷1, ÷2, ÷4 output divider, which can  
allow the part to support multiple output frequencies from the same  
reference clock.  
• Output rise time: 156ps (typical)  
The 8S89202 is packaged in a small 5mm x 5mm 32-pin VFQFN  
package which makes it ideal for use in space-constrained  
applications.  
• Full 2.5V 5% and 3.3V 10% operating supply voltage  
• -40°C to 85°C ambient operating temperature  
• Available in lead-free (RoHS 6) package  
Pin Assignment  
24 23 22 21 20 19 18 17  
25  
16  
QB0  
nQA2  
QA2 26  
15 nQB0  
nQA1 27  
14  
13  
QB1  
28  
29  
QA1  
nQA0  
QA0  
V
nQB1  
12 QB2  
11  
10  
9
nQB2  
30  
V
CC 31  
CC  
nMR  
32  
E N  
1
2
3
4
5
6
7
8
8S89202  
32-Lead VFQFN  
5mm x 5mm x 0.925mm package body  
K Package  
Top View  
8S89202 Rev B 7/1/15  
1
©2015 Integrated Device Technology, Inc.  
8S89202 DATA SHEET  
Block Diagram  
Pullup  
QA0  
DIVSEL_A  
nQA0  
QA1  
÷1  
÷2  
÷4  
÷1  
÷2  
nQA1  
IN  
QA2  
R
=50  
IN  
VT  
nQA2  
R
=50  
IN  
nIN  
QA3  
nQA3  
Pullup  
EN  
Pullup  
nMR  
QB0  
nQB0  
VREF_AC  
÷2  
÷4  
QB1  
nQB1  
QB2  
nQB2  
Pullup  
DIVSEL_B  
÷2  
÷4  
QC  
nQC  
Pullup  
DIVSEL_C  
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
2
Rev B 7/1/15  
8S89202 DATA SHEET  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
1, 20, 21  
VEE  
Power  
Negative supply pins.  
Output divider select pin. Controls output divider settings for Bank A.  
See Table 3 for additional information. LVCMOS/LVTTL interface levels.  
2
DIVSEL_A  
Input  
Pullup  
3
4
5
6
IN  
VT  
Input  
Input  
Non-inverting differential LVPECL clock input. RIN = 50termination to VT.  
Termination center-tap input.  
VREF_AC  
nIN  
Output  
Input  
Reference voltage for AC-coupled applications.  
Inverting differential LVPECL clock input. RIN = 50termination to VT.  
Output divider select pin. Controls output divider settings for Bank B.   
See Table 3 for additional information. LVCMOS/LVTTL interface levels.  
7
8
9
DIVSEL_B  
DIVSEL_C  
EN  
Input  
Input  
Input  
Pullup  
Pullup  
Pullup  
Output divider select pin. Controls output divider settings for Bank C.   
See Table 3 for additional information. LVCMOS/LVTTL interface levels.  
Output enable pin. See Table 3 for additional information.   
LVCMOS/LVTTL interface levels.  
10, 19, 22, 31  
11, 12  
VCC  
Power  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Positive supply pins.  
nQB2, QB2  
nQB1, QB1  
nQB0, QB0  
nQC, QC  
Differential output pair. LVPECL interface levels.  
Differential output pair. LVPECL interface levels.  
Differential output pair. LVPECL interface levels.  
Differential output pair. LVPECL interface levels.  
Differential output pair. LVPECL interface levels.  
Differential output pair. LVPECL interface levels.  
Differential output pair. LVPECL interface levels.  
Differential output pair. LVPECL interface levels.  
13, 14  
15, 16  
17, 18  
23, 24  
nQA3, QA3  
nQA2, QA2  
nQA1, QA1  
nQA0, QA0  
25, 26  
27, 28  
29, 30  
Master Reset. See additional 3 for additional information.   
LVCMOS/LVTTL interface levels.  
32  
nMR  
Input  
Pullup  
NOTE: Pullup refers to internal input resistor. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
pF  
CIN  
Input Capacitance  
2
RPULLUP Input Pullup Resistor  
25  
k  
Rev B 7/1/15  
3
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
8S89202 DATA SHEET  
Function Tables  
Table 3. SEL Function Table  
Output Bank  
A
Output Bank  
B
Output Bank  
C
nMR  
EN  
n/a  
0
DIVSEL_A  
DIVSEL_B  
DIVSEL_C  
0
1
1
1
n/a  
n/a  
0
n/a  
n/a  
0
n/a  
n/a  
0
0
0
0
0
0
0
1
÷1  
÷2  
÷2  
÷4  
÷2  
÷4  
1
1
1
1
1
2
3
4
nIN  
IN  
tRR  
nMR  
VCC/2  
nMR asynchronously resets the outputs  
EN  
® ¬ /MR-Q  
tPD  
nQ  
1 Output  
Q
nQ  
2 Output  
Q
nQ  
4 Output  
Q
Outputs go HIGH simultaneously after 4 complete input clock (IN) periods after nMR is de-asserted  
Figure 1A. Reset with Output Enabled  
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
4
Rev B 7/1/15  
8S89202 DATA SHEET  
Figure 1B. Enabled Timing  
1
2
3
4
nIN  
IN  
VCC/2  
Enabled asserted  
EN  
nQ  
1 Output  
Q
nQ  
2 Output  
Q
nQ  
4 Output  
Q
Outputs go HIGH simultaneously after EN is asserted.  
The number of IN clock cycles after EN is asserted before  
the outputs go HIGH varies from 2 to 6 cycles (4 cycles shown).  
1
2
3
4
nIN  
IN  
EN  
VCC/2  
Enabled de-asserted to disable Q[0:7] outputs  
nQ  
1 Output  
Q
nQ  
2 Output  
Q
Q
4 Output  
nQ  
Outputs go LOW in output sequence after EN is de-asserted.  
The 4, 2 and 1 outputs go LOW in that order.  
The number of IN clock cycles after EN is de-asserted  
varies from 2 to 6 cycles (4 cycles shown).  
Figure 1C. Disabled Timing  
Rev B 7/1/15  
5
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
8S89202 DATA SHEET  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.   
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond   
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for   
extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VCC  
Inputs, VI  
4.6V  
-0.5V to VCC + 0.5V  
Outputs, IO  
Continuous Current  
Surge Current  
50mA  
100mA  
Input Current, IN, nIN  
50mA  
VT Current, IVT  
100mA  
Input Sink/Source, IREF_AC  
Package Thermal Impedance, JA  
Storage Temperature, TSTG  
2mA  
42.7C/W (0 mps)  
-65C to 150C  
DC Electrical Characteristics  
Table 4A. Power Supply DC Characteristics, VCC = 2.5V 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol Parameter  
VCC Positive Supply Voltage  
IEE Power Supply Current  
Test Conditions  
Minimum  
Typical  
2.5  
Maximum  
2.625  
Units  
V
2.375  
117  
131  
mA  
Table 4B. Power Supply DC Characteristics, VCC = 3.3V 10%, VEE = 0V, TA = -40°C to 85°C  
Symbol Parameter  
VCC Positive Supply Voltage  
IEE Power Supply Current  
Test Conditions  
Minimum  
Typical  
3.3  
Maximum  
3.63  
Units  
V
2.97  
125  
139  
mA  
Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V 10% or 2.5V 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol Parameter  
Test Conditions  
CC = 3.3V  
Minimum  
2.2  
Typical  
Maximum  
VCC + 0.3  
VCC + 0.3  
0.8  
Units  
V
V
VIH  
VIL  
Input High Voltage  
VCC = 2.5V  
VCC = 3.3V  
1.7  
V
-0.3  
V
Input Low Voltage  
VCC = 2.5V  
-0.3  
0.7  
V
IIH  
IIL  
Input High Current  
Input Low Current  
VCC = VIN = 3.63V or 2.625V  
VCC = 3.63V or 2.625V, VIN = 0V  
-125  
20  
µA  
uA  
-300  
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
6
Rev B 7/1/15  
8S89202 DATA SHEET  
Table 4D. Differential DC Characteristics, VCC = 3.3V 10% or 2.5V 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol  
RIN  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Input Resistance  
Input High Voltage  
Input Low Voltage  
Input Voltage Swing  
IN, nIN  
IN, nIN  
IN, nIN  
IN to VT, nIN to VT  
50  
V
V
V
V
V
VIH  
0.15  
0
VCC +0.3  
VCC -0.15  
VCC  
VIL  
VIN  
0.15  
0.3  
VDIFF_IN  
VREF_AC  
Differential Input Voltage Swing  
Bias Voltage  
VCC -1.7  
VCC -1.3  
VCC -0.9  
Table 4E. LVPECL DC Characteristics, VCC = 3.3V 10%, VEE = 0V, TA = -40°C to 85°C  
Symbol  
VOH  
Parameter  
Test Conditions  
Minimum  
VCC -1.65  
VCC -2.25  
0.7  
Typical  
VCC -1.0  
VCC -1.8  
0.8  
Maximum  
VCC -0.5  
VCC -1.6  
1.1  
Units  
Output High Voltage; NOTE 1  
Output Low Voltage; NOTE 1  
Output Voltage Swing  
V
V
V
V
VOL  
VOUT  
VDIFF_OUT Differential Output Voltage Swing  
1.4  
1.6  
2.2  
NOTE 1: Outputs terminated with 50to VCC – 2V.  
Table 4F. LVPECL DC Characteristics, VCC = 2.5V 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol  
VOH  
Parameter  
Test Conditions  
Minimum  
VCC -1.35  
VCC -2.00  
0.6  
Typical  
VCC -1.0  
VCC -1.75  
0.8  
Maximum  
VCC -0.70  
VCC -1.50  
1.0  
Units  
Output High Voltage; NOTE 1  
Output Low Voltage; NOTE 1  
Output Voltage Swing  
V
V
V
V
VOL  
VOUT  
VDIFF_OUT Differential Output Voltage Swing  
1.2  
1.6  
2.0  
NOTE 1: Outputs terminated with 50to VCC – 2V.  
Rev B 7/1/15  
7
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
8S89202 DATA SHEET  
AC Electrical Characteristics  
Table 5. AC Characteristics, VCC = 3.3V 10% or 2.5V 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol Parameter  
fOUT Output Frequency  
fIN  
Test Conditions  
Minimum  
Typical  
Maximum  
1.5  
Units  
GHz  
GHz  
ps  
Input Frequency  
3
IN to Qx  
660  
600  
845  
772  
6
1020  
905  
26  
tPD  
Propagation Delay; NOTE 1  
nMR to Qx  
ps  
tsk(b)  
tsk(w)  
tsk(o)  
tsk(pp)  
Bank to Bank Skew; NOTE 2, 3  
Bank to Bank Skew; NOTE 2, 3  
Within-Bank Skew; NOTE 2, 4  
Part-to-Part Skew; NOTE 2, 5  
Same divide setting  
Different divide setting  
Within same fanout bank  
ps  
27  
3
103  
13  
ps  
ps  
250  
ps  
Buffer Additive Phase Jitter, RMS;  
refer to Additive Phase Jitter section  
156.25MHz, Integration Range:  
12kHz to 20MHz  
tjit  
0.166  
156  
0.193  
218  
ps  
ps  
tR / tF  
Output Rise/Fall Time  
20% to 80%  
73  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.  
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.  
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential  
cross points.  
NOTE 4: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.  
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and  
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.  
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
8
Rev B 7/1/15  
8S89202 DATA SHEET  
Additive Phase Jitter  
The spectral purity in a band at a specific offset from the fundamental  
compared to the power of the fundamental is called the dBc Phase  
Noise. This value is normally expressed using a Phase noise plot  
and is most often the specified plot in many applications. Phase noise  
is defined as the ratio of the noise power present in a 1Hz band at a  
specified offset from the fundamental frequency to the power value of  
the fundamental. This ratio is expressed in decibels (dBm) or a ratio  
of the power in the 1Hz band to the power in the fundamental. When  
the required offset is specified, the phase noise is called a dBc value,  
which simply means dBm at a specified offset from the fundamental.  
By investigating jitter in the frequency domain, we get a better  
understanding of its effects on the desired application over the entire  
time record of the signal. It is mathematically possible to calculate an  
expected bit error rate given a phase noise plot.  
Input/Output Additive Phase Jitter, RMS @  
156.25MHz (12kHz to 20MHz) = 166fs typical  
Offset from Carrier Frequency (Hz)  
As with most timing specifications, phase noise measurements have  
issues relating to the limitations of the measurement equipment. The  
noise floor of the equipment can be higher or lower than the noise  
floor of the device. Additive phase noise is dependent on both the  
noise floor of the input source and measurement equipment.  
The additive phase jitter for this device was measured using a Rohde  
& Schwarz SMA100 input source and an Agilent E5052 Phase noise  
analyzer.  
Rev B 7/1/15  
9
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
8S89202 DATA SHEET  
Parameter Measurement Information  
2V  
2V  
SCOPE  
SCOPE  
V
V
CC  
Qx  
Qx  
CC  
nQx  
nQx  
VEE  
VEE  
-0.5V 0.125V  
-1.3V 0.33V  
2.5V Output Load AC Test Circuit  
3.3V Output Load AC Test Circuit  
V
CC  
nIN  
IN  
nIN  
IN  
nQAx,  
nQBx, nQC  
VIN  
VIH  
Cross Points  
VIL  
QAx,  
QBx, QC  
tPD  
V
EE  
Input Levels  
Propagation Delay  
nQAx,  
nQBx, nQC  
80%  
tF  
80%  
tR  
VDIFF_IN, VDIFF_OUT  
VIN, VOUT  
VOUT  
QAx,  
20%  
20%  
QBx, QC  
Differential Voltage Swing = 2 x Single-ended VIN  
Single-Ended & Differential Input Swing  
Output Rise/Fall Time  
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
10  
Rev B 7/1/15  
8S89202 DATA SHEET  
Parameter Measurement Information, continued  
Part 1  
Part 2  
nQx  
nQx  
Qx  
Qx  
nQy  
Qy  
nQy  
Qy  
tsk(pp)  
Within Bank Skew  
Part-to-Part Skew  
nQXx  
QXx  
nQXx  
QXx  
nQXy  
QXy  
nQXy  
QXy  
tsk(ω)  
tsk(b)  
Where X = Bank A, Bank B or Bank C  
Bank to Bank Skew (same divide setting)  
Bank to Bank (different divide settings)  
Rev B 7/1/15  
11  
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
8S89202 DATA SHEET  
Applications Information  
Recommendations for Unused Input and Output Pins  
Inputs:  
Outputs:  
LVCMOS Select Pins  
LVPECL Outputs  
All control pins have internal pullups; additional resistance is not  
required but can be added for additional protection. A 1kresistor  
can be used.  
All unused LVPECL outputs can be left floating. We recommend that  
there is no trace attached. Both sides of the differential output pair  
should either be left floating or terminated.  
2.5V LVPECL Input with Built-In 50Termination Interface  
The IN /nIN with built-in 50terminations accept LVDS, LVPECL,  
CML and other differential signals. Both VOH and VOL must meet the  
VIN and VIH input requirements. Figures 2A to 2D show interface  
examples for the IN/nIN with built-in 50termination input driven by  
the most common driver types. The input interfaces suggested here  
are examples only. If the driver is from another vendor, use their  
termination recommendation. Please consult with the vendor of the  
driver component to confirm the driver termination requirements.  
Figure 2A. IN/nIN Input with Built-In 50  
Figure 2B. IN/nIN Input with Built-In 50  
Driven by an LVDS Driver  
Driven by an LVPECL Driver  
Figure 2C. IN/nIN Input with Built-In 50  
Figure 2D. IN/nIN Input with Built-In 50Driven by a  
CML Driver with Built-In 50Pullup  
Driven by a CML Driver  
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
12  
Rev B 7/1/15  
8S89202 DATA SHEET  
3.3V LVPECL Input with Built-In 50Termination Interface  
The IN /nIN with built-in 50terminations accept LVDS, LVPECL,  
CML and other differential signals. Both VOH and VOL must meet the  
VIN and VIH input requirements. Figures 3A to 3D show interface  
examples for the IN /nIN input with built-in 50terminations driven by  
the most common driver types. The input interfaces suggested here  
are examples only. If the driver is from another vendor, use their  
termination recommendation. Please consult with the vendor of the  
driver component to confirm the driver termination requirements.  
Figure 3A. IN/nIN Input with Built-In 50  
Figure 3B. IN/nIN Input with Built-In 50  
Driven by an LVDS Driver  
Driven by an LVPECL Driver  
3.3V  
3.3V  
3.3V CML with  
Built-In Pullup  
Zo = 50Ω  
Zo = 50Ω  
C1  
C2  
IN  
50Ω  
50Ω  
VT  
nIN  
V_REF_AC  
Receiver with  
Built-In 50Ω  
Figure 3C. IN/nIN Input with Built-In 50  
Figure 3D. IN/nIN Input with Built-In 50  
Driven by a CML Driver with Open Collector  
Driven by a CML Driver with Built-In 50  
Pullup  
Rev B 7/1/15  
13  
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
8S89202 DATA SHEET  
Termination for 2.5V LVPECL Outputs  
Figure 4A and Figure 4B show examples of termination for 2.5V  
LVPECL driver. These terminations are equivalent to terminating 50  
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground  
level. The R3 in Figure 4B can be eliminated and the termination is  
shown in Figure 4C.  
2.5V  
VCC = 2.5V  
2.5V  
2.5V  
VCC = 2.5V  
R1  
R3  
50Ω  
250Ω  
250Ω  
+
50Ω  
50Ω  
+
–
50Ω  
–
2.5V LVPECL Driver  
R1  
R2  
50Ω  
50Ω  
2.5V LVPECL Driver  
R2  
R4  
62.5Ω  
62.5Ω  
R3  
18Ω  
Figure 4A. 2.5V LVPECL Driver Termination Example  
Figure 4B. 2.5V LVPECL Driver Termination Example  
2.5V  
VCC = 2.5V  
50Ω  
+
50Ω  
–
2.5V LVPECL Driver  
R1  
R2  
50Ω  
50Ω  
Figure 4C. 2.5V LVPECL Driver Termination Example  
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
14  
Rev B 7/1/15  
8S89202 DATA SHEET  
Termination for 3.3V LVPECL Outputs  
The clock layout topology shown below is a typical termination for  
LVPECL outputs. The two different layouts mentioned are  
recommended only as guidelines.  
transmission lines. Matched impedance techniques should be used  
to maximize operating frequency and minimize signal distortion.  
Figures 5A and 5B show two different layouts which are  
recommended only as guidelines. Other suitable clock layouts may  
exist and it would be recommended that the board designers  
simulate to guarantee compatibility across all printed circuit and clock  
component process variations.  
The differential output is a low impedance follower output that  
generate ECL/LVPECL compatible outputs. Therefore, terminating  
resistors (DC current path to ground) or current sources must be  
used for functionality. These outputs are designed to drive 50  
3.3V  
R3  
R4  
125  
125  
3.3V  
3.3V  
Zo = 50  
+
_
Input  
Zo = 50  
R1  
84  
R2  
84  
Figure 5A. 3.3V LVPECL Output Termination  
Figure 5B. 3.3V LVPECL Output Termination  
Rev B 7/1/15  
15  
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
8S89202 DATA SHEET  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 6. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally/  
Electrically Enhance Leadframe Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
SOLDER  
SOLDER  
PIN  
PIN  
EXPOSED HEAT SLUG  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
16  
Rev B 7/1/15  
8S89202 DATA SHEET  
Power Considerations  
This section provides information on power dissipation and junction temperature for the 8S89202.   
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the 8S89202 is the sum of the core power plus the power dissipated in the load(s).   
The following is the power dissipation for VCC = 3.63V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.  
The maximum current at 85°C is as follows:  
IEE_MAX = 128mA  
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 139mA = 504.57mW  
Power (outputs)MAX = 27.8mW/Loaded Output pair  
If all outputs are loaded, the total power is 8 * 27.8mW = 222.4mW  
•
Power Dissipation for internal termination RT  
Power (RT)MAX = (VIN_MAX)2 / RT_MIN = (1.1V)2 / 80= 15.12mW  
Total Power_MAX = (3.63V, with all outputs switching) = 504.57mW + 222.4mW + 15.12mW = 742.09mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 42.7°C/W per Table 6 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.742W * 42.7°C/W = 116.7°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on input swing, the number of loaded outputs, supply voltage, air flow and  
the type of board (multi-layer).  
Table 6. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection  
JA vs. Air Flow  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
42.7°C/W  
37.3°C/W  
33.5°C/W  
Rev B 7/1/15  
17  
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
8S89202 DATA SHEET  
3. Calculations and Equations.  
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.  
LVPECL output driver circuit and termination are shown in Figure 7.  
VCC  
Q1  
VOUT  
RL  
VCC - 2V  
Figure 7. LVPECL Driver Circuit and Termination  
To calculate worst case power dissipation into the load, use the following equations which assume a 50load, and a termination voltage of  
VCC – 2V.  
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.5V  
(VCC_MAX – VOH_MAX) = 0.5V  
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.6V  
(VCC_MAX – VOL_MAX) = 1.6V  
Pd_H is power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
Pd_H = [(VOH_MAX– (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =  
[(2V – 0.5V)/50] * 0.5V = 15mW  
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCO_MAX – VOL_MAX) =  
[(2V – 1.6V)/50] * 1.6V = 12.8mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 27.8mW  
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
18  
Rev B 7/1/15  
8S89202 DATA SHEET  
Reliability Information  
Table 7. JA vs. Air Flow Table for a 32 Lead VFQFN  
JA vs. Air Flow  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
42.7°C/W  
37.3°C/W  
33.5°C/W  
Transistor Count  
The transistor count for 8S89202: 689  
Rev B 7/1/15  
19  
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
8S89202 DATA SHEET  
32 Lead VFQFN Package Outline and Package Dimensions  
Package Outline - K Suffix for 32 Lead VFQFN  
(Ref.)  
N & N  
Even  
Seating Plane  
(N -1)x e  
(Ref.)  
A1  
IndexArea  
L
A3  
E2  
e
2
N
N
(Ty p.)  
If N & N  
are Even  
Anvil  
1
Singulation  
2
(N -1)x e  
(Re f.)  
E2  
2
TopView  
D
b
e
Thermal  
Base  
A
(Ref.)  
D2  
2
N & N  
Odd  
0. 08  
C
Chamfer 4x  
0.6 x 0.6 max  
OPTIONAL  
D2  
C
Bottom View w/Type A ID  
Bottom View w/Type C ID  
2
1
2
1
CHAMFER  
RADIUS  
N N-1  
N N-1  
4
4
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:  
1. Type A: Chamfer on the paddle (near pin 1)  
2. Type C: Mouse bite on the paddle (near pin 1)  
NOTE: The following package mechanical drawing is a generic  
Table 9. Package Dimensions  
JEDEC Variation: VHHD-2/-4  
All Dimensions in Millimeters  
drawing that applies to any pin count VFQFN package. This drawing  
is not intended to convey the actual pin count or pin layout of this  
device. The pin count and pinout are shown on the front page. The  
package dimensions are in Table 9.  
Symbol  
Minimum  
Nominal  
Maximum  
N
32  
A
0.80  
0
1.00  
0.05  
Reference Document: JEDEC Publication 95, MO-220  
A1  
A3  
0.25 Ref.  
0.25  
b
ND & NE  
D & E  
D2 & E2  
e
0.18  
0.30  
8
5.00 Basic  
3.0  
3.3  
0.50 Basic  
0.40  
L
0.30  
0.50  
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
20  
Rev B 7/1/15  
8S89202 DATA SHEET  
Ordering Information  
Table 8. Ordering Information  
Part/Order Number  
8S89202BKILF  
8S89202BKILFT  
8S89202BKILF/W  
Marking  
Package  
Shipping Packaging  
Tray  
Tape & Reel, pin 1 orientation: EIA-481-C  
Tape & Reel, pin 1 orientation EIA-481-D  
Temperature  
-40C to 85C  
-40C to 85C  
-40C to 85C  
ICS89202BIL  
ICS89202BIL  
ICS89202BIL  
“Lead-Free” 32 Lead VFQFN  
“Lead-Free” 32 Lead VFQFN  
“Lead-Free” 32 Lead VFQFN  
Table 9. Pin 1 Orientation in Tape and Reel Packaging  
Part Number Suffix  
Pin 1 Orientation  
Illustration  
T
Quadrant 1 (EIA-481-C)  
/W  
Quadrant 2 (EIA-481-D)  
Rev B 7/1/15  
21  
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
8S89202 DATA SHEET  
Revision History Sheet  
Rev  
Table  
Page  
Description of Change  
Date  
T9  
8
21  
21  
Added Pin 1 Orientation in Tape and Reel Table.  
Ordering Information - Added W part number.  
B
7/1/15  
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL  
TERMINATION  
22  
Rev B 7/1/15  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
Sales  
Tech Support  
email: clocks@idt.com  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in  
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined  
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether  
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This  
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or  
other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as  
those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any  
circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected  
names, logos and designs, are the property of IDT or their respective third party owners.  
Copyright ©2015 Integrated Device Technology, Inc.. All rights reserved.  
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