请登录

免费注册
全部商品
电子元器件
方案中心
工业品
PDF资料
购物车 0
上传BOM

产品分类

找货询价

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

QQ咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

会员中心
购物车
技术支持

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

售后咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

8S89200

型号：

8S89200

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

20 页

PDF大小：

428 K

下载PDF手册
Low Skew, 2:1 LVDS MUX with 1:8  
Fanout and Internal Termination  
8S89200  
Data Sheet  
General Description  
Features  
The 8S89200 is a high speed 1-to-8 Differential-to-LVDS Clock  
Divider and is part of the high performance clock solutions from IDT.  
The 8S89200 is optimized for high speed and very low output skew,  
making it suitable for use in demanding applications such as SONET,  
1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally  
terminated differential inputs and VREF_AC pins allow other  
differential signal families such as LVPECL, LVDS and CML to be  
easily interfaced to the input with minimal use of external  
components.  
• Three output banks, consisting of eight LVDS output pairs total  
• INx, nINx inputs can accept the following differential input levels:  
LVPECL, LVDS, CML  
• Selectable output divider values of ÷1, ÷2 and ÷4  
• Maximum output frequency: 1.5GHz  
• Maximum input frequency: 3GHz  
• Bank Skew: 10ps (typical)  
• Part-to-part skew: 100ps (typical)  
• Additive phase jitter, RMS: 0.170ps (typical)  
• Propagation delay: 802ps (typical)  
• Output rise time: 150ps (typical)  
• 2.5V 5% operating supply voltage  
• -40°C to 85°C ambient operating temperature  
• Available in lead-free (RoHS 6) package  
The device also has a selectable ÷1, ÷2, ÷4 output divider, which can  
allow the part to support multiple output frequencies from the same  
reference clock.  
The 8S89200 is packaged in a small 5mm x 5mm 32-pin VFQFN  
package which makes it ideal for use in space-constrained  
applications.  
Pin Assignment  
32 31 30 29 28 27 26 25  
1
2
3
4
5
6
7
8
QA3  
nQA3  
VDD  
GND  
24  
23  
22  
DIVSEL_A  
IN  
VT  
GND  
GND  
VDD  
21  
20  
8S89200  
VREF_AC  
nIN  
19  
18  
17  
DIVSEL_B  
DIVSEL_C  
QC  
nQC  
9
10 11 12 13 14 15 16  
32-Lead 5mm x 5mm VFQFN  
©2016 Integrated Device Technology, Inc  
1
Revision B February 8, 2016  
Block Diagram  
Pullup  
QA0  
DIVSEL_A  
nQA0  
QA1  
÷1  
÷2  
÷4  
÷1  
÷2  
nQA1  
IN  
QA2  
R
=50  
=50  
IN  
VT  
nQA2  
R
IN  
nIN  
QA3  
nQA3  
Pullup  
Pullup  
EN  
nMR  
QB0  
nQB0  
VREF_AC  
÷2  
÷4  
QB1  
nQB1  
QB2  
nQB2  
Pullup  
DIVSEL_B  
÷2  
÷4  
QC  
nQC  
Pullup  
DIVSEL_C  
8S89200 Data Sheet  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
1, 20, 21  
GND  
Power  
Input  
Ground supply pins.  
Output divider select pin. Controls output divider settings for Bank A.  
See Table 3 for additional information. LVCMOS/LVTTL interface levels.  
2
DIVSEL_A  
Pullup  
3
4
5
6
Input  
Input  
Non-inverting differential LVPECL clock input. RIN = 50termination to VT.  
Termination center-tap input.  
IN  
VT  
Output  
Input  
Reference voltage for AC-coupled applications.  
VREF_AC  
nIN  
Inverting differential LVPECL clock input. RIN = 50termination to VT.  
Output divider select pin. Controls output divider settings for Bank B.  
See Table 3 for additional information. LVCMOS/LVTTL interface levels.  
7
8
9
Input  
Input  
Input  
Pullup  
Pullup  
Pullup  
DIVSEL_B  
DIVSEL_C  
EN  
Output divider select pin. Controls output divider settings for Bank C.  
See Table 3 for additional information. LVCMOS/LVTTL interface levels.  
Output enable pin. See Table 3 for additional information.  
LVCMOS/LVTTL interface levels.  
10, 19, 22, 31  
11, 12  
VDD  
Power  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Positive supply pins.  
nQB2, QB2  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
13, 14  
nQB1, QB1  
nQB0, QB0  
15, 16  
17, 18  
nQC, QC  
23, 24  
nQA3, QA3  
25, 26  
nQA2, QA2  
nQA1, QA1  
27, 28  
29, 30  
nQA0, QA0  
nMR  
Master Reset. See Table 3 for additional information.  
LVCMOS/LVTTL interface levels.  
32  
Input  
Pullup  
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
pF  
Input Capacitance  
Input Pullup Resistor  
2
RPULLUP  
25  
k  
©2016 Integrated Device Technology, Inc  
3
Revision B February 8, 2016  
8S89200 Data Sheet  
Function Tables  
Table 3. SEL Function Table  
nMR  
EN  
n/a  
0
DIVSEL_A  
DIVSEL_B  
DIVSEL_C  
Output Bank A  
Output Bank B  
Output Bank C  
0
1
1
1
n/a  
n/a  
0
n/a  
n/a  
0
n/a  
n/a  
0
0
0
0
0
0
0
1
÷1  
÷2  
÷2  
÷4  
÷2  
÷4  
1
1
1
1
ꢀ
ꢂ
ꢄ
ꢃ
Q,1  
,1  
W55  
Q05  
9''ꢅꢂ  
Q05ꢁDV\QFKURQRXVO\ꢁUHVHWVꢁWKHꢁRXWSXWV  
(1  
Q4  
¤
W3'ꢅ05ꢈ4  
·ꢀꢁ2XWSXW  
4
Q4  
·ꢂꢁ2XWSXW  
4
Q4  
ꢁ·ꢃꢁ2XWSXW  
4
2XWSXWVꢁJRꢁ+,*+ꢁVLPXOWDQHRXVO\ꢁDIWHUꢁꢃꢁFRPSOHWHꢁLQSXWꢁFORFNꢁꢆ,1ꢇꢁSHULRGVꢁDIWHUꢁQ05ꢁLVꢁGHꢈDVVHUWHG  
Figure 1A. Reset with Output Enabled  
©2016 Integrated Device Technology, Inc  
4
Revision B February 8, 2016  
8S89200 Data Sheet  
1
2
3
4
nIN  
IN  
VDD/2  
Enabled asserted  
EN  
nQ  
÷1 Output  
Q
nQ  
÷2 Output  
Q
nQ  
÷4 Output  
Q
Outputs go HIGH simultaneously after EN is asserted.  
The number of IN clock cycles after EN is asserted before  
the outputs go HIGH varies from 2 to 6 cycles (4 cycles shown).  
Figure 1B. Enabled Timing  
©2016 Integrated Device Technology, Inc  
5
Revision B February 8, 2016  
8S89200 Data Sheet  
1
2
3
4
nIN  
IN  
EN  
VDD/2  
Enabled de-asserted to disable Q[0:7] outputs  
nQ  
÷1 Output  
Q
nQ  
÷2 Output  
Q
Q
÷4 Output  
nQ  
Outputs go LOW in output sequence after EN is de-asserted.  
The ÷4, ÷2 and ÷1 outputs go LOW in that order.  
The number of IN clock cycles after EN is de-asserted  
varies from 2 to 6 cycles (4 cycles shown).  
Figure 1C. Disabled Timing  
©2016 Integrated Device Technology, Inc  
6
Revision B February 8, 2016  
8S89200 Data Sheet  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.  
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond  
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for  
extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VDD  
Inputs, VI  
4.6V  
-0.5V to VDD + 0.5V  
Outputs, IO  
Continuous Current  
Surge Current  
10mA  
15mA  
Input Current, IN, nIN  
50mA  
VT Current, IVT  
100mA  
Input Sink/Source, IREF_AC  
Package Thermal Impedance, JA  
Storage Temperature, TSTG  
2mA  
42.7C/W (0 mps)  
-65C to 150C  
DC Electrical Characteristics  
Table 4A. Power Supply DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C  
Symbol Parameter  
VDD Positive Supply Voltage  
IDD Power Supply Current  
Test Conditions  
Minimum  
Typical  
2.5  
Maximum  
2.625  
Units  
V
2.375  
280  
311  
mA  
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C  
Symbol  
VIH  
Parameter  
Test Conditions  
Minimum  
1.7  
Typical  
Maximum  
VDD + 0.3  
0.7  
Units  
V
Input High Voltage  
Input Low Voltage  
Input High Current  
Input Low Current  
VIL  
-0.3  
V
IIH  
VDD = VIN = 2.625V  
-125  
20  
µA  
uA  
IIL  
VDD = 2.625V, VIN = 0V  
-300  
Table 4C. Differential DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
RIN  
VIH  
VIL  
VIN  
Input Resistance  
IN, nIN  
IN, nIN  
IN, nIN  
IN to VT, nIN to VT  
50  
V
V
V
V
V
Input High Voltage  
Input Low Voltage  
Input Voltage Swing  
0.15  
0
VDD + 0.3  
VDD – 0.15  
1.2  
0.15  
VDIFF_IN Differential Input Voltage Swing  
VREF_AC Bias Voltage  
0.3  
2.4  
VDD – 1.34  
VDD – 1.3  
VDD – 1.18  
©2016 Integrated Device Technology, Inc  
7
Revision B February 8, 2016  
8S89200 Data Sheet  
Table 4D. LVDS DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C  
Symbol Parameter Test Conditions  
Minimum  
Typical  
Maximum  
Units  
mV  
mV  
V
VOD  
Differential Output Voltage  
312  
375  
483  
50  
VOD  
VOS  
VOD Magnitude Change  
Offset Voltage  
1.14  
1.25  
1.40  
50  
VOS  
VOS Magnitude Change  
mV  
AC Electrical Characteristics  
Table 5. AC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C  
Symbol Parameter  
fOUT Output Frequency  
fIN  
Test Conditions  
Minimum  
Typical  
Maximum  
1.5  
Units  
GHz  
GHz  
ps  
Input Frequency  
3
IN to Qx  
650  
500  
802  
725  
10  
80  
935  
965  
55  
tPD  
Propagation Delay; NOTE 1  
nMR to Qx  
ps  
tsk(b)  
tsk(w)  
tsk(o)  
tsk(pp)  
Bank to Bank Skew; NOTE 2, 3  
Bank to Bank Skew; NOTE 2, 3  
Within-Bank Skew; NOTE 2, 4  
Part-to-Part Skew; NOTE 2, 5  
Same divide setting  
Different divide setting  
Within same fanout bank  
ps  
150  
25  
ps  
4
ps  
250  
ps  
Buffer Additive Phase Jitter, RMS;  
refer to Additive Phase Jitter section  
156.25MHz, Integration Range:  
12kHz to 20MHz  
tjit  
0.170  
150  
0.214  
210  
ps  
ps  
tR / tF  
Output Rise/Fall Time  
20% to 80%  
80  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.  
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.  
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential  
cross points.  
NOTE 4: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.  
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and  
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.  
©2016 Integrated Device Technology, Inc  
8
Revision B February 8, 2016  
8S89200 Data Sheet  
Additive Phase Jitter  
The spectral purity in a band at a specific offset from the  
fundamental. When the required offset is specified, the phase noise  
is called a dBc value, which simply means dBm at a specified offset  
from the fundamental. By investigating jitter in the frequency  
domain, we get a better understanding of its effects on the desired  
application over the entire time record of the signal. It is  
mathematically possible to calculate an expected bit error rate given  
a phase noise plot.  
fundamental compared to the power of the fundamental is called the  
dBc Phase Noise. This value is normally expressed using a Phase  
noise plot and is most often the specified plot in many applications.  
Phase noise is defined as the ratio of the noise power present in a  
1Hz band at a specified offset from the fundamental frequency to the  
power value of the fundamental. This ratio is expressed in decibels  
(dBm) or a ratio of the power in the 1Hz band to the power in the  
Offset from Carrier Frequency (Hz)  
As with most timing specifications, phase noise measurements has  
issues relating to the limitations of the equipment. Often the noise  
floor of the equipment is higher than the noise floor of the device.  
This is illustrated above. The device meets the noise floor of what is  
shown, but can actually be lower. The phase noise is dependent on  
the input source and measurement equipment.  
Measured using a Rohde & Schwarz SMA100 as the input source.  
©2016 Integrated Device Technology, Inc  
9
Revision B February 8, 2016  
8S89200 Data Sheet  
Parameter Measurement Information  
V
CC  
nIN  
IN  
V
DD  
VIN  
VIH  
Cross Points  
VIL  
V
EE  
Output Load AC Test Circuit  
Input Levels  
nQAx,  
nQBx, nQC  
nIN  
IN  
80%  
80%  
tR  
VOD  
20%  
nQAx,  
nQBx, nQC  
QAx,  
QBx, QC  
20%  
tF  
QAx,  
QBx, QC  
tPD  
Propagation Delay  
Output Rise/Fall Time  
Offset Voltage Setup  
Differential Output Voltage Setup  
©2016 Integrated Device Technology, Inc  
10  
Revision B February 8, 2016  
8S89200 Data Sheet  
Parameter Measurement Information, continued  
Part 1  
Part 2  
nQx  
Qx  
nQx  
Qx  
nQy  
Qy  
nQy  
Qy  
tsk(pp)  
Within Bank Skew  
Part-to-Part Skew  
nQXx  
QXx  
nQXx  
QXx  
nQXy  
QXy  
nQXy  
QXy  
tsk(b)  
tsk(ω)  
Where X = Bank A, Bank B or Bank C  
Bank to Bank Skew (same divide setting)  
Bank to Bank (different divide settings)  
VDIFF_IN  
VIN  
Differential Voltage Swing = 2 x Single-ended VIN  
Single-Ended & Differential Input Swing  
©2016 Integrated Device Technology, Inc  
11  
Revision B February 8, 2016  
8S89200 Data Sheet  
Applications Information  
2.5V LVPECL Input with Built-In 50Termination Interface  
The IN/nIN with built-in 50terminations accept LVDS, LVPECL,  
CML and other differential signals. Both signals must meet the VIN  
and VIH input requirements. Figures 2A to 2D show interface  
examples for the IN/nIN with built-in 50termination input driven by  
the most common driver types. The input interfaces suggested here  
are examples only. If the driver is from another vendor, use their  
termination recommendation. Please consult with the vendor of the  
driver component to confirm the driver termination requirements.  
Figure 2A. IN/nIN Input with Built-In 50  
Figure 2B. IN/nIN Input with Built-In 50  
Driven by an LVDS Driver  
Driven by an LVPECL Driver  
Figure 2D. IN/nIN Input with Built-In 50Driven by a  
CML Driver with Built-In 50Pullup  
Figure 2C. IN/nIN Input with Built-In 50  
Driven by a CML Driver  
©2016 Integrated Device Technology, Inc  
12  
Revision B February 8, 2016  
8S89200 Data Sheet  
LVDS Driver Termination  
For a general LVDS interface, the recommended value for the  
termination impedance (ZT) is between 90and 132. The actual  
value should be selected to match the differential impedance (Z0) of  
your transmission line. A typical point-to-point LVDS design uses a  
100parallel resistor at the receiver and a 100differential  
transmission-line environment. In order to avoid any  
transmission-line reflection issues, the components should be  
surface mounted and must be placed as close to the receiver as  
possible. IDT offers a full line of LVDS compliant devices with two  
types of output structures: current source and voltage source. The  
standard termination schematic as shown in Figure 3A can be used  
with either type of output structure. Figure 3B, which can also be  
used with both output types, is an optional termination with center  
tap capacitance to help filter common mode noise. The capacitor  
value should be approximately 50pF. If using a non-standard  
termination, it is recommended to contact IDT and confirm if the  
output structure is current source or voltage source type. In addition,  
since these outputs are LVDS compatible, the input receiver’s  
amplitude and common-mode input range should be verified for  
compatibility with the output.  
ZO ZT  
LVDS  
Receiver  
LVDS  
Driver  
ZT  
Figure 3A. Standard Termination  
ZT  
2
ZO ZT  
LVDS  
Driver  
LVDS  
ZT Receiver  
C
2
Figure 3B. Optional Termination  
Recommendations for Unused Input and Output Pins  
Inputs:  
Outputs:  
LVCMOS Select Pins  
LVDS Outputs  
All control pins have internal pullups; additional resistance is not  
required but can be added for additional protection. A 1kresistor  
can be used.  
All unused LVDS output pairs can be either left floating or terminated  
with 100across. If they are left floating, we recommend that there  
is no trace attached.  
©2016 Integrated Device Technology, Inc  
13  
Revision B February 8, 2016  
8S89200 Data Sheet  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 4. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
/Electrically Enhance Leadframe Base Package, Amkor Technology.  
SOLDER  
SOLDER  
PIN  
PIN  
EXPOSED HEAT SLUG  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
©2016 Integrated Device Technology, Inc  
14  
Revision B February 8, 2016  
8S89200 Data Sheet  
Power Considerations  
This section provides information on power dissipation and junction temperature for the 8S89200.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the 8S89200 is the sum of the core power plus the power dissipated in the load(s). The following is the power  
dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.  
The maximum current at 85°C is as follows:  
IDD_MAX = 281mA  
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 2.625V * 311mA = 816.375mW  
Power Dissipation for internal termination RT  
Power (RT)MAX = (VIN_MAX)2 / RT_MIN = (1.2V)2 / 80= 18mW  
Total Power_MAX = (2.625V, with all outputs switching) = 816.375mW + 18mW = 816.393mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 42.7°C/W per Table 6 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.816W * 42.7°C/W = 120°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 6. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection  
JA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
42.7°C/W  
37.3°C/W  
33.5°C/W  
©2016 Integrated Device Technology, Inc  
15  
Revision B February 8, 2016  
8S89200 Data Sheet  
Reliability Information  
Table 7. JA vs. Air Flow Table for a 32 Lead VFQFN  
JA vs. Air Flow  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
42.7°C/W  
37.3°C/W  
33.5°C/W  
Transistor Count  
The transistor count for 8S89200: 689  
©2016 Integrated Device Technology, Inc  
16  
Revision B February 8, 2016  
8S89200 Data Sheet  
32 Lead VFQFN Package Outline and Package Dimensions  
Package Outline - K Suffix for 32 Lead VFQFN  
(Ref.)  
N & N  
Even  
Seating Plane  
(N -1)x e  
(Ref.)  
A1  
IndexArea  
L
A3  
E2  
e
2
N
N
(Ty p.)  
If N & N  
are Even  
Anvil  
1
Singulation  
2
(N -1)x e  
(Re f.)  
E2  
2
TopView  
D
b
e
Thermal  
Base  
A
(Ref.)  
D2  
2
N & N  
Odd  
0. 08  
C
Chamfer 4x  
0.6 x 0.6 max  
OPTIONAL  
D2  
C
Bottom View w/Type A ID  
Bottom View w/Type C ID  
2
1
2
1
CHAMFER  
RADIUS  
N N-1  
N N-1  
4
4
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:  
1. Type A: Chamfer on the paddle (near pin 1)  
2. Type C: Mouse bite on the paddle (near pin 1)  
NOTE: The following package mechanical drawing is a generic  
drawing that applies to any pin count VFQFN package. This drawing  
is not intended to convey the actual pin count or pin layout of this  
device. The pin count and pin-out are shown on the front page. The  
package dimensions are in Table 8.  
Table 8. Package Dimensions  
JEDEC Variation: VHHD-2/-4  
All Dimensions in Millimeters  
Symbol  
Minimum  
Nominal  
Maximum  
N
32  
A
0.80  
0
1.00  
0.05  
A1  
A3  
0.25 Ref.  
0.25  
b
ND & NE  
D & E  
D2 & E2  
e
0.18  
0.30  
8
5.00 Basic  
3.0  
3.3  
0.50 Basic  
0.40  
L
0.30  
0.50  
Reference Document: JEDEC Publication 95, MO-220  
©2016 Integrated Device Technology, Inc  
17  
Revision B February 8, 2016  
8S89200 Data Sheet  
Ordering Information  
Table 9. Ordering Information  
Part/Order Number  
Marking  
Package  
Shipping Packaging  
Tray  
Temperature  
-40C to 85C  
-40C to 85C  
8S89200BKILF  
8S89200BKILFT  
ICS89200BIL  
ICS89200BIL  
32 Lead VFQFN, Lead-Free  
32 Lead VFQFN, Lead-Free  
Tape & Reel  
Tape & Reel Pin 1  
Orientation: EIA-481-D  
8S89200BKILF/W  
ICS89200BIL  
32 Lead VFQFN, Lead-Free  
-40C to 85C  
Table 10. Pin 1 Orientation in Tape and Reel Packaging  
Part Number Suffix  
Pin 1 Orientation  
Illustration  
CARRIER TAPE TOPSIDE  
(Round Sprocket Holes)  
Correct Pin 1 ORIENTATION  
LFT  
Quadrant 1 (EIA-481-C)  
USER DIRECTION OF FEED  
CARRIER TAPE TOPSIDE  
(Round Sprocket Holes)  
Correct Pin 1 ORIENTATION  
LF/W  
Quadrant 2 (EIA-481-D)  
USER DIRECTION OF FEED  
©2016 Integrated Device Technology, Inc  
18  
Revision B February 8, 2016  
8S89200 Data Sheet  
Revision History Sheet  
Rev  
Table  
Page  
Description of Change  
Date  
T9  
T10  
18  
18  
Ordering information Table - added additional row.  
Added Pin 1 Orientation in Tape & Reel Packaging Table.  
Updated header/footer throughout the data sheet.  
B
06/08/2015  
T9  
18  
Ordering Information - removed LF note below table.  
Updated header and footer.  
B
2/8/16  
©2016 Integrated Device Technology, Inc  
19  
Revision B February 8, 2016  
8S89200 Data Sheet  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
www.idt.com/go/support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications  
and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein  
is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,  
or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of  
IDT or their respective third party owners.  
For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary.  
Copyright ©2016 Integrated Device Technology, Inc. All rights reserved.  
厂商 型号 描述 页数 下载

IDT

 		8S89200BKILF [ Low Skew, 2:1 LVDS MUX with 1:8 Fanout and Internal Termination ] 20 页

IDT

 		8S89200BKILFT [ Low Skew, 2:1 LVDS MUX with 1:8 Fanout and Internal Termination ] 20 页

IDT

 		8S89202 [ Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination ] 23 页

IDT

 		8S89202BKILF [ Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination ] 23 页

IDT

 		8S89202BKILFT [ Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination ] 23 页

IDT

 		8S89296 [ LVDS Programmable Delay Line ] 16 页

IDT

 		8S89296NLGI [ LVDS Programmable Delay Line ] 16 页

IDT

 		8S89296NLGI8 [ LVDS Programmable Delay Line ] 16 页

IDT

 		8S89831AKILF [ Differential LVPECL-To-LVPECL/ECL Fanout Buffer ] 21 页

IDT

 		8S89831AKILFT [ Differential LVPECL-To-LVPECL/ECL Fanout Buffer ] 21 页

购物指南

支付方式

配送服务

售后服务

发票须知

优惠券使用规则

特色服务

PCBA制造

国产品牌推荐

国产料号替代

质量保证

技术资料

行业资讯

关于我们

关于达普

联系我们

联系我们

服务热线：400-618-9990

企业邮箱：smail@ic72.com

服务时间：周一至周六 8:30-17:30

达普官方微信号

PDF索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

IC型号索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

Copyright 2024 gkzhan.com Al Rights Reserved 京ICP备06008810号-21 京

深圳网络警察报警平台
公共信息安全网络监察
经营性网站备案信息
不良信息举报中心
工商网监电子标识
全国公安机关备案
0.200059s