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8S89876I

型号：

8S89876I

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

15 页

PDF大小：

335 K

下载PDF手册
Differential-to-LVDS Buffer/Divider  
w /Internal Termination  
8S89876I  
Datasheet  
Description  
Features  
The 8S89876I is a high speed Differential-to-LVDS Buffer/Divider  
w/Internal Termination. The 8S89876I has a selectable ÷1, ÷2, ÷4,  
÷8, ÷16 output divider. The clock input has internal termination  
resistors, allowing it to interface with several differential signal types  
while minimizing the number of required external components.  
• Two LVDS outputs  
• Frequency divide select options: ÷1, ÷2, ÷4, ÷8, ÷16  
• IN, nIN input can accept the following differential input levels:  
LVPECL, LVDS, CML  
• Input Frequency: 2.5GHz (maximum)  
• Additive phase jitter, RMS: 0.07ps (typical)  
• Output skew: 25ps (maximum)  
The device is packaged in a small, 3mm x 3mm VFQFN package,  
making it ideal for use on space-constrained boards.  
• Part-to-part skew: 280ps (maximum)  
• Propagation Delay: 1.1ns (maximum)  
• Full 3.3V supply mode  
• -40°C to 85°C ambient operating temperature  
• Available in lead-free (RoHS 6) package  
• Pin compatible with the obsolete device 889876AK  
Pin Assignment  
Block Diagram  
Pullup  
S2  
16 15 14 13  
1
2
3
Q0  
nQ0  
Q1  
12  
11  
10  
IN  
VT  
nRESET/  
nDISABLE  
Enable  
FF  
Pullup  
VREF_AC  
nIN  
nQ1  
4
9
5
6
7
8
Enable  
MUX  
VREF_AC  
Q0  
nQ0  
MUX  
8S89876I  
IN  
VT  
16-Lead VFQFN  
3mm x 3mm x 0.9mm package body  
Q1  
50Ω  
50Ω  
÷2, ÷4,  
÷8, ÷16  
nQ1  
K Package  
Top View  
nIN  
Pullup  
Pullup  
S1  
S0  
Decoder  
©2018 Integrated Device Technology, Inc  
1
January 11, 2018  
8S89876I Datasheet  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
Differential output pair. Divide by 1, 2, 4, 8, or 16. Unused output pairs must be  
terminated with 100across the differential pair. LVDS interface levels.  
1, 2  
Q0, nQ0  
Output  
Output  
Input  
Differential output pair. Divide by 1, 2, 4, 8, or 16. Unused output pairs must be  
terminated with 100across the differential pair. LVDS interface levels.  
3, 4  
Q1, nQ1  
Select pins. Internal 25kpullup resistor. Logic HIGH if left disconnected (÷16 mode).  
Input threshold is VDD/2. LVCMOS/LVTTL interface levels.  
5, 15, 16  
S2, S1, S0  
Pullup  
Pullup  
6
nc  
Unused  
Power  
No connect.  
7, 14  
VDD  
Power supply pins.  
nRESET/  
nDISABLE  
When LOW, resets the divider (÷2, ÷4, ÷8 or ÷16 mode). When HIGH, outputs are  
active. LVTTL / LVCMOS interface levels.  
8
9
Input  
Input  
nIN  
Inverting differential LVPECL clock input. RT = 50termination to VT.  
Reference voltage for AC-coupled applications. Equal to VDD – 1.35V (approx.).  
Maximum sink/source current is 2mA.  
10  
VREF_AC  
Output  
11  
12  
13  
VT  
IN  
Input  
Input  
Termination center-tap input. Leave pin floating.  
Non-inverting LVPECL differential clock input. RT = 50termination to VT.  
Power supply ground.  
GND  
Power  
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
RPULLUP Input Pullup Resistor  
37.5  
k  
©2018 Integrated Device Technology, Inc  
2
January 11, 2018  
8S89876I Datasheet  
Function Tables  
Table 3A. Control Input Function Table  
Input  
nRESET/nDISABLE  
0
Outputs  
Q0, Q1  
Disabled; LOW  
Enabled  
nQ0, nQ1  
Disabled; HIGH  
Enabled  
1(default)  
V
/2  
DD  
nRESET  
t
RR  
IN  
nIN  
V
Swing  
IN  
t
PD  
nQx  
Qx  
V
Swing  
OUT  
Figure 1. nRESET Timing Diagram  
Table 3B. Truth Table  
Inputs  
Outputs  
nRESET/nDISABLE  
S2  
0
S1  
X
0
S0  
X
0
Q0, nQ0, Q1, nQ1  
1
1
1
1
1
0
Reference Clock (pass through)  
Reference Clock ÷2  
1
1
0
1
Reference Clock ÷4  
1
1
0
Reference Clock ÷8  
1
1
1
Reference Clock ÷16 (default)  
Qx = LOW, nQx = HIGH; Clock disabled  
X
X
X
©2018 Integrated Device Technology, Inc  
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January 11, 2018  
8S89876I Datasheet  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.  
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond  
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for  
extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VDD  
Inputs, VI  
4.6V  
-0.5V to VDD + 0.5V  
(NOTE)  
Outputs, IOUT  
50mA  
100mA  
Continuos Current  
Surge Current  
Input Current, IN, nIN  
±50mA  
VT Current, IVT  
±100mA  
Input Sink/Source, IREF_AC  
± 2mA  
Operating Temperature Range, TA  
Package Thermal Impedance, JA, (Junction-to-Ambient)  
Storage Temperature, TSTG  
-40°C to +85°C  
74.7C/W (0 mps)  
-65C to 150C  
NOTE: IOUT refers to output current supplied by the IDT device only.  
DC Electrical Characteristics  
Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 10%, TA = -40°C to 85°C  
Symbol  
VDD  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
3.63  
Units  
V
Power Supply Voltage  
Power Supply Current  
Differential Input Resistance  
Input High Voltage  
2.97  
3.3  
IDD  
72  
mA  
RIN  
(IN, nIN)  
(IN, nIN)  
(IN, nIN)  
80  
1.2  
0
100  
120  
VIH  
VDD + 0.3  
VDD - 0.15  
1.8  
V
VIL  
Input Low Voltage  
V
VIN  
Input Voltage Swing; NOTE 1  
Differential Input Voltage Swing  
Input Current; NOTE 2  
Bias Voltage  
0.15  
0.3  
V
VDIFF_IN  
IIN  
V
(IN, nIN)  
45  
mA  
V
VREF_AC  
VDD - 1.45  
VDD – 1.35  
VDD - 1.25  
NOTE 1: Refer to Parameter Measurement Information, Input Voltage Swing Diagram  
NOTE 2: Guaranteed by design.  
©2018 Integrated Device Technology, Inc  
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January 11, 2018  
8S89876I Datasheet  
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 10%, TA = -40°C to 85°C  
Symbol  
VIH  
Parameter  
Test Conditions  
Minimum  
2.2  
Typical  
Maximum  
Units  
V
Input High Voltage  
Input Low Voltage  
Input High Current  
Input Low Current  
VDD + 0.3  
0.8  
VIL  
-0.3  
V
IIH  
VDD = VIN = 3.63V  
-125  
20  
µA  
µA  
IIL  
VDD = 3.63V, VIN = 0V  
-300  
Table 4C. LVDS DC Characteristics, VDD = 3.3V ± 10%, TA = -40°C to 85°C  
Symbol  
VOUT  
VOH  
Parameter  
Test Conditions  
Minimum  
247  
Typical  
Maximum  
454  
Units  
mV  
V
Output Voltage Swing  
Output High Voltage  
1.35  
1.85  
VOL  
Output Low Voltage  
1.1  
1.5  
V
VOCM  
VOCM  
Output Common Mode Voltage  
Change in Common Mode Voltage  
1.205  
1.475  
50  
V
mV  
AC Electrical Characteristics  
Table 5. AC Characteristics, VDD = 3.3V ± 10%, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
fIN  
Input Frequency  
2.5  
GHz  
Propagation Delay;  
NOTE 1  
tPD  
IN-to-Q  
0.46  
1.1  
ns  
tsk(o)  
Output Skew; NOTE 2, 3  
25  
ps  
ps  
tsk(pp)  
Part-to-Part Skew; NOTE 3, 4  
280  
Buffer Additive Phase Jitter, RMS;  
refer to Additive Phase Jitter Section  
622.08MHz, Integration Range:  
12kHz - 20MHz  
tjit  
0.07  
150  
ps  
tRR  
Reset Recovery Time  
Output Rise/Fall Time  
600  
40  
ps  
ps  
tR / tF  
250  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device  
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal  
equilibrium has been reached under these conditions.  
All parameters characterized at 1.7GHz unless otherwise noted.  
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.  
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential  
cross points.  
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.  
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency  
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.  
©2018 Integrated Device Technology, Inc  
5
January 11, 2018  
8S89876I Datasheet  
Additive Phase Jitter  
The spectral purity in a band at a specific offset from the  
(dBm) or a ratio of the power in the 1Hz band to the power in the  
fundamental. When the required offset is specified, the phase noise  
is called a dBc value, which simply means dBm at a specified offset  
from the fundamental. By investigating jitter in the frequency domain,  
we get a better understanding of its effects on the desired application  
over the entire time record of the signal. It is mathematically possible  
to calculate an expected bit error rate given a phase noise plot.  
fundamental compared to the power of the fundamental is called the  
dBc Phase Noise. This value is normally expressed using a Phase  
noise plot and is most often the specified plot in many applications.  
Phase noise is defined as the ratio of the noise power present in a  
1Hz band at a specified offset from the fundamental frequency to the  
power value of the fundamental. This ratio is expressed in decibels  
622.08MHz  
RMS Phase Jitter (Random)  
12kHz to 20MHz = 0.07ps (typical)  
Offset from Carrier Frequency (Hz)  
As with most timing specifications, phase noise measurements have  
issues relating to the limitations of the equipment. Often the noise  
floor of the equipment is higher than the noise floor of the device.  
This is illustrated above. The device meets the noise floor of what is  
shown, but can actually be lower. The phase noise is dependent on  
the input source and measurement equipment.  
The source generator “Rohde & Schwarz SMA 100A Signal  
Generator, 91Hz – 6GHz as external input with a balun was used to  
drive the input clock IN, nIN”.  
©2018 Integrated Device Technology, Inc  
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January 11, 2018  
8S89876I Datasheet  
Parameter Measurement Information  
SCOPE  
VDIFF_IN  
VIN, VOUT  
Qx  
V
DD  
3.3V±10%  
POWER SUPPLY  
+
Float GND –  
nQx  
Differential Voltage Swing = 2 x Single-ended VIN  
LVDS Output Load AC Test Circuit  
Single-Ended & Differential Input/Output Voltage Swing  
Part 1  
nQx  
Qx  
nQx  
Qx  
nQy  
Qy  
Part 2  
nQy  
Qy  
tsk(pp)  
Part-to-Part Skew  
Output Skew  
nQ0, nQ1  
nIN  
IN  
80%  
80%  
VOUT  
20%  
20%  
nQ0, nQ1  
Q0, Q1  
tF  
tR  
Q0, Q1  
tPD  
Output Rise/Fall Time  
Propagation Delay  
©2018 Integrated Device Technology, Inc  
7
January 11, 2018  
8S89876I Datasheet  
Parameter Measurement Information, continued  
VDD  
VDD  
out  
➤
out  
out  
➤
DC Input  
LVDS  
LVDS  
DC Input  
100  
VOUT  
out  
➤
VOCM/∆ VOCM  
➤
LVDS Output Common Mode Voltage  
LVDS Output Voltage Swing  
nQx  
Qx  
VOH  
VOUT  
VOL  
LVDS Output Voltage Level  
©2018 Integrated Device Technology, Inc  
8
January 11, 2018  
8S89876I Datasheet  
Applications Information  
3.3V Differential Input with Built-In 50Termination Interface  
The IN /nIN with built-in 50terminations accept LVDS, LVPECL,  
CML, and other differential signals. The differential signal must meet  
the VIN and VIH input requirements. Figures 2A to 2D show interface  
examples for the IN/nIN input with built-in 50terminations driven by  
the most common driver types. The input interfaces suggested here  
are examples only. If the driver is from another vendor, use their  
termination recommendation. Please consult with the vendor of the  
driver component to confirm the driver termination requirements.  
Figure 2A. IN/nIN Input with Built-In 50  
Figure 2B. IN/nIN Input with Built-In 50  
Driven by an LVDS Driver  
Driven by an LVPECL Driver  
3.3V  
3.3V  
3.3V CML with  
Built-In Pullup  
Zo = 50Ω  
Zo = 50Ω  
C1  
C2  
IN  
50Ω  
50Ω  
VT  
nIN  
V_REF_AC  
Receiver with  
Built-In 50Ω  
Figure 2C. IN/nIN Input with Built-In 50  
Figure 2D. IN/nIN Input with Built-In 50Driven by a  
CML Driver with Built-In 50Pullup  
Driven by a CML Driver with Open Collector  
©2018 Integrated Device Technology, Inc  
9
January 11, 2018  
8S89876I Datasheet  
LVDS Driver Termination  
A general LVDS interface is shown in Figure 3. Standard termination  
for LVDS type output structure requires both a 100parallel resistor  
at the receiver and a 100differential transmission line environment.  
In order to avoid any transmission line reflection issues, the 100  
resistor must be placed as close to the receiver as possible. IDT  
offers a full line of LVDS compliant devices with two types of output  
structures: current source and voltage source. The standard  
termination schematic as shown in Figure 3 can be used with either  
type of output structure. If using a non-standard termination, it is  
recommended to contact IDT and confirm if the output is a current  
source or a voltage source type structure. In addition, since these  
outputs are LVDS compatible, the input receivers amplitude and  
common mode input range should be verified for compatibility with  
the output.  
+
LVDS  
Receiver  
–
LVDS Driver  
100Ω  
100Ω Differential Transmission Line  
Figure 3. Typical LVDS Driver Termination  
Recommendations for Unused Input Pins  
Inputs:  
Outputs:  
LVCMOS Select Pins  
LVDS Outputs  
All control pins have internal pullups; additional resistance is not  
required but can be added for additional protection. A 1kresistor  
can be used.  
All unused LVDS output pairs can be either left floating or terminated  
with 100across. If they are left floating, we recommend that there  
is no trace attached.  
©2018 Integrated Device Technology, Inc  
10  
January 11, 2018  
8S89876I Datasheet  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on  
the package, as shown in Figure 4. The solderable area on the PCB,  
as defined by the solder mask, should be at least the same  
size/shape as the exposed pad/slug area on the package to  
maximize the thermal/electrical performance. Sufficient clearance  
should be designed on the PCB between the outer edges of the land  
pattern and the inner edges of pad pattern for the leads to avoid any  
shorts.  
specific and dependent upon the package power dissipation as well  
as electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be  
taken to eliminate any solder voids between the exposed heat slug  
and the land pattern. Note: These recommendations are to be used  
as a guideline only. For further information, please refer to the  
Application Note on the Surface Mount Assembly of Amkor’s  
Thermally/ Electrically Enhance Leadframe Base Package, Amkor  
Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern  
must be connected to ground through these vias. The vias act as  
“heat pipes”. The number of vias (i.e. “heat pipes”) are application  
SOLDER  
PIN  
SOLDER  
EXPOSED HEAT SLUG  
PIN  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
©2018 Integrated Device Technology, Inc  
11  
January 11, 2018  
8S89876I Datasheet  
Power Considerations  
This section provides information on power dissipation and junction temperature for the 8S89876I.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the 8S89876I is the sum of the core power plus the analog power plus the power dissipated in the load(s).  
The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.  
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.63V * 72mA = 261.4mW  
Power Dissipation for internal termination RT  
Power (RT)MAX = (VIN_MAX)2 / RIN_MIN = (1.2V)2 / 80= 18mW  
Total Power_MAX (3.63V, with all outputs switching) = 261.4mW + 18mW + 18mW = 279.4mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 74.7°C/W per Table 6 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.279W * 74.7°C/W = 105.8°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 6. Thermal Resistance JA for 16 Lead VFQFN Forced Convection  
JA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
74.7°C/W  
65.3°C/W  
58.5°C/W  
©2018 Integrated Device Technology, Inc  
12  
January 11, 2018  
8S89876I Datasheet  
Reliability Information  
Table 7. JA vs. Air Flow Table for a 16 Lead VFQFN  
JA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
74.7°C/W  
65.3°C/W  
58.5°C/W  
Transistor Count  
The transistor count for 8S89876I is: 504  
Package Outline Drawings  
The package outline drawings are located at the end of this document. The package information is the most current data available and is  
subject to change without notice or revision of this document.  
Ordering Information  
Table 9. Ordering Information  
Part/Order Number  
8S89876BKILF  
Marking  
876B  
Package  
Shipping Packaging  
Tube  
Temperature  
-40C to 85C  
-40C to 85C  
“Lead-Free” 16 Lead VFQFN  
“Lead-Free” 16 Lead VFQFN  
8S89876BKILFT  
876B  
Tape & Reel  
Revision History  
Revision Date  
Description of Change  
January 11, 2018  
February 9, 2016  
▪ Updated the package outline drawings; however, no mechanical changes  
▪ Removed ICS from part number where needed.  
▪ Ordering Information - removed quantity from tape and reel. Removed LF note below table.  
▪ Updated header and footer.  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
www.idt.com/go/support  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without  
notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed  
in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any  
particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intel-  
lectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of  
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc All rights reserved.  
©2018 Integrated Device Technology, Inc  
13  
January 11, 2018  
16-QFN Package Outline Drawing  
3.0 x 3.0 x 0.9 mm, 0.5mm Pitch, 1.70 x 1.70 mm Epad  
NL/NLG16P2, PSC-4169-02, Rev 04, Page 1  
‹ꢀ,QWHJUDWHGꢀ'HYLFHꢀ7HFKQRORJ\ꢁꢀ,QFꢂ  
16-QFN Package Outline Drawing  
3.0 x 3.0 x 0.9 mm, 0.5mm Pitch, 1.70 x 1.70 mm Epad  
NL/NLG16P2, PSC-4169-02, Rev 04, Page 2  
Package Revision History  
Description  
Date Created Rev No.  
Rev 04 Remove Bookmak at Pdf Format & Update Thickness Tolerance  
Oct 25, 2017  
Update Epad Range  
Aug 15, 2017 Rev 03  
‹ꢀ,QWHJUDWHGꢀ'HYLFHꢀ7HFKQRORJ\ꢁꢀ,QFꢂ  
厂商 型号 描述 页数 下载

IDT

 		8S89200 [ Low Skew, 2:1 LVDS MUX with 1:8 Fanout and Internal Termination ] 20 页

IDT

 		8S89200BKILF [ Low Skew, 2:1 LVDS MUX with 1:8 Fanout and Internal Termination ] 20 页

IDT

 		8S89200BKILFT [ Low Skew, 2:1 LVDS MUX with 1:8 Fanout and Internal Termination ] 20 页

IDT

 		8S89202 [ Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination ] 23 页

IDT

 		8S89202BKILF [ Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination ] 23 页

IDT

 		8S89202BKILFT [ Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination ] 23 页

IDT

 		8S89296 [ LVDS Programmable Delay Line ] 16 页

IDT

 		8S89296NLGI [ LVDS Programmable Delay Line ] 16 页

IDT

 		8S89296NLGI8 [ LVDS Programmable Delay Line ] 16 页

IDT

 		8S89831AKILF [ Differential LVPECL-To-LVPECL/ECL Fanout Buffer ] 21 页

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