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8S89832I

型号：

8S89832I

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

14 页

PDF大小：

321 K

下载PDF手册
Low Skew , 1-to-4 Differential-to-LVDS  
Fanout Buffer  
8S89832I  
Data Sheet  
Description  
Features  
The 8S89832I is a high speed 1-to-4 Differential-to-LVDS Fanout  
Buffer. The 8S89832I is optimized for high speed and very low output  
skew, making it suitable for use in demanding applications such as  
SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The  
internally terminated differential input and VREF_AC pin allow other  
differential signal families such as LVPECL, LVDS, and SSTL to be  
easily interfaced to the input with minimal use of external  
• Four differential LVDS output pairs  
• IN, nIN input pairs can accept the following differential input levels:  
LVPECL, LVDS, SSTL  
• 50internal input termination to VT  
• Maximum output frequency: 2GHz  
• Output skew: 25ps (maximum)  
• Part-to-part skew: 200ps (maximum)  
• Propagation delay: 550ps (maximum)  
• Additive phase jitter, RMS: 0.09ps (typical)  
• Full 2.5V supply mode  
components. The device also has an output enable pin that may be  
useful for system test and debug purposes.  
The 8S89832I is packaged in a small 3mm x 3mm 16-pin VFQFN  
package which makes it ideal for use in space-constrained  
applications.  
• -40°C to 85°C ambient operating temperature  
• Available in lead-free (RoHS 6) package  
Pin Assignment  
Block Diagram  
Q0  
16 15 14 13  
1
2
3
Q1  
nQ1  
Q2  
12  
11  
10  
IN  
nQ0  
VT  
VREF_AC  
IN  
Q1  
50Ω  
50Ω  
nQ2  
4
nIN  
9
VT  
nQ1  
5
6
7
8
nIN  
Q2  
VREF_AC  
EN  
8S89832I  
nQ2  
D
Q
16-Lead VFQFN  
3mm x 3mm x 0.925mm package body  
Q3  
CLK  
K Package  
Top View  
nQ3  
©2017 Integrated Device Technology, Inc.  
1
September 22, 2017  
8S89832I Data Sheet  
Table 1. Pin Descriptions  
Number  
1, 2  
Name  
Type  
Description  
Q1, nQ1  
Q2, nQ2  
Q3, nQ3  
Output  
Output  
Output  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
3, 4  
5, 6  
7, 14  
VDD  
Power  
Positive supply pins.  
Synchronizing clock enable. When LOW, Qx outputs will go LOW and nQx outputs will  
go HIGH on the next LOW transition at IN inputs. Input threshold is VDD/2V. Includes a  
37kpullup resistor. Default state is HIGH when left floating. The internal latch is  
clocked on the falling edge of the input signal IN. See Table 3A  
8
EN  
Input  
Pullup  
LVTTL / LVCMOS interface levels.  
9
10  
nIN  
VREF_AC  
VT  
Input  
Output  
Input  
Inverting differential clock input. 50internal input termination to VT.  
Reference voltage for AC-coupled applications.  
Termination input.  
11  
12  
IN  
Input  
Non-inverting differential clock input. 50internal input termination to VT.  
Power supply ground.  
13  
GND  
Power  
Output  
15, 16  
Q0, nQ0  
Differential output pair. LVDS interface levels.  
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
pF  
Input Capacitance  
Input Pullup Resistor  
2
RPULLUP  
37  
k  
©2017 Integrated Device Technology, Inc.  
2
September 22, 2017  
8S89832I Data Sheet  
Function Tables  
Table 3A. Control Input Function Table  
Input  
EN  
0
Outputs  
Q[0:3]  
Disabled; LOW  
Enabled  
nQ[0:3]  
Disabled; HIGH  
Enabled  
1
NOTE: EN switches, the clock outputs are disabled or enabled  
following a falling input clock edge as shown in Figure 1.  
Figure 1. EN Timing Diagram  
EN  
VDD/2  
VDD/2  
tS  
tH  
nIN  
IN  
VIN  
tPD  
→
←
nQx  
Qx  
VOD  
Table 3B. Truth Table  
Inputs  
Outputs  
IN  
0
nIN  
1
EN  
Q[0:3]  
nQ[0:3]  
1
1
0
0
1
1
0
1
0
X
X
0 (NOTE 1)  
1 (NOTE 1)  
NOTE 1: On next negative transition of the input signal (IN).  
©2017 Integrated Device Technology, Inc.  
3
September 22, 2017  
8S89832I Data Sheet  
Absolute Maximum Ratings  
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.  
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond  
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for  
extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VDD  
Inputs, VI  
4.6V  
-0.5V to VDD + 0.5V  
Outputs, IO  
Continuous Current  
Surge Current  
10mA  
15mA  
Input Current, IN, nIN  
±50mA  
VT Current, IVT  
±100mA  
Input Sink/Source, IREF_AC  
± 0.5mA  
Operating Temperature Range, TA  
Package Thermal Impedance, JA, (Junction-to-Ambient)  
Storage Temperature, TSTG  
-40°C to +85°C  
74.7C/W (0 mps)  
-65C to 150C  
DC Electrical Characteristics  
Table 4A. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C  
Symbol Parameter  
VDD Positive Supply Voltage  
IDD Power Supply Current  
Test Conditions  
Minimum  
Typical  
Maximum  
2.625  
95  
Units  
V
2.375  
2.5  
mA  
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C  
Symbol Parameter  
Test Conditions  
Minimum  
1.7  
Typical  
Maximum  
VDD + 0.3  
0.7  
Units  
V
VIH  
VIL  
IIH  
Input High Voltage  
Input Low Voltage  
Input High Current  
Input Low Current  
-0.3  
V
VDD = VIN = 2.625V  
10  
µA  
µA  
IIL  
VDD = 2.625V, VIN = 0V  
-150  
©2017 Integrated Device Technology, Inc.  
4
September 22, 2017  
8S89832I Data Sheet  
Table 4C. Differential DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C  
Symbol  
RIN  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
60  
Units  
Differential Input Resistance  
Input High Voltage  
IN, nIN  
IN, nIN  
IN, nIN  
IN to VT, nIN to VT  
40  
1.2  
0
50  
VIH  
VDD  
V
VIL  
Input Low Voltage  
VIH – 0.15  
1.2  
V
VIN  
Input Voltage Swing; NOTE 1  
Differential Input Voltage Swing  
Input Current; NOTE 2  
Reference Voltage  
0.15  
0.3  
V
VDIFF_IN  
IIN  
V
IN, nIN  
35  
mA  
V
VREF_AC  
VDD – 1.40  
VDD – 1.35  
VDD – 1.30  
NOTE 1: VIL should not be less than -0.3V.  
NOTE 2: Guaranteed by design.  
Table 4D. LVDS DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C  
Symbol  
VOD  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
454  
Units  
mV  
mV  
V
Differential Output Voltage  
VOD Magnitude Change  
Offset Voltage  
247  
VOD  
VOS  
50  
1.125  
1.375  
50  
VOS  
VOS Magnitude Change  
mV  
AC Electrical Characteristics  
Table 5. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C  
Symbol Parameter Test Conditions  
fOUT Operating Frequency  
Minimum  
Typical  
Maximum  
Units  
2
GHz  
Propagation Delay; (Differential)  
NOTE 1  
tPD  
300  
550  
ps  
tsk(o)  
Output Skew; NOTE 2, 3  
25  
ps  
ps  
tsk(pp)  
Part-to-Part Skew; NOTE 3, 4  
200  
Buffer Additive Phase Jitter, RMS; refer to  
Additive Phase Jitter Section  
200MHz, Integration Range:  
12kHz - 20MHz  
tjit  
0.09  
ps  
ts /tH  
Clock Enable Setup Time EN to IN, nIN  
Output Rise/Fall Time  
300  
50  
ps  
ps  
tR / tF  
20% to 80%  
235  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device  
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal  
equilibrium has been reached under these conditions.  
All parameters are measured at 1.5GHz unless otherwise noted.  
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.  
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.  
Measured at the output differential cross points.  
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.  
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency  
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.  
©2017 Integrated Device Technology, Inc.  
5
September 22, 2017  
8S89832I Data Sheet  
Additive Phase Jitter  
The spectral purity in a band at a specific offset from the  
fundamental. When the required offset is specified, the phase noise  
is called a dBc value, which simply means dBm at a specified offset  
from the fundamental. By investigating jitter in the frequency  
domain, we get a better understanding of its effects on the desired  
application over the entire time record of the signal. It is  
mathematically possible to calculate an expected bit error rate given  
a phase noise plot.  
fundamental compared to the power of the fundamental is called the  
dBc Phase Noise. This value is normally expressed using a Phase  
noise plot and is most often the specified plot in many applications.  
Phase noise is defined as the ratio of the noise power present in a  
1Hz band at a specified offset from the fundamental frequency to the  
power value of the fundamental. This ratio is expressed in decibels  
(dBm) or a ratio of the power in the 1Hz band to the power in the  
Additive Phase Jitter @ 200MHz  
12kHz to 20MHz = 0.09ps (typical)  
Offset from Carrier Frequency (Hz)  
As with most timing specifications, phase noise measurements has  
issues relating to the limitations of the equipment. Often the noise  
floor of the equipment is higher than the noise floor of the device.  
This is illustrated above. The device meets the noise floor of what is  
shown, but can actually be lower. The phase noise is dependent on  
the input source and measurement equipment.  
The source generator “IFR2042 10kHz – 56.4GHz Low Noise Signal  
Generator as external input to an Agilent 8133A 3GHz Pulse  
Generator”.  
©2017 Integrated Device Technology, Inc.  
6
September 22, 2017  
8S89832I Data Sheet  
Parameter Measurement Information  
V
DD  
nIN  
IN  
V
VIN  
VIH  
Cross Points  
DD  
VIL  
GND  
nIN  
IN  
V
,
IN  
LVDS Output Load AC Test Circuit  
VOUT  
Single-Ended Voltage Swing  
Part 1  
nQx  
nIN  
IN  
V
,
DIFF_IN  
Qx  
VDIFF_OUT  
Part 2  
nQy  
Qy  
Differential Voltage Swing = 2 x VIN  
tsk(pp)  
Part-to-Part Skew  
Differential Input Level  
nQx  
Qx  
VDIFF_IN, VDIFF_OUT  
VIN, VOUT  
700mV  
(typical)  
350mV  
(typical)  
nQy  
Qy  
Single-Ended & Differential Input, Output Voltage Swing  
Output Skew  
©2017 Integrated Device Technology, Inc.  
7
September 22, 2017  
8S89832I Data Sheet  
Parameter Measurement Information, continued  
nQ0, nQ1  
80%  
80%  
tR  
VOD  
20%  
20%  
Q0, Q1  
tF  
Output Rise/Fall Time  
Differential Output Voltage Setup  
nIN  
IN  
nQ0,nQ1  
Q0,Q1  
tPD  
Propagation Delay  
Offset Voltage Setup  
©2017 Integrated Device Technology, Inc.  
8
September 22, 2017  
8S89832I Data Sheet  
Application Information  
Recommendations for Unused Output Pins  
Outputs  
LVDS Outputs  
All unused LVDS output pairs can be either left floating or terminated  
with 100across. If they are left floating, we recommend that there  
is no trace attached.  
2.5V LVPECL Input with Built-In 50Termination Interface  
The IN /nIN with built-in 50terminations accept LVDS, LVPECL,  
SSTL and other differential signals. Both differential signals must  
meet the VPP and VCMR input requirements. Figures 2A to 2D show  
interface examples for the IN /nIN with built-in 50termination input  
driven by the most common driver types. The input interfaces  
suggested here are examples only. If the driver is from another  
vendor, use their termination recommendation. Please consult with  
the vendor of the driver component to confirm the driver termination  
requirements.  
2.5V  
2.5V  
Zo = 50Ω  
Zo = 50Ω  
R1  
R2  
25Ω  
IN  
VT  
nIN  
Receiver  
With  
25Ω  
SSTL  
Built-In  
50Ω  
Figure 2B. IN/nIN Input with Built-In 50Driven by an  
SSTL Driver  
Figure 2A. IN/nIN Input with Built-In 50Driven by an  
LVDS Driver  
Figure 2C. IN/nIN Input with Built-In 50Driven by a  
Figure 2D. IN/nIN Input with Built-In 50Driven by an  
CML Driver  
LVPECL Driver  
©2017 Integrated Device Technology, Inc.  
9
September 22, 2017  
8S89832I Data Sheet  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 3. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally/  
Electrically Enhance Leadframe Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
SOLDER  
SOLDER  
PIN  
PIN  
EXPOSED HEAT SLUG  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
2.5V LVDS Driver Termination  
Figure 4 shows a typical termination for LVDS driver in  
characteristic impedance of 100differential (50single)  
transmission line environment. For buffer with multiple LVDS driver,  
it is recommended to terminate the unused outputs.  
Figure 4. Typical LVDS Driver Termination  
©2017 Integrated Device Technology, Inc.  
10  
September 22, 2017  
8S89832I Data Sheet  
Power Considerations  
This section provides information on power dissipation and junction temperature for the 8S89832I.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the 8S89832I is the sum of the core power plus the analog power plus the power dissipated in the load(s).  
The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.  
•
Power (coreM) AX = VDD_MAX * IDD_MAX = 2.625V * 95mA = 249.375mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 74.7°C/W per Table 6 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.249W * 74.7°C/W = 103.6°C. This is well below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 6. Thermal Resistance JA for 16 Lead VFQFN Forced Convection  
JA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
74.7°C/W  
65.3°C/W  
58.5°C/W  
Reliability Information  
Table 7. JA vs. Air Flow Table for a 16 Lead VFQFN  
JA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
74.7°C/W  
65.3°C/W  
58.5°C/W  
Transistor Count  
The transistor count for 8S89832I is: 339  
Pin compatible with SY89832U.  
This device is pin and function compatible and a suggested replacement for 889832.  
©2017 Integrated Device Technology, Inc.  
11  
September 22, 2017  
8S89832I Data Sheet  
Package Outline Drawings  
The package outline drawings are located in the last section of this document. The package information is the most current data available and  
is subject to change without notice or revision of this document.  
Ordering Information  
Table 9. Ordering Information  
Part/Order Number  
8S89832AKILF  
8S89832AKILFT  
Marking  
832A  
832A  
Package  
“Lead-Free” 16 Lead VFQFN  
“Lead-Free” 16 Lead VFQFN  
Shipping Packaging  
Tube  
Temperature  
-40C to 85C  
-40C to 85C  
Tape & Reel  
Revision History  
Revision Date  
Description of Change  
Updated the package outline drawings; however, no mechanical changes  
Completed other minor improvements  
September 22, 2017  
Removed ICS from part numbers where needed.  
General Description - Deleted ICS chip.  
January 27, 2016  
January 11, 2010  
Ordering Information - Deleted quantity from tape and reel. Deleted LF note below table.  
Updated header and footer.  
Parameter Measurement Information - updated Differential Input Level diagram.  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
www.IDT.com/go/support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without  
notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed  
in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any  
particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual  
property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of  
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.  
©2017 Integrated Device Technology, Inc.  
12  
September 22, 2017  
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