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8P79818NLGI8

型号：

8P79818NLGI8

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

34 页

PDF大小：

869 K

下载PDF手册
Programmable Low Additive Jitter 2:8  
8P79818  
Datasheet  
Buffer with Dividers and Universal Outputs  
Description  
Features  
▪ Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS  
The device is intended to take 1 or 2 reference clocks, select  
between them, using a pin or register selection and generate up to 8  
outputs that may be the same as the reference frequency or  
integer-divider versions of it.  
reference clocks  
— Accepts input frequencies ranging from 1PPS (1Hz) to  
700MHz  
▪ Select which of the two input clocks is to be used as the reference  
The 8P79818 supports two output banks, each with its own divider  
and power supply. All outputs in one bank would generate the same  
output frequency, but each output can be individually controlled for  
output type, output enable or even powered-off.  
clock for which divider via pin or register selection  
— Switchover will not generate any runt clock pulses on the  
output  
▪ Generates eight differential outputs  
The device supports a serial port for configuration of the parameters  
while in operation. The serial port can be selected to use the I2C or  
SPI protocol. After power-up, all outputs will come up in LVDS mode  
and may be programmed to other configurations over the serial port.  
Outputs may be enabled or disabled under control of the OE input  
pin.  
or eight LVCMOS outputs, Bank A only  
— Differential outputs selectable as LVPECL, LVDS, CML or  
HCSL  
— Differential outputs support frequencies from 1PPS to 700MHz  
— LVCMOS outputs support frequencies from 1PPS to 200MHz  
The device can operate over the -40°C to +85°C temperature range.  
— LVCMOS outputs in the same pair may be inverted or in-phase  
relative to one another  
▪ Outputs arranged in 2 banks of 4 outputs each  
— Each bank supports a separate power supply of 3.3V, 2.5V or  
1.8V  
— 1.5V output voltage is also supported for LVCMOS, Bank A  
only  
— One divider per output bank, supporting divide ratios of 2...511  
or divider bypass  
▪ Output enable control pin  
— Output enable or disable will not cause any runt pulses  
▪ Register programmable via I2C / SPI serial port  
— Individual output enables, output type selection and output  
power-down control bits supported  
— Input mux selection control bit  
▪ Core voltage supply of 3.3V, 2.5V or 1.8V  
▪ -40°C to +85°C ambient operating temperature  
▪ Lead-free (RoHS 6) packaging  
©2016 Integrated Device Technology, Inc.  
1
December 19, 2016  
8P79818 Datasheet  
Block Diagram  
Figure 1: Block Diagram  
Bank A  
QA0  
nQA0  
DIV A  
(2 to 511)  
QA1  
nQA1  
PU  
CLK_SEL  
QA2  
Div‐by‐1  
nQA2  
PD  
CLK0  
QA3  
nQA3  
nCLK0  
PU/PD  
Bank B  
QB0  
PD  
CLK1  
nQB0  
DIV B  
(2 to 511)  
nCLK1  
QB1  
PU/PD  
PU  
nQB1  
OE  
QB2  
nQB2  
Div‐by‐1  
PU  
PU  
PU  
SCLK  
QB3  
nQB3  
SDATA/SDI  
SA0/nCS  
Logic  
PD  
nI2C/SPI  
8P79818 transistor count: 33,394  
©2016 Integrated Device Technology, Inc.  
2
December 19, 2016  
8P79818 Datasheet  
Pin Assignment  
Figure 2: Pin Assignments for 5mm x 5mm 32-Lead VFQFN Package (Top View)  
31 30 29 28 27 26 25  
32  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
SDO  
QA0  
CLK_SEL  
QB0  
nQA0  
QA1  
nQB0  
QB1  
8P79818  
nQA1  
VCCOA  
QA2  
nQB1  
VCCOB  
QB2  
nQA2  
nQB2  
10 11 12 13 14 15 16  
9
Pin Description and Characteristic Tables  
Table 1: Pin Description  
Number  
Name  
Type[a]  
Description  
2
1
2
SDO  
QA0  
Output  
Output  
Output  
Output  
Output  
Power  
Output  
Output  
Output  
Output  
SPI mode data output signal. Unused in I C mode.  
Positive differential clock output. Included in Bank A. Refer to Output Drivers section for details.  
Negative differential clock output. Included in Bank A. Refer to Output Drivers section for details.  
Positive differential clock output. Included in Bank A. Refer to Output Drivers section for details.  
Negative differential clock output. Included in Bank A. Refer to Output Drivers section for details.  
Output supply for output Bank A.  
3
nQA0  
QA1  
4
5
nQA1  
VCCOA  
QA2  
6
7
Positive differential clock output. Included in Bank A. Refer to Output Drivers section for details.  
Negative differential clock output. Included in Bank A. Refer to Output Drivers section for details.  
Positive differential clock output. Included in Bank A. Refer to Output Drivers section for details.  
Negative differential clock output. Included in Bank A. Refer to Output Drivers section for details.  
Select protocol for serial port:  
8
nQA2  
QA3  
9
10  
nQA3  
2
11  
nI2C/SPI  
Input (PD)  
0 = I C mode  
1 = SPI mode  
12  
13  
VCC  
Power  
Core logic supply.  
2
SA0/nCS  
Input (PU)  
SPI chip select input (active low) in SPI mode. Base address bit 0 in I C mode.  
©2016 Integrated Device Technology, Inc.  
3
December 19, 2016  
8P79818 Datasheet  
Table 1: Pin Description (Cont.)  
Master output enable control  
14  
OE  
Input (PU)  
0 = All outputs high-impedance  
1 = All outputs enabled or disabled under control of register bits  
15  
16  
17  
18  
19  
20  
21  
22  
23  
nQB3  
QB3  
Output  
Output  
Output  
Output  
Power  
Output  
Output  
Output  
Output  
Negative differential clock output. Included in Bank B. Refer to Output Drivers section for details.  
Positive differential clock output. Included in Bank B. Refer to Output Drivers section for details.  
Negative differential clock output. Included in Bank B. Refer to Output Drivers section for details.  
Positive differential clock output. Included in Bank B. Refer to Output Drivers section for details.  
Output supply for output Bank B.  
nQB2  
QB2  
VCCOB  
nQB1  
QB1  
Negative differential clock output. Included in Bank B. Refer to Output Drivers section for details.  
Positive differential clock output. Included in Bank B. Refer to Output Drivers section for details.  
Negative differential clock output. Included in Bank B. Refer to Output Drivers section for details.  
Positive differential clock output. Included in Bank B. Refer to Output Drivers section for details.  
nQB0  
QB0  
Input clock selection control pin. This pin may be disabled by register control, but if enabled  
(default) its function is:  
24  
CLK_SEL  
Input (PU)  
0 = CLK0 is selected  
1 = CLK1 is selected  
25  
26  
CLK1  
Input (PD)  
Non-inverting differential clock input.  
Inverting differential clock input. VCC/2 when left floating (set by the internal pull-up and  
pull-down resistors).  
nCLK1  
Input (PU/ PD)  
27  
28  
VCC  
Power  
Core logic supply.  
2
SCLK  
Input (PU)  
Serial port input clock for either SPI or I C mode.  
Input/Output  
(PU)  
Input (PU)  
2
In I C mode, this is the bi-directional data signal for the serial port  
SDATA/  
SDI  
29  
In SPI mode, this is the data input signal.  
30  
31  
VCC  
Power  
Core logic supply.  
Inverting differential clock input. VCC/2 when left floating (set by the internal pull-up and  
pull-down resistors).  
nCLK0  
Input (PU/ PD)  
32  
CLK0  
VEE  
Input (PD)  
Ground  
Non-inverting differential clock input.  
Must be connected to ground (GND).  
EP  
a. Pull-up (PU) and pull-down (PD) resistors are indicated in parentheses. Pullup and Pulldown refer to internal input resistors. See Table 10,  
DC Input/ Output Characteristics, for typical values.  
©2016 Integrated Device Technology, Inc.  
4
December 19, 2016  
8P79818 Datasheet  
Principles of Operation  
Input Selection  
The 8P79818 supports two input references: CLK0 and CLK1 that may be driven with differential or single-ended clock signals. Either or both  
may be used as the source frequency for either output divider under control of the CLK_SEL input pin or under register control.  
The CLK_SEL pin is the default selection mechanism and selects whether both dividers are driven by the CLK0, nCLK0 input (CLK_SEL =  
Low) or by the CLK1, nCLK1 input (CLK_SEL = High).  
If the user enables register control via the SEL_REG control bit, then there are 4 selection options available as shown in Table 2.  
Table 2: Input Selection Register Control (SEL_REG = 1)  
CLK_SEL [1:0]  
Description  
0
0
0
1
Divider A & B both driven from CLK0  
Divider A driven from CLK1 &  
Divider B driven from CLK0  
Divider A driven from CLK0 &  
Divider B driven from CLK1  
1
1
0
1
Divider A & B both driven from CLK1  
Output Dividers  
Each bank of outputs has its own divider. All outputs in the same bank will be driven by that divider and so will all have the same frequency.  
Divider A supplies the QA output bank and Divider B supplies the QB output bank. Each divider is capable of being driven by the same or a  
different input frequency. Each divider can pass that input frequency directly to the outputs or to divide it by any integer from 2 up to 511.  
Output Drivers  
The QA[0:3] and QB[0:3] clock outputs are provided with register-controlled output drivers. By selecting the output drive type in the appropriate  
register, any of these outputs can support LVCMOS, LVPECL, CML, HCSL or LVDS logic levels.  
CML operation supports both a 400mV peak-peak swing and an 800mV peak-peak swing selection.  
The operating voltage ranges of each output bank is determined by its independent output power pin (VCCOA or VCCOB). Output voltage levels  
of 1.8V, 2.5V or 3.3V are supported for differential operation and LVCMOS operation. In addition, LVCMOS output operation supports 1.5V  
VCCO  
.
A global OE input pin is provided. If the OE pin is negated (Low), then all outputs will be in a high-impedance state. If the OE pin is asserted  
(High), then each output will behave as indicated by its individual register enable bit. Using the global OE pin to enable or disable outputs will  
not result in any ‘runt’ clock pulses on the outputs.  
Each output bank may be enabled or disabled using the SYNC_DISx register bit. Using these bits to enable or disable outputs will not result in  
any ‘runt’ clock pulses on the outputs.  
Individual outputs within a bank may be enabled or disabled using the DIS_Qxm register bits. These bits however may result in ‘runt’ pulses on  
the outputs if the output is otherwise enabled, so it is recommended that the entire bank be disabled via the appropriate SYNC_DISx register  
bit while an individual output is being enabled using the DIS_Qxm bit to avoid a possible ‘runt’ pulse on the output. If ‘runt’ pulses are not a  
concern, then the DIS_Qxm bits may be used directly.  
LVCMOS Operation  
When a given output is configured to provide LVCMOS levels, then both the Q and nQ outputs will toggle at the selected output frequency. All  
the previously described configuration and control apply equally to both outputs. Frequency, voltage levels and enable / disable status apply to  
both the Q and nQ pins.  
When configured as LVCMOS, the Q & nQ outputs can be selected to be phase-aligned with each other or inverted relative to one another.  
Phase-aligned outputs will have increased simultaneous switching currents which can negatively affect phase noise performance and power  
consumption. It is recommended that use of this selection be kept to a minimum.  
©2016 Integrated Device Technology, Inc.  
5
December 19, 2016  
8P79818 Datasheet  
Power-Saving Modes  
To allow the device to consume the least power possible for a given application, the following functions are included under register control:  
▪ Any unused output can be individually powered-off.  
▪ If either bank is completely unused, all logic, including the dividers for that bank may be completely powered-off.  
▪ Clock gating on logic that is not being used.  
Device Start-up Behavior  
The device will power-up with all outputs enabled in LVDS mode and all dividers bypassed.  
Serial Control Port Description  
Serial Control Port Configuration Description  
The device has a serial control port capable of responding as a slave in an I2C or SPI compatible configuration, to allow access to any of the  
internal registers for device programming or examination of internal status. All registers are configured to have default values. See the  
specifics for each register for details. Selection of I2C versus SPI protocol will be done via the nI2C/SPI input pin.  
SPI Mode Operation  
SPI mode can be enabled via pin selection from power-up. The following information assumes SPI mode has been selected.  
In a read operation (R/W bit is '1'), data on SDO will be clocked out on the falling edge of SCLK.  
In a write operation (R/W bit is '0'), data on SDI will be clocked in on the rising edge of SCLK.  
Figure 3: SPI Read Sequencing Diagram  
©2016 Integrated Device Technology, Inc.  
6
December 19, 2016  
8P79818 Datasheet  
During SPI Write operations, the user may continue to hold nCS low and provide further bytes of data for up to a total of 16 bytes in a single  
block write. Data is written directly into the appropriate register as it is received.  
Figure 4: SPI Write Sequencing Diagram  
Figure 5: SPI Read/Write Timing Diagram  
tsu1  
tpwh  
tpwl  
nCS  
th2  
tsu2  
SCLK  
SDI  
R/W  
A0  
td2  
td1  
Hi‐Z  
Hi‐Z  
SDO  
Table 3: Timing Characteristics in SPI Mode[a]  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
tpw  
tpw1  
tpw2  
tsu1  
th1  
SCLK Period  
20  
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SCLK Pulse Width Low  
SCLK Pulse Width High  
8
Valid nCS to SCLK Rising Setup Time  
Valid nCS After Valid SCLK Hold Time (CLKE = 0/1)  
Valid SDI to SCLK Rising Setup Time  
10  
10  
5
tsu2  
th2  
Valid SDI after valid SCLK Hold Time  
5
td1  
SCLK falling (rising in CLKE = 1 case) to Valid Data Delay Time  
nCS rising edge to SDO High Impedance Delay Time  
5
td2  
10  
Time between Consecutive Read-Read or Read-Write Accesses  
(nCS rising edge to nCS falling edge)  
tcsh  
20  
ns  
a. Specifications guaranteed by design and characterization.  
©2016 Integrated Device Technology, Inc.  
7
December 19, 2016  
8P79818 Datasheet  
2
I C Mode Operation  
The I2C interface is designed to fully support v1.0 of the I2C specification for normal and fast mode operation. The device acts as a slave  
device on the I2C bus at 100kHz or 400kHz using an address of 110110x (binary), where the value of ‘x’ is set by the SA0/nCS input pin. The  
interface accepts byte-oriented block write and block read operations. One address byte specifies the register address of the byte position of  
the first register to write or read. Data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant  
bit first). Read and write block transfers can be stopped after any complete byte transfer. During a write operation, data will be written to the  
registers directly as each byte is received.  
For full electrical I2C compliance, it is recommended to use external pull-up resistors for SDATA and SCLK. The internal pull-up resistors have  
a size of 51ktypical.  
Figure 6: Slave Read and Write Cycle Sequencing  
Current Read  
S
Dev Addr + R  
A
A
A
Data 0  
A
Data 1  
A
A
Data n  
Data 0  
A
A
P
Sequential Read  
S
Dev Addr + W  
Offset Addr MSB  
Offset Addr MSB  
A
A
Sr  
Dev Addr + R  
A
A
Data 1  
A
A
Data n  
A
P
Sequential Write  
S
Dev Addr + W  
Data 0  
A
Data 1  
A
Data n  
A
P
S = start  
from master to slave  
from slave to master  
Sr = repeated start  
A = acknowledge  
A = none acknowledge  
P = stop  
©2016 Integrated Device Technology, Inc.  
8
December 19, 2016  
8P79818 Datasheet  
Register Descriptions  
Table 4: Register Blocks  
Register Ranges Offset (Hex)  
Register Block Description  
0 1  
2 5  
6 9  
A B  
C F  
Device control  
Bank A control  
Bank B control  
Reserved  
Divide ratios  
©2016 Integrated Device Technology, Inc.  
9
December 19, 2016  
8P79818 Datasheet  
Table 5: Device Control Register Bit Field Locations  
Address (Hex)  
D7  
D6  
CLK_SEL[1:0]  
BKB_Vx  
D5  
D4  
D3  
D2  
D1  
D0  
0
1
CLKMODE  
BKA_Vx  
SEL_REG  
Rsvd  
Rsvd  
Rsvd  
DIV_SYNC  
SYNC_DISA SYNC_DISB PWR_DNA  
PWR_DNB  
DIS_DIVA  
DIS_DIVB  
Bit Field Name  
Field Type  
Default Value  
Description  
Clock switchover mode selection:  
0 = Forced clock switch (may result in glitches as clocks switch)  
CLKMODE  
R/W  
R/W  
0b  
1 = Glitch-less clock switch (may remain on original clock source if that  
source is no longer toggling)  
Select which input clock is to be used as the reference clock. These bits are  
only in effect when SEL_REG = 1:  
00 = CLK0, nCLK0 input drives both Divider A & Divider B  
CLK_SEL[1:0]  
00b  
01 = CLK1, nCLK1 input drives Divider A & CLK0, nCLK0 drives Divider B  
10 = CLK0, nCLK0 input drives Divider A & CLK1, nCLK1 drives Divider B  
11 = CLK1, nCLK1 input drives both Divider A & Divider B  
Determines if input clock selection is to be performed by pin or register:  
SEL_REG  
Rsvd  
R/W  
R/W  
0b  
0 = CLK_SEL input pin controls reference selection mux  
1 = CLK_SEL register bits controls reference selection mux  
Reserved. Always write ‘0’ to this bit location. Read values are not defined.  
Divider synchronization control:  
0 = Dividers running normally  
DIV_SYNC  
R/W  
0b  
1 = Dividers in reset (output clocks halted)  
1–>0 transition on this bit will synchronize the Bank A & Bank B output  
dividers  
Bank A voltage setting for optimal performance:  
0 = VCCOA is 3.3V  
BKA_Vx  
BKB_Vx  
R/W  
R/W  
0b  
0b  
1 = VCCOA is 2.5V,1.8V, and 1.5V  
Bank B voltage setting for optimal performance:  
0 = VCCOB is 3.3V  
1 = VCCOB is 2.5V,1.8V  
Glitch-free output enable bit for Bank A outputs:  
0 = Outputs in Bank A are enabled glitch-lessly as indicated by their individual  
DIS_QAm bits  
1 = All outputs for Bank A are high-impedance  
SYNC_DISA  
SYNC_DISB  
R/W  
R/W  
0b  
0b  
Glitch-free output enable bit for Bank B outputs:  
0 = Outputs in Bank B are enabled glitch-lessly as indicated by their individual  
DIS_QBm bits  
1 = All outputs for Bank B are high-impedance  
©2016 Integrated Device Technology, Inc.  
10  
December 19, 2016  
8P79818 Datasheet  
Bit Field Name  
Field Type  
Default Value  
Description  
Power-down control for Bank A outputs:  
0 = All outputs for Bank A are powered (SYNC_DISA should be 1 when  
powering-up the bank to prevent glitches on the output)  
1 = All outputs in Bank A are powered-off  
PWR_DNA  
R/W  
0b  
Power-down control for Bank B outputs:  
0 = All outputs for Bank B are powered (SYNC_DISB should be 1 when  
powering-up the bank to prevent glitches on the output)  
1 = All outputs in Bank B are powered-off  
PWR_DNB  
R/W  
0b  
Power-down output divider for Bank A (DIVA must be set to 000h to bypass):  
0 = Output divider for Bank A is powered  
DIS_DIVA  
DIS_DIVB  
R/W  
R/W  
0b  
0b  
1 = Output divider for Bank A is powered-down  
Power-down output divider for Bank B (DIVB must be set to 000h to bypass):  
0 = Output divider for Bank B is powered  
1 = Output divider for Bank B is powered-down  
©2016 Integrated Device Technology, Inc.  
11  
December 19, 2016  
8P79818 Datasheet  
Table 6: Bank A Control Register Bit Field Locations  
Address (Hex)  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
QA_POL0  
2
3
4
5
Rsvd  
TERM_A  
MODE_QA3[2:0]  
MODE_QA1[2:0]  
DIS_QA0  
QA_POL3  
QA_POL2  
QA_POL1  
Rsvd  
Rsvd  
MODE_QA2[2:0]  
MODE_QA0[2:0]  
DIS_QA3  
DIS_QA2  
DIS_QA1  
Rsvd  
Bit Field Name  
Field Type  
Default Value  
Description  
Indicates termination used on Bank A outputs when HCSL mode is selected:  
TERM_A  
R/W  
0b  
0h  
0 = 33/ 50  
1 = 50  
Output polarity selection for output pair nQAm, QAm in LVCMOS mode:  
QA_POLm  
R/W  
R/W  
0 = nQAm pin is inverted relative to QAm pin when in LVCMOS mode  
1 = nQAm and QAm pins are in-phase when in LVCMOS mode  
Output driver mode of operation for output pair QAm, nQAm:  
000 = high-impedance  
001 = LVPECL  
010 = LVDS (default)  
011 = LVCMOS  
MODE_QAm[2:0]  
010b  
100 = HCSL  
101 = CML 400mV swing  
110 = CML 800mV swing  
111 = Reserved  
Disable output pair QAm, nQAm:  
0 = Output pair QAm, nQAm is enabled (disable output bank using  
SYNC_DISA to prevent runt pulses when enabling)  
DIS_QAm  
Rsvd  
R/W  
R/W  
0b  
1 = Output pair QAm, nQAm is powered-down  
Reserved. Always write 0 to this bit location. Read values are not defined.  
©2016 Integrated Device Technology, Inc.  
12  
December 19, 2016  
8P79818 Datasheet  
Table 7: Bank B Control Register Bit Field Locations  
Address (Hex)  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
6
7
8
9
Rsvd  
TERM_B  
MODE_QB3[2:0]  
MODE_QB1[2:0]  
DIS_QB0  
Rsvd  
Rsvd  
Rsvd  
Rsvd  
Rsvd  
Rsvd  
MODE_QB2[2:0]  
MODE_QB0[2:0]  
DIS_QB3  
DIS_QB2  
DIS_QB1  
Rsvd  
Bit Field Name  
Field Type  
Default Value  
Description  
Indicates termination used on Bank B outputs when HCSL mode is selected:  
TERM_B  
R/W  
0b  
0 = 33/ 50  
1 = 50  
Output driver mode of operation for output pair QBm, nQBm:  
000 = high-impedance  
001 = LVPECL  
010 = LVDS (default)  
011 = Rsvd  
MODE_QBm[2:0]  
R/W  
010b  
100 = HCSL  
101 = CML 400mV swing  
110 = CML 800mV swing  
111 = Reserved  
Disable output pair QBm, nQBm:  
0 = Output pair QBm, nQBm is enabled (disable output bank using  
SYNC_DISB to prevent runt pulses when enabling)  
DIS_QBm  
Rsvd  
R/W  
R/W  
0b  
1 = Output pair QBm, nQBm is powered-down  
Reserved. Always write 0 to this bit location. Read values are not defined.  
©2016 Integrated Device Technology, Inc.  
13  
December 19, 2016  
8P79818 Datasheet  
Table 8: Divide Ratio Register Field Locations  
Address (Hex)  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
C
D
E
F
DIVA[7:0]  
DIVB[7:0]  
Rsvd  
DIVB[8]  
DIVA[8]  
Rsvd  
Bit Field Name  
Field Type  
Default Value  
Description  
Divider ratio for Bank A outputs:  
00h 01h = Bypass divider and pass reference clock directly to the Bank A  
outputs  
DIVA[8:0]  
R/W  
000h  
02h 1FFh = ratio to be used by the A divider is value written here. For  
example writing a 4 in this field will results in a divide ratio of 4 being used.  
Divider ratio for Bank B outputs:  
00h 01h = Bypass divider and pass reference clock directly to the Bank B  
outputs  
DIVB[8:0]  
Rsvd  
R/W  
R/W  
000h  
02h 1FFh = ratio to be used by the B divider is value written here. For  
example writing a 4 in this field will results in a divide ratio of 4 being used.  
Reserved. Always write 0 to this bit location. Read values are not defined.  
©2016 Integrated Device Technology, Inc.  
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December 19, 2016  
8P79818 Datasheet  
Absolute Maximum Ratings  
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device.  
Functional operation of the 8P79818 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect  
device reliability.  
Table 9: Absolute Maximum Ratings  
Item  
Rating  
Supply voltage, VCCX[a] to GND  
3.6V  
Inputs SCLK, SDATA/SDI, SA0/nCS, CLK_SEL, CLK0, nCLK0,  
CLK1, nCLK1, OE, nI2C/SPI  
0.5V to 3.6V  
Outputs, IO QA[0:3], nQA[0:3], QB[0:3], nQB[0:3]  
Continuous current  
40mA  
60mA  
Surge current  
Outputs, VO QA[0:3], nQA[0:3], QB[0:3], nQB[0:3]  
Outputs, VO SDO, SDATA/SDI  
0.5V to 3.6V  
0.5V to 3.6V  
125°C  
Operating junction temperature  
Storage temperature, TSTG  
65°C to 150°C  
260°C  
Lead temperature (Soldering, 10s)  
a. VCCx denotes VCC, VCCOA, or VCCOB  
.
©2016 Integrated Device Technology, Inc.  
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December 19, 2016  
8P79818 Datasheet  
DC Characteristics  
Table 10: DC Input/ Output Characteristics  
Symbol  
Parameter  
Test Conditions  
Minimum Typical Maximum Units  
Cin  
Input capacitance  
LVPECL  
0.5  
0.8  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
k  
k  
LVDS  
1.2  
QA[0:3], nQA[0:3]  
QB[0:3], nQB[0:3]  
VCCOX[a] = 3.465V or 2.625V  
CML 400mV  
CML 800mV  
LVCMOS  
LVPECL  
0.48  
0.44  
2.33  
1.4  
Power  
Bank A  
V
V
V
CCOA = 3.465V or 2.625V  
dissipation  
capacitance  
(per output)  
CPD  
LVDS  
1.5  
QA[0:3], nQA[0:3]  
QB[0:3], nQB[0:3]  
CCOX = 1.89V  
CML 400mV  
CML 800mV  
LVCMOS  
0.53  
0.3  
Bank A  
CCOA = 1.89V or 1.575V  
2.1  
RPULLUP  
Input pull-up resistor  
51  
RPULLDOWN Input pull-down resistor  
51  
LVCMOS output type selected  
CCOA = 3.3V+5%  
24  
15  
26  
46  
V
LVCMOS output type selected  
CCOA = 2.5V+5%  
V
ROUT  
Output impedance  
QA[3:0], nQA[3:0]  
LVCMOS output type selected  
CCOA = 1.8V+5%  
V
LVCMOS output type selected  
CCOA = 1.5V+5%  
V
a. VCCOx denotes VCCOA and VCCOB  
.
©2016 Integrated Device Technology, Inc.  
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December 19, 2016  
8P79818 Datasheet  
,
Supply Voltage Characteristics  
Table 11: Power Supply Characteristics, VCC = 3.3V ±5%, VEE = 0V, TA = -40°C to +85°C[a]  
[b] [c]  
,
,
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VCC  
Core supply voltage  
3.135  
3.465  
V
VCCOA  
VCCOB  
,
Output supply voltage  
Core supply current  
1.71  
VCC  
V
ICC  
ICCOA  
23  
26  
mA  
mA  
mA  
mA  
DIV-by-1  
DIV A = DIV B = 2  
157  
125  
183  
177  
140  
206  
Output supply current  
Power supply current  
ICCOB  
IEE  
a. Internal dynamic switching current at maximum fOUT is included.  
b. All outputs configured for LVEPCL logic levels and not terminated.  
c. VCC VCCOA and VCCOB  
.
[b] [c]  
Table 12: Power Supply Characteristics, VCC = 2.5V ±5%, VEE = 0V, TA = -40°C to +85°C[a]  
,
,
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VCC  
Core supply voltage  
2.375  
2.625  
V
VCCOA  
VCCOB  
,
Output supply voltage  
Core supply current  
1.71  
VCC  
V
ICC  
ICCOA  
18  
20  
mA  
mA  
mA  
mA  
DIV-by-1  
DIV A = DIV B = 2  
156  
124  
177  
175  
139  
199  
Output supply current  
Power supply current  
ICCOB  
IEE  
a. Internal dynamic switching current at maximum fOUT is included.  
b. All outputs configured for LVEPCL logic levels and not terminated.  
c. VCC VCCOA and VCCOB  
.
©2016 Integrated Device Technology, Inc.  
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December 19, 2016  
8P79818 Datasheet  
[b] [c]  
Table 13: Power Supply Characteristics, VCC = 1.8V ±5%, VEE = 0V, TA = -40°C to +85°C[a]  
,
,
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VCC  
Core supply voltage  
1.71  
1.89  
V
VCCOA  
VCCOB  
,
Output supply voltage  
Core supply current  
1.71  
VCC  
V
ICC  
ICCOA  
14  
16  
mA  
mA  
mA  
mA  
DIV-by-1  
DIV A = DIV B = 2  
143  
117  
161  
160  
132  
181  
Output supply current  
Power supply current  
ICCOB  
IEE  
a. Internal dynamic switching current at maximum fOUT is included.  
b. All outputs configured for LVEPCL logic levels and not terminated.  
c. VCC VCCOA and VCCOB  
.
Table 14: Output Supply Current, VCC = 3.3V, 2.5V or 1.8V, VEE = 0V, TA = 25°C[a] [b]  
,
VCCOx[d] = 3.3V  
VCCOx[d] = 2.5V  
VCCOx[d] = 1.8V  
V
CC = 3.3V,  
76  
96  
73 119 60 75  
96  
67 92 58 68  
87  
66 72 53  
60  
71  
mA  
Bank A  
output  
supply  
current  
TA = 25°C  
ICCOA  
VCC  
=
3.3V 5%, 88 114 87 149 70 88 113 85 111 67 80 104 78 86 63  
TA = 85°C  
mA  
V
CC = 3.3V,  
Bank B  
output  
supply  
current  
76  
96  
73 119 60 75  
96  
67 92 58 68  
87  
66 72 53  
60  
71  
mA  
mA  
TA = 25°C  
ICCOB  
VCC = 3.3V,  
TA = 85°C  
88 114 87 149 70 88 113 85 111 67 80 104 78 86 63  
a. All outputs not terminated.  
b. VCC VCCOA and VCCOB  
c. Internal dynamic switching current at maximum fOUT is included.  
d. VCCOx denotes VCCOA and VCCOB  
.
.
©2016 Integrated Device Technology, Inc.  
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December 19, 2016  
8P79818 Datasheet  
DC Electrical Characteristics  
Table 15: LVCMOS/LVTTL Control / Status Signals DC Characteristics, VEE = 0V, TA = -40°C to +85°C  
Symbol  
Parameter  
Test Conditions  
VCC = 3.3V  
VCC = 2.5V  
Minimum  
Typical  
Maximum Units  
2.20  
1.85  
1.25  
–0.3  
–0.3  
–0.3  
VCC 0.3  
VCC 0.3  
VCC 0.3  
0.8  
V
V
V
V
V
V
VIH  
Input high voltage  
VCC = 1.8V  
VCC = 3.3V  
VIL  
Input low voltage  
V
CC = 2.5V  
0.7  
VCC = 1.8V  
0.7  
SA0/nCS, SDATA/SDI,  
SCLK, CLK_SEL, OE  
5
A  
A  
A  
Input  
high current  
VCC = VIN = 3.465V, 2.625V or  
1.89V  
IIH  
nI2C/SPI  
150  
SA0/nCS, SDATA/SDI,  
SCLK, CLK_SEL,OE  
–150  
Input  
low current  
V
V
CC = 3.465V, 2.625V or 1.89V,  
IN = 0V  
IIL  
nI2C/SPI  
–5  
2.6  
1.8  
A  
V
V
CC = 3.3V ±5%, IOH = –5mA  
Output  
high voltage  
VOH  
SDATA/SDI, SDO  
VCC = 2.5V ±5%, IOH = –5mA  
VCC = 1.8V ±5%, IOH = –5mA  
V
V
Output  
low voltage  
V
CC = 3.3V ±5% or 2.5V ±5% or  
VOL  
SDATA/SDI, SDO  
0.5  
V
1.8V ±5%, IOL = 5mA  
,
Table 16: Differential Input DC Characteristics, VCC = 3.3V±5%, 2.5V±5% or 1.8V±5%, VEE = 0V,  
TA = -40°C to +85°C  
Symbol  
Parameter  
CLKx, nCLKx[a]  
Test Conditions  
Minimum  
Typical  
Maximum Units  
Input  
high current  
IIH  
V
CC = VIN = 3.465V or 2.625V  
150  
A  
CLKx[a]  
nCLKx[a]  
Peak-to-peak voltage[b]  
Common mode input voltage[b], [c]  
VCC = 3.465V or 2.625V, VIN = 0V  
VCC = 3.465V or 2.625V, VIN = 0V  
–5  
–150  
0.15  
0
A  
A  
V
Input  
low current  
IIL  
VPP  
1.3  
VCMR  
VCC  
V
a. CLKx denotes CLK0, CLK1. nCLKx denotes nCLK0, nCLK1.  
b. VIL should not be less than –0.3V. VIH should not be higher than VCC  
c. Common mode voltage is defined as the cross-point.  
.
©2016 Integrated Device Technology, Inc.  
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December 19, 2016  
8P79818 Datasheet  
Table 17: LVPECL DC Characteristics, VCC = 3.3V±5%, 2.5V±5% or 1.8V±5%, VEE = 0V, TA = -40°C to +85°C  
VCCOx[a] = 3.3V±5%  
Min Typ Max  
VCCOx[a] = 2.5V±5%  
Min Typ Max  
VCCOx[a] = 1.8V±5%  
Min Typ Max  
Symbol  
Parameter  
Units  
Output  
Qx,  
VCCOx  
1.30  
-
VCCOx  
0.80  
-
-
VCCOx  
1.35  
-
VCCOx  
0.80  
-
-
VCCOx  
1.50  
-
VCCOx  
0.90  
-
VOH  
V
high voltage[b] nQx[c]  
Output  
low voltage  
Qx,  
VCCOx  
2.00  
-
VCCOx  
1.75  
VCCOx  
2.00  
-
VCCOx  
1.75  
VOL  
VEE  
0.25  
V
nQx[c]  
a. VCCOx denotes VCCOA and VCCOB  
b. Outputs terminated with 50to VCCOx – 2V when VCCOx = 3.3V±5% or 2.5V±5%. Outputs terminated with 50to ground when  
CCOx = 1.8V±5%.  
.
V
c. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3.  
Table 18: LVDS DC Characteristics, VCC = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%,  
V
CCOA = VCCOB = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, TA = -40°C to +85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VOD  
VOD  
VOS  
Differential output voltage  
VOD magnitude change  
Offset voltage  
Qx, nQx[a]  
Qx, nQx[a]  
Qx, nQx[a]  
Qx, nQx[a]  
247  
480  
50  
mV  
mV  
V
Terminated 100across  
Qx and nQx  
1.125  
1.375  
50  
VOS  
VOS magnitude change  
mV  
a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3.  
Table 19: CML (400mV Swing) DC Characteristics, VCC = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%,  
V
CCOA = VCCOB = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, TA = -40°C to +85°C  
Symbol  
Parameter  
Output high voltage  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
[b]  
VOH  
VOL  
Qx, nQx[a]  
Qx, nQx[a]  
Qx, nQx[a]  
VCCOx[b] – 0.10  
VCCOx[b] – 0.50  
300  
VCCOx  
V
V
Terminated with 50to  
Output low voltage  
VCCOx[b] – 0.30  
[b]  
VCCOx  
VOUT  
Output voltage swing  
500  
mV  
a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3.  
b. VCCOx denotes VCCOA and VCCOB  
.
Table 20: CML (800mV Swing) DC Characteristics, VCC = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, VCCOA = VCCOB  
3.3V ±5%, 2.5V ±5% or 1.8V ±5%, TA = -40°C to +85°C  
=
Symbol  
Parameter  
Output high voltage  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VOH  
VOL  
Qx, nQx[a]  
Qx, nQx[a]  
Qx, nQx[a]  
VCCOx[b] – 0.10  
VCCOx[b] – 0.95  
575  
VCCOx  
VCCOx[b] – 0.70  
1000  
V
V
Terminated with 50to  
Output low voltage  
[b]  
VCCOx  
VOUT  
Output voltage swing  
mV  
a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3.  
b. VCCOx denotes VCCOA and VCCOB  
.
©2016 Integrated Device Technology, Inc.  
20  
December 19, 2016  
8P79818 Datasheet  
Table 21: LVCMOS Clock Outputs DC Characteristics, VCC = 3.3V±5%, 2.5V±5% or 1.8V±5%, VEE = 0V,  
TA = -40°C to +85°C  
VCCOA = 3.3V±5% VCCOA = 2.5V±5% VCCOA = 1.8V ±5% VCCOA = 1.5V ±5%  
Conditions Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units  
Test  
Symbol  
Parameter  
Output high voltage  
QAx, nQAx[a]  
VOH  
I
OH = –8mA  
2.6  
1.1  
1.1  
1.1  
V
V
Output low voltage  
QAx, nQAx[a]  
VOL  
IOL = 8mA  
0.5  
0.5  
0.5  
0.5  
a. QAm denotes QA0, QA1, QA2, QA3. nQAm denotes nQA0, nQA1, nQA2, nQA3.  
Table 22: Input Frequency Characteristics, VCC = 3.3V±5%, 2.5V±5% or 1.8V±5%, TA = -40°C to +85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
LVPECL,LVDS,  
HCSL, CML  
1PPS  
1PPS  
700MHz  
200MHz  
Input frequency,  
CLKx, nCLKx  
fIN  
LVCMOS  
idc  
Input duty cycle[a]  
50  
%
2
I C operation  
100  
400  
50  
kHz  
MHz  
fSCLK  
Serial port clock SCLK  
SPI operation  
a. Any deviation from a 50% duty cycle on the input may be reflected in the output duty cycle.  
©2016 Integrated Device Technology, Inc.  
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December 19, 2016  
8P79818 Datasheet  
AC Electrical Characteristics  
Table 23: AC Characteristics, VCC = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%,  
V
CCOA = VCCOB = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, TA = -40°C to +85°C  
Symbol  
Parameter[a]  
LVPECL, LVDS  
Test Conditions  
Minimum Typical Maximum Units  
1PPS  
700MHz  
fOUT  
Output frequency  
HCSL, CML[b]  
LVCMOS  
1PPS  
125  
200MHz  
700  
LVPECL  
20% to 80%  
ps  
ps  
VCCOx[c] = 3.3V 20% to 80%  
VCCOx[c] = 2.5V 20% to 80%  
VCCOx[c] = 1.8V 20% to 80%  
20% to 80%  
125  
550  
LVDS  
175  
100  
125  
550  
675  
825  
ps  
ps  
ps  
CML, 400mV  
CML, 800mV  
Output rise and fall  
times  
tR / tF  
20% to 80%  
V
CCOA = 3.3V  
VCCOA = 2.5V  
CCOA = 1.8V  
20% to 80%  
20% to 80%  
20% to 80%  
20% to 80%  
200  
800  
ps  
LVCMOS  
V
VCCOA = 1.5V  
650  
15  
20  
10  
10  
50  
1300  
50  
ps  
ps  
ps  
ps  
ps  
ps  
LVPECL  
LVDS  
Bank skew[d], [e], [f] CML  
60  
tsk(b)  
35  
HCSL  
35  
LVCMOS  
100  
LVPECL,LVDS,  
HCSL, CML  
Even divide ratios  
45  
50  
55  
%
LVPECL,LVDS,  
HCSL, CML  
Odd divide ratios / bypass  
43  
45  
40  
40  
38  
50  
50  
50  
50  
50  
57  
55  
60  
60  
62  
%
%
%
%
%
Even divide ratios  
Output  
odc  
VCCOA = 3.3V,  
2.5V, or 1.8V  
duty cycle[g]  
LVCMOS  
LVCMOS  
Odd divide ratios /  
bypass  
Even divide ratios  
VCCOA = 1.5V  
Odd divide ratios /  
bypass  
MUXISOL Mux isolation  
Noise floor  
156.25MHz, VSWING = 800mV  
61  
dB  
Offset >10MHz from156.25MHz carrier  
–154  
dBc/Hz  
a. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
b. CML denotes CML 400mV and CML 800mV, unless otherwise stated.  
c. VCCOx denotes VCCOA and VCCOB  
.
©2016 Integrated Device Technology, Inc.  
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December 19, 2016  
8P79818 Datasheet  
d. This parameter is guaranteed by characterization. Not tested in production.  
e. This parameter is defined in accordance with JEDEC Standard 65.  
f. Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.  
g. Measured using 50% duty cycle on input reference.  
Table 24: HCSL AC Characteristics, VCC = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%,  
V
CCOA = VCCOB = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, TA = -40°C to +85°C  
Symbol  
Parameter[a]  
Rise/ fall edge rate[c]  
Test Conditions[b]  
Minimum  
Typical  
Maximum  
Units  
V
V
CCOx = 3.3V or 2.5V  
CCOx = 1.8V  
0.6  
4
4
V/ns  
V/ns  
mV  
tSLEW  
0.45  
VMAX  
VMIN  
Absolute max. output voltage[d], [e]  
Absolute min. output voltage[d], [f]  
Absolute crossing voltage[g], [h]  
VCCOx = 3.3V, 2.5V, 1.8V  
VCCOx = 3.3V, 2.5V, 1.8V  
1150  
–150  
mV  
VCROSS  
V
V
CCOx = 3.3V, 2.5V, 1.8V  
CCOx = 3.3V, 2.5V, 1.8V  
550  
140  
mV  
VCROSS Total variation of VCROSS over all edges[g], [i]  
mV  
a. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal  
equilibrium has been reached under these conditions.  
b. VCCOx denotes VCCOA and VCCOB  
.
c. Measured from –150mV to 150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic through the  
measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.  
d. Measurement taken from single ended waveform.  
e. Defined as the maximum instantaneous voltage including overshoot.  
f. Defined as the minimum instantaneous voltage including undershoot.  
g. Measured at crossing point where the instantaneous voltage value of the rising edge of Qm equals the falling edge of nQm.  
h. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points  
for this measurement.  
i. Defined as the total variation of all crossing voltages of rising Qm and falling nQm, This is the maximum allowed variance in VCROSS for any  
particular system.  
©2016 Integrated Device Technology, Inc.  
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December 19, 2016  
8P79818 Datasheet  
Table 25: Additive Jitter, VCC = 3.3V, 2.5V or 1.8V, VCCOA = VCCOB = 3.3V, 2.5V, 1.8V or 1.5V  
(1.5V only supported for LVCMOS outputs), TA = 25°C  
Symbol  
Parameter  
Test Conditions[a]  
Minimum  
Typical  
Maximum  
Units  
VCCOx[b] = 3.3V or 2.5V  
VCCOx[b] = 1.8V  
VCCOx[b] = 3.3V or 2.5V  
VCCOx[b] = 1.8V  
VCCOx[b] = 3.3V or 2.5V  
VCCOx[b] = 1.8V  
VCCOx[b] = 3.3V or 2.5V  
VCCOx[b] = 1.8V  
VCCOx[b] = 3.3V or 2.5V  
VCCOx[b] = 1.8V  
VCCOx[b] = 3.3V or 2.5V  
VCCOx[b] = 1.8V  
77  
90  
92  
117  
60  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fOUT  
156.25MHz  
=
LVPECL  
LVDS  
50  
fOUT  
625MHz  
=
60  
84  
85  
104  
185  
61  
fOUT  
156.25MHz  
=
126  
48  
RMS additive jitter  
(random);  
fOUT  
625MHz  
=
tjit(f)  
57  
84  
Integration range:  
12kHz – 20MHz  
92  
132  
133  
73  
fOUT  
156.25MHz  
=
92  
HCSL  
61  
fOUT  
625MHz  
=
67  
93  
V
V
CCOA = 3.3V or 2.5V  
CCOA = 1.8V  
98  
166  
204  
314  
fOUT  
156.25MHz  
=
LVCMOS  
128  
198  
VCCOA = 1.5V  
a. All outputs configured for the specific output type, as shown in the table.  
b. VCCOx denotes VCCOA and VCCOB  
.
©2016 Integrated Device Technology, Inc.  
24  
December 19, 2016  
8P79818 Datasheet  
Applications Information  
Recommendations for Unused Input and Output Pins  
Inputs:  
CLK/nCLK Inputs  
For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional  
protection, a 1kresistor can be tied from CLK to ground.  
LVCMOS Control Pins  
All control pins have internal pullups and pulldowns; additional resistance is not required but can be added for additional protection. A 1k  
resistor can be used.  
Outputs:  
LVCMOS Outputs  
All unused LVCMOS outputs can be left floating. It is recommended that there is no trace attached.  
LVPECL Outputs  
All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should  
either be left floating or terminated.  
LVDS Outputs  
All unused LVDS output pairs can be either left floating or terminated with 100across. If they are left floating, there should be no trace  
attached.  
Differential Outputs  
All unused Differential outputs can be left floating. It is recommended that there is no trace attached.  
Power Dissipation and Thermal Considerations  
The 8P79818 is a multi-functional, high speed device that targets a wide variety of clock frequencies and applications. Since this device is  
highly programmable with a broad range of features and functionality, the power consumption will vary as each of these features and functions  
is enabled.  
The 8P79818 device was designed and characterized to operate within the ambient industrial temperature range of -40°C to +85°C. The  
ambient temperature represents the temperature around the device, not the junction temperature. When using the device in extreme cases,  
such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe and reliable  
junction temperature. Extreme care must be taken to avoid exceeding 125°C junction temperature.  
The power calculation examples below were generated using a maximum ambient temperature and supply voltage. For many applications, the  
power consumption will be much lower. Please contact IDT technical support for any concerns on calculating the power dissipation for your  
own specific configuration.  
©2016 Integrated Device Technology, Inc.  
25  
December 19, 2016  
8P79818 Datasheet  
Power Domains  
The 8P79818 device has a number of separate power domains that can be independently enabled and disabled via register accesses (all  
power supply pins must still be connected to a valid supply voltage). Figure 7 below indicates the individual domains and the associated power  
pins.  
Figure 7: 8P79818 Power Domains  
©2016 Integrated Device Technology, Inc.  
26  
December 19, 2016  
8P79818 Datasheet  
Power Consumption Calculation  
Determining total power consumption involves several steps:  
1.Determine the power consumption using maximum current values for core voltage from Table 11, Table 12 and Table 13, Page 18 for the  
appropriate case of how many dividers are enabled.  
2.Determine the nominal power consumption of each enabled output path.  
a. This consists of a base amount of power that is independent of operating frequency, as shown in Table 27 through Table 43 (depending  
on the chosen output protocol).  
b. Then there is a variable amount of power that is related to the output frequency. This can be determined by multiplying the output  
frequency by the FQ_Factor shown in Table 27 through Table 43.  
3.All of the above totals are then summed.  
Example Calculations  
Table 26: Example 1. Common Customer Configuration (3.3V Core Voltage)  
Bank  
Configuration  
Frequency (MHz)  
VCCO  
Bank A  
Bank B  
LVDS  
LVDS  
125  
125  
3.3V  
2.5V  
▪ Core supply current, ICC = 24.7mA (max.)  
▪ Output supply current, Bank A = 0.06 125 71.615 = 79.115mA  
▪ Output supply current, Bank B = 0.06 125 71.615 = 79.115mA  
▪ Total device current = 24.7mA + 79.115mA 79.115mA = 182.93mA  
▪ Total device power = 3.465V 183.93mA = 633.934mW  
With an ambient temperature of 85°C and no airflow, the junction temperature is:  
TJ = 85°C 35.23°C/W 0.634W = 107.3°C  
©2016 Integrated Device Technology, Inc.  
27  
December 19, 2016  
8P79818 Datasheet  
Thermal Considerations  
Once the total power consumption has been determined, it is necessary to calculate the maximum operating junction temperature for the device  
under the environmental conditions it will operate in. Thermal conduction paths, air flow rate and ambient air temperature are factors that can  
affect this. The thermal conduction path refers to whether heat is to be conducted away via a heat-sink, via airflow or via conduction into the  
PCB through the device pads (including the ePAD). Thermal conduction data is provided for typical scenarios in Table 44, Page 30. Please  
contact IDT for assistance in calculating results under other scenarios.  
Current Consumption Data and Equations  
Table 27: 3.3V LVDS Output Calculation Table  
Table 30: 3.3V LVPECL Output Calculation Table  
FQ_Factor (mA/MHz),  
FQ_Factor (mA/MHz),  
LVDS  
per output  
Base_Current (mA)  
LVPECL  
per output  
Base_Current (mA)  
Qx, nQx[a]  
0.06  
71.615  
Qx, nQx[a]  
0.05  
53.475  
a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.  
nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2,  
nQB3.  
a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.  
nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2,  
nQB3.  
Table 28: 2.5V LVDS Output Calculation Table  
Table 31: 2.5V LVPECL Output Calculation Table  
FQ_Factor (mA/MHz),  
FQ_Factor (mA/MHz),  
LVDS  
per output  
Base_Current (mA)  
LVPECL  
per output  
Base_Current (mA)  
Qx, nQx[a]  
0.06  
71.544  
Qx, nQx[a]  
0.04  
20.874  
a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.  
nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2,  
nQB3.  
a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.  
nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2,  
nQB3.  
Table 29: 1.8V LVDS Output Calculation Table  
Table 32: 1.8V LVPECL Output Calculation Table  
FQ_Factor (mA/MHz),  
FQ_Factor (mA/MHz),  
LVDS  
per output  
Base_Current (mA)  
LVPECL  
per output  
Base_Current (mA)  
Qx, nQx[a]  
0.1  
50.284  
Qx, nQx[a]  
0.04  
19.962  
a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.  
nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2,  
nQB3.  
a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.  
nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2,  
nQB3.  
Table 33: 3.3V HCSL Output Calculation Table  
FQ_Factor (mA/MHz),  
HCSL  
per output  
Base_Current (mA)  
Qx, nQx[a]  
0.05  
54.911  
a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.  
nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2,  
nQB3.  
©2016 Integrated Device Technology, Inc.  
28  
December 19, 2016  
8P79818 Datasheet  
Table 34: 3.3V CML Output (400mV) Calculation  
Table  
Table 39: 1.8V CML Output (800mV) Calculation  
Table  
FQ_Factor (mA/MHz),  
FQ_Factor (mA/MHz),  
per output  
CML  
per output  
Base_Current (mA)  
CML  
Qx, nQx[a]  
Base_Current (mA)  
Qx, nQx[a]  
0.03  
51.889  
0.02  
47.334  
a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.  
nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2,  
nQB3.  
a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.  
nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2,  
nQB3.  
Table 35: 2.5V CML Output (400mV) Calculation  
Table  
Table 40: 3.3V LVCMOS Output Calculation Table  
LVCMOS  
Base_Current (mA)  
FQ_Factor (mA/MHz),  
Qx, nQx[a]  
62.289  
CML  
per output  
Base_Current (mA)  
Qx, nQx[a]  
0.02  
49.220  
a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.  
nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2,  
nQB3.  
a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.  
nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2,  
nQB3.  
Table 41: 2.5V LVCMOS Output Calculation Table  
Table 36: 1.8V CML Output (400mV) Calculation  
Table  
LVCMOS  
Base_Current (mA)  
Qx, nQx[a]  
51.097  
FQ_Factor (mA/MHz),  
a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.  
nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2,  
nQB3.  
CML  
per output  
Base_Current (mA)  
Qx, nQx[a]  
0.02  
47.326  
a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.  
nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2,  
nQB3.  
Table 42: 1.8V LVCMOS Output Calculation Table  
LVCMOS  
Base_Current (mA)  
Qx, nQx[a]  
47.745  
Table 37: 3.3V CML Output (800mV) Calculation  
Table  
a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.  
nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2,  
nQB3.  
FQ_Factor (mA/MHz),  
CML  
per output  
Base_Current (mA)  
Qx, nQx[a]  
0.02  
51.474  
Table 43: 1.5V LVCMOS Output Calculation Table  
a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.  
nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2,  
nQB3.  
LVCMOS  
Base_Current (mA)  
Qx, nQx[a]  
41.485  
a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.  
nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2,  
nQB3.  
Table 38: 2.5V CML Output (800mV) Calculation  
Table  
FQ_Factor (mA/MHz),  
CML  
per output  
Base_Current (mA)  
Qx, nQx[a]  
0.02  
48.906  
a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.  
nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2,  
nQB3.  
©2016 Integrated Device Technology, Inc.  
29  
December 19, 2016  
8P79818 Datasheet  
Applying the values to the following equation will yield output current by frequency: (mA) = FQ_Factor Frequency (MHz) Base_Current  
where:  
Qx Current is the specific output current according to output type and frequency  
FQ_Factor is used for calculating current increase due to output frequency  
Base_Current is the base current for each output path independent of output frequency  
The second step is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient, using the following  
equation:  
TJ = TA (JA Pdtotal  
)
where:  
TJ is the junction temperature (°C)  
TA is the ambient temperature (°C)  
JA is the thermal resistance value from Table 44, Page 30, dependent on ambient airflow (°C/W)  
Pdtotal is the total power dissipation of the 8P79818 under usage conditions, including power dissipated due to loading (W)  
Note that for LVPECL outputs the power dissipation through the load is assumed to be 27.95mW. When selecting LVCMOS outputs, power  
dissipation through the load will vary based on a variety of factors including termination type and trace length. For these examples, power  
dissipation through loading will be calculated using CPD (found in Table 10, Page 16) and output frequency:  
2
PdOUT = CPD fOUT VCCO  
where:  
Pdout is the power dissipation of the output (W)  
C
PD is the power dissipation capacitance (pF)  
OUT is the output frequency of the selected output (MHz)  
CCO is the voltage supplied to the appropriate output (V)  
f
V
Table 44: JA vs. Air Flow Table for a 32-lead 5mm x 5mm VFQFN  
JA vs. Air Flow  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
35.23°C/W  
31.6°C/W  
30.0°C/W  
©2016 Integrated Device Technology, Inc.  
30  
December 19, 2016  
8P79818 Datasheet  
Package Drawings  
Figure 8: Package Drawings  
©2016 Integrated Device Technology, Inc.  
31  
December 19, 2016  
8P79818 Datasheet  
Figure 9: Package Drawings (Continued)  
©2016 Integrated Device Technology, Inc.  
32  
December 19, 2016  
8P79818 Datasheet  
Marking Diagram  
1. Line 1 is the prefix of the part number.  
2. Line 2 and Line 3 is the part number.  
3. Line 4 “YYWW$”  
a. “YY” are the last digits of the year and “WW” is the work week that the part was assembled.  
b. “$” denotes mark code.  
Ordering Information  
Table 45: Ordering Information  
Part/Order Number  
Marking  
Package  
Shipping Packaging  
Temperature  
8P79818NLGI  
8P79818NLGI8  
8P79818NLGI/W  
IDT8P79818NLGI  
IDT8P79818NLGI  
IDT8P79818NLGI  
32-lead VFQFN, Lead Free  
32-lead VFQFN, Lead Free  
32-lead VFQFN, Lead Free  
Tray  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
Tape & Reel  
Tape & Reel  
Table 46: Pin 1 Orientation in Tape and Reel Packaging  
Part Number Suffix  
Pin 1 Orientation  
Illustration  
CARRIER TAPE TOPSIDE  
(Round Sprocket Holes)  
Correct Pin 1 ORIENTATION  
NLGI8  
Quadrant 1 (EIA-481-C)  
USER DIRECTION OF FEED  
CARRIER TAPE TOPSIDE  
(Round Sprocket Holes)  
Correct Pin 1 ORIENTATION  
NLGI/W  
Quadrant 2 (EIA-481-D)  
USER DIRECTION OF FEED  
©2016 Integrated Device Technology, Inc.  
33  
December 19, 2016  
8P79818 Datasheet  
Revision History  
Revision Date  
Description of Change  
December 19, 2016  
Initial datasheet.  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
www.IDT.com/go/support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance spec-  
ifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information  
contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied  
warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of  
IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-  
sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property  
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.  
©2016 Integrated Device Technology, Inc  
34  
December 19, 2016  
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