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8P73S674

型号：

8P73S674

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

15 页

PDF大小：

281 K

下载PDF手册
1.8V LVPECL Clock Divider  
8P73S674  
DATA SHEET  
General Description  
Features  
The 8P73S674 is a 1.8V LVPECL Clock Divider and Fanout Buffer.  
The device has been designed for clock signal division and fanout in  
wireless base station (radio and base band), high-end computing and  
telecommunication equipment. The device is optimized to deliver  
excellent phase noise performance. The 8P73S674 uses SiGe  
technology for an optimum of high clock frequency and low phase  
noise performance, combined with high power supply noise rejection.  
The device offers the frequency division by ÷1, ÷2, ÷4 and ÷8. Four  
low-skew 1.8V LVPECL outputs are available for and support clock  
output frequencies up to 1GHz (÷1 frequency division). 1.8V LVPECL  
• Clock signal division and distribution  
• SiGe technology for high-frequency and fast signal rise/fall times  
• Four low-skew LVPECL clock outputs  
• Supports frequency division of ÷1, ÷2, ÷4 and ÷8  
• Maximum Output frequency: 1GHz  
• Output skew: 100ps (maximum)  
• LVPECL output rise/fall time (20% - 80%): 220ps (maximum)  
• 1.8V core and output supply mode  
outputs are terminated 50to GND. Outputs can be disabled to save  
power consumption if not used. The device is packaged in a lead-free  
(RoHS 6) 20-lead VFQFN package. The extended temperature range  
supports wireless infrastructure, telecommunication and networking  
end equipment requirements. The device is a member of the  
high-performance clock family from IDT.  
• Supports 1.8V I/O LVCMOS logic levels for all control pins  
• -40°C to +85°C ambient operating temperature  
• Lead-free (RoHS 6) 20-lead VFQFN packaging  
Block Diagram  
Pin Assignment  
Q0  
nQ0  
IN  
nIN  
÷N  
19  
18  
17  
20  
16  
1
2
3
4
5
15  
14  
13  
12  
11  
nIN  
NC  
VT  
IN  
nQ1  
Q1  
2x 50  
Q1  
nQ1  
VT  
N[1:0]  
8P73S674  
nQ2  
Q2  
Q2  
nQ2  
nOEA  
nOEB  
Q3  
nQ3  
N0  
VCC  
6
7
8
9
10  
20-pin, 2.15mm x 2.15mm, EPad, VFQFN Package  
8P73S674 REVISION 1 12/17/14  
1
©2014 Integrated Device Technology, Inc.  
8P73S674 DATA SHEET  
Pin Descriptions and Characteristics  
Table 1. Pin Descriptions  
Number  
Name  
nIN  
NC  
Type  
Description  
1
2
3
4
5
6
7
Input  
Unused  
—
—
—
Clock signal inverting differential input. Internal termination 50to VT.  
Not connected.  
VT  
—
Leave open if IN, nIN is used with LVDS signals.  
Clock signal non-inverting differential input. Internal termination 50to VT.  
Frequency divider control. 1.8V LVCMOS/LVTTL interface levels.  
Power supply ground.  
IN  
Input  
Input  
Power  
Input  
—
N0  
Pulldown  
—
GND  
N1  
Pulldown  
Frequency divider control. 1.8V LVCMOS/LVTTL interface levels.  
Output enable control for the Q1, Q2 and Q3 outputs.   
1.8V LVCMOS/LVTTL interface levels.  
8
nOEB  
Input  
Pulldown  
9
nQ3  
Q3  
Output  
Output  
Power  
Output  
Output  
Output  
Output  
Power  
Output  
Output  
—
—
—
—
—
—
—
—
—
—
Differential clock output 3. 1.8V LVPECL output levels.  
Supply voltage for the clock outputs.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
VCC  
Q2  
Differential clock output 2. 1.8V LVPECL output levels.  
nQ2  
Q1  
Differential clock output 1. 1.8V LVPECL output levels.  
Supply voltage for the clock outputs.  
nQ1  
VCC  
Q0  
Differential clock output 0. 1.8V LVPECL output levels.  
nQ0  
Output enable control for the Q0 output.   
1.8V LVCMOS/LVTTL interface levels.  
19  
20  
nOEA  
GND  
Input  
Power  
Power  
Pulldown  
—
—
Power supply ground.  
Exposed package pad negative supply voltage (GND).   
Return current path for the Q0, Q1, Q2 and Q3 outputs.  
EPAD  
GND_EP  
Table 2. Pin Characteristics  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
pF  
Input Capacitance  
4
RPULLDOWN  
Input Pulldown Resistor  
51  
k  
1.8V LVPECL CLOCK DIVIDER  
2
REVISION 1 12/17/14  
8P73S674 DATA SHEET  
Truth Tables  
Table 3A. N Clock Divider  
Input  
N1  
N0  
Divider Value  
0 (default)  
0 (default)  
÷1  
÷2  
÷4  
÷8  
0
1
1
1
0
1
Table 3B. nOEA Output Enable  
Input  
nOEA  
Output  
Q0  
0 (default)  
Output is enabled  
Output is disabled in logic low state  
1
Table 3C. nOEB Output Enable  
Input  
Output  
nOEB  
Q1, Q2, Q3  
0 (default)  
1
Outputs are enabled  
Outputs are disabled in logic low state  
REVISION 1 12/17/14  
3
1.8V LVPECL CLOCK DIVIDER  
8P73S674 DATA SHEET  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress  
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Electrical Characteristics  
or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability  
.
Item  
Rating  
Supply Voltage, VCC  
Inputs  
4.6V  
-0.5V to VCC + 0.5V  
30mA  
Input Current, IN, nIN  
VT Current, IVT  
60mA  
Outputs, IO (LVPECL)  
Continuous Current  
Surge Current  
50mA  
100mA  
Junction Temperature  
125C  
Storage Temperature, TSTG  
-65C to 150C  
DC Electrical Characteristics  
Table 4A. Power Supply DC Characteristics, V = 1.8V 0.15V, T = -40°C to +85°C  
CC  
A
Symbol  
VCC  
Parameter  
Test Conditions  
Minimum  
Typical  
1.8  
Maximum  
1.95  
Units  
V
Core Supply Voltage  
Power Supply Current  
1.65  
ICC  
Outputs Unloaded  
62  
73  
mA  
Table 4B. LVCMOS/LVTTL DC Characteristics, V = 1.8V 0.15V, T = -40°C to +85°C  
CC  
A
Symbol  
VIH  
Parameter  
Test Conditions  
Minimum  
1.2  
Typical  
Maximum  
1.8  
Units  
Input High Voltage  
Input Low Voltage  
V
V
VIL  
-0.3  
0.3  
Input High  
Current  
N0, N1,  
nOEA, nOEB  
IIH  
IIL  
V
CC = 1.95V, VIN = 1.95V  
150  
µA  
µA  
Input Low  
Current  
N0, N1,  
nOEA, nOEB  
VCC = 1.95V, VIN = 0V  
-10  
Table 4C. Differential Input DC Characteristics, V = 1.8V 0.15V, T = -40°C to +85°C  
CC  
A
Symbol  
RIN  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
130  
Units  
Differential Input  
Resistance  
IN, nIN  
IN, nIN  
Across IN and nIN with VT floated  
70  
100  
IIN  
Input Current  
25  
mA  
1.8V LVPECL CLOCK DIVIDER  
4
REVISION 1 12/17/14  
8P73S674 DATA SHEET  
Table 4D. LVPECL DC Characteristics, V = 1.8V 0.15V, T = -40°C to +85°C  
CC  
A
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
VCC – 0.75  
VCC – 1.5  
Units  
VOH  
VOL  
Output High Voltage1  
Output Low Voltage1  
VCC – 1.1  
V
V
Peak-to-Peak Output   
VSWING  
0.6  
1.0  
V
Voltage Swing1  
NOTE 1: Outputs terminated with 50to GND.  
AC Electrical Characteristics  
1 2  
,
Table 5. AC Characteristics, V = 1.8V 0.15V, T = -40°C to +85°C  
CC  
A
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VPP  
Input Voltage Swing  
IN, nIN  
0.2  
1
V
Differential Input  
Voltage Swing  
VDIFF_IN  
IN, nIN  
IN, nIN  
0.4  
0.9  
2
V
V
Common Mode Input  
Voltage3  
VCMR  
V
CC –VPP/2  
N = ÷1  
N = ÷2  
N = ÷4  
N = ÷8  
1000  
500  
250  
125  
1000  
100  
600  
900  
500  
410  
220  
MHz  
MHz  
MHz  
MHz  
MHz  
ps  
fOUT  
Output Frequency, Q[3:0]  
fIN  
Input Frequency, IN, nIN  
Output Skew4, 5  
tsk(o)  
40  
N = ÷1  
200  
400  
ps  
tPD  
Propagation Delay  
N = ÷2, ÷4, ÷8  
ps  
tsk(pp)  
tR / tF  
Part-to-Part Skew4, 6  
ps  
10%-90%  
20%-80%  
270  
150  
ps  
Output  
Rise/Fall Time  
ps  
Phase Jitter Noise Floor, >100kHz  
offset7  
tjit(Ø)  
any Q, fOUT = 1000MHz  
-153  
dBc/Hz  
122.88 MHz; 1kHz-40MHz  
122.88 MHz; 12kHz-20MHz  
50% Input Duty Cycle  
100  
60  
180  
120  
55  
fs  
fs  
%
tjit(Ø)  
Additive Phase Noise, RMS  
Output Duty Cycle  
odc  
45  
50  
NOTE 1: Outputs terminated with 50to GND.  
NOTE 2: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the  
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after  
thermal equilibrium has been reached under these conditions.  
NOTE 3: Common mode input voltage is defined as the signal crosspoint.  
NOTE 4: This parameter is defined in accordance with JEDEC standard 65.  
NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential  
crosspoints.  
NOTE 6: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency  
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the output differential  
crosspoints.  
NOTE 7: VCMR is set to 1.12V.  
REVISION 1 12/17/14  
5
1.8V LVPECL CLOCK DIVIDER  
8P73S674 DATA SHEET  
Parameter Measurement Information  
1.8V 0.15V  
V
CC  
SCOPE  
V
CC  
Qx  
nIN  
IN  
nQx  
GND  
V
EE  
1.8V LVPECL Output Load Test Circuit  
Differential Input Level  
Part 1  
nQx  
nQx  
Qx  
Qx  
Part 2  
nQy  
nQy  
Qy  
Qy  
tsk(pp)  
Output Skew  
Part-to-Part Skew  
nQ[0:3]  
Q[0:3]  
nQ[0:3]  
Q[0:3]  
Output Rise/Fall Time  
Output Duty Cycle/Pulse Width/Period  
1.8V LVPECL CLOCK DIVIDER  
6
REVISION 1 12/17/14  
8P73S674 DATA SHEET  
Applications Information  
Recommendations for Unused Output Pins  
Inputs:  
Outputs:  
LVCMOS Control Pins  
LVPECL Outputs  
All unused LVPECL output pairs can be left floating. We recommend  
that there is no trace attached. Both sides of the differential output  
pair should either be left floating or terminated.  
All control pins have internal pulldowns; additional resistance is not  
required but can be added for additional protection. A 1kresistor  
can be used.  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 1. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally/  
Electrically Enhance Leadframe Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
SOLDER  
SOLDER  
PIN  
PIN  
EXPOSED HEAT SLUG  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 1. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
REVISION 1 12/17/14  
7
1.8V LVPECL CLOCK DIVIDER  
8P73S674 DATA SHEET  
1.8V Differential Clock Input Interface  
The IN /nIN accepts LVDS and other differential signals. The  
differential input signal must meet both the VPP and VCMR input  
requirements. Figure 2A to Figure 2C show interface examples for  
the IN /nIN input driven by the most common driver types. The input  
interfaces suggested here are examples only. If the driver is from  
another vendor, use their termination recommendation. Please  
consult with the vendor of the driver component to confirm the driver  
termination requirements.  
2.5V, 1.8V  
1.8V  
3.3V, 2.5V, 1.8V  
1.8V  
Zo = 50  
Zo = 50  
Zo = 50  
Zo = 50  
IN  
IN  
VT  
nIN  
VT  
nIN  
Receiver  
Receiver  
LVPECL  
LVDS  
Figure 2A. Differential Input Driven by an LVDS Driver  
Figure 2C. Differential Input Driven by an LVPECL Driver  
1.8V  
1.8V  
Zo = 50  
Zo = 50  
IN  
VT  
nIN  
Receiver  
CML  
Figure 2B. Differential Input Driven by a CML Driver  
1.8V LVPECL CLOCK DIVIDER  
8
REVISION 1 12/17/14  
8P73S674 DATA SHEET  
Power Considerations  
This section provides information on power dissipation and junction temperature for the 8P73S674.   
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the 8P73S674 is the sum of the core power plus the power dissipated due to loading.   
The following is the power dissipation for VCC = 1.8V + 0.15V = 1.95V, which gives worst case results.  
The following calculation is for 85°C. The maximum current at 85°C is 68.3mA.  
NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.  
•
•
Power (core)MAX = VCC_MAX * ICC_MAX = 1.95V * 68.3mA = 133.2mW  
Power (outputs)MAX = 31.5mW/Loaded Output pair  
If all outputs are loaded, the total power is 4 * 31.5mW = 126mW  
•
Power Dissipation for internal termination RT  
Power (RT)MAX = 2 * [(IIN_MAX)2 * 50] = 2 * (25mA)2 * 50= 62.5mW  
Total Power_MAX = Power (core)MAX + Power (outputs)MAX + Power (RT)MAX = 133.2+ 126mW + 62.5mW = 321.7mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and it directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 62.2°C/W per Table 6 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.322W * 70.7°C/W = 108°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 6. Thermal Resistance for 20-Lead VFQFN, Forced Convection  
JA  
JA by Velocity  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
70.7°C/W  
67.0°C/W  
65.3°C/W  
REVISION 1 12/17/14  
9
1.8V LVPECL CLOCK DIVIDER  
8P73S674 DATA SHEET  
3. Calculations and Equations.  
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.  
LVPECL output driver circuit and termination are shown in Figure 3.  
VCC  
Q1  
VOUT  
RL  
Figure 3. LVPECL Driver Circuit and Termination  
To calculate power dissipation due to loading, use the following equations which assume a 50load.  
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.75V  
(VCC_MAX – VOH_MAX) = 0.75V  
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.5V  
(VCC_MAX – VOL_MAX) = 1.5V  
Pd_H is power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
Pd_H = [(VOH_MAX)/RL] * (VCC_MAX – VOH_MAX)   
= [(VCC_MAX – 0.75)/RL] * (VCC_MAX – VOH_MAX)   
= [(1.95V – 0.75V)/50] * 0.75V = 18mW  
Pd_L = [(VOL_MAX)/RL] * (VCC_MAX – VOL_MAX)   
= [(VCC_MAX – 1.5v)/RL] * (VCC_MAX – VOL_MAX)   
= [(1.95V – 1.5V)/50] * 1.5V = 13.5mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 31.5mW  
1.8V LVPECL CLOCK DIVIDER  
10  
REVISION 1 12/17/14  
8P73S674 DATA SHEET  
Reliability Information  
Table 7. vs. Air Flow Table for a 20-Lead VFQFN  
JA  
JA at 0 Air Flow  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
70.7°C/W  
67.0°C/W  
65.3°C/W  
Transistor Count  
The transistor count for the 8P73S674 is: 1,238  
REVISION 1 12/17/14  
11  
1.8V LVPECL CLOCK DIVIDER  
8P73S674 DATA SHEET  
Package Information  
1.8V LVPECL CLOCK DIVIDER  
12  
REVISION 1 12/17/14  
8P73S674 DATA SHEET  
Ordering Information  
Table 8. Ordering Information  
Part/Order Number  
Marking  
Package  
Shipping Packaging  
Tray  
Temperature  
-40°C to +85°C  
-40°C to +85°C  
8P73S674NLGI  
8P73S674NLGI8  
8P73S674NLGI  
8P73S674NLGI  
20-Lead VFQFN, Lead-Free  
20-Lead VFQFN, Lead-Free  
Tape & Reel  
REVISION 1 12/17/14  
13  
1.8V LVPECL CLOCK DIVIDER  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
Sales  
Tech Support  
email: clocks@idt.com  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in  
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined  
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether  
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This  
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or  
other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as  
those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any  
circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected  
names, logos and designs, are the property of IDT or their respective third party owners.  
Copyright ©2014 Integrated Device Technology, Inc.. All rights reserved.  
8P73S674 DATA SHEET  
REVISION 1 12/17/14  
15  
1.8V LVPECL CLOCK DIVIDER  
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IDT

 		8P791208NLGI [ Low Additive Jitter 2:8 Buffer with CMOS/ Differential Outputs ] 32 页

IDT

 		8P791208NLGI/W [ Low Additive Jitter 2:8 Buffer with CMOS/ Differential Outputs ] 32 页

IDT

 		8P791208NLGI8 [ Low Additive Jitter 2:8 Buffer with CMOS/ Differential Outputs ] 32 页

IDT

 		8P791208_18 [ Low Addit ive Jit ter 2:8 Buffer with CMOS / Different ial Outputs ] 31 页

IDT

 		8P79818 [ Programmable Low Additive Jitter 2:8 Buffer with Dividers and Universal Outputs ] 34 页

IDT

 		8P79818NLGI [ Programmable Low Additive Jitter 2:8 Buffer with Dividers and Universal Outputs ] 34 页

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