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8P791208NLGI/W

型号：

8P791208NLGI/W

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

32 页

PDF大小：

817 K

下载PDF手册
Low Additive Jitter 2:8 Buffer with  
8P791208  
CMOS/ Differential Outputs  
Datasheet  
General Description  
The 8P791208 is a low additive jitter 2:8 buffer with CMOS/  
differential outputs The device takes one or two reference clocks,  
selects between them using a pin selection, and generates up to  
eight outputs that are the same as the reference frequency.  
Features  
• Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz  
• Two differential inputs support LVPECL, LVDS, LVHSTL, HCSL or  
LVCMOS reference clocks  
• Generates 8 differential or 16 LVCMOS outputs  
The 8P791208 supports two output banks, each with its own power  
supply. All outputs in one bank would generate the same output  
frequency, but each output can be individually controlled for output  
type or output enable.  
• Outputs arranged in two banks of four outputs each  
• Select pins control which input drives which of two output banks  
• Controlled by 3-level input pins that are 3.3V tolerant for all core  
voltages  
The device can operate over the -40°C to 85°C temperature range.  
• Output type may be selected from LVPEC, LVDS or 2xLVCMOS  
• Each bank supports a separate power supply of 3.3V, 2.5V or  
1.8V  
• LVCMOS outputs are limited to 125MHz maximum and support  
swings of 3.3V, 2.5V, 1.8V and 1.5V  
• Individual output enables and output type selection supported  
• Output noise floor of –158dBc/Hz @ 156.25MHz  
• Core voltage supply of 3.3V, 2.5V or 1.8V  
• –40°C to 85°C ambient operating temperature  
• Lead-free (RoHS 6) QFN-32 (5mm x 5mm) packaging  
©2016 Integrated Device Technology  
1
November 28, 2016  
8P79208 Datasheet  
Block Diagram  
8P791208 transistor count: 9,703  
Pin Assignment  
Figure 1: Pin Assignment for 5mm × 5mm VFQFN Package – Top View  
31 30 29 28 27 26 25  
32  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
OEB1  
QB0  
OEA1  
QA0  
nQB0  
QB1  
nQA0  
QA1  
nQB1  
VCCOB  
QB2  
nQA1  
VCCOA  
QA2  
nQA2  
nQB2  
10 11 12 13 14 15 16  
9
©2016 Integrated Device Technology  
2
November 28, 2016  
8P79208 Datasheet  
Pin Descriptions  
Table 1: Pin Description  
Number  
Name  
Type[1]  
Description  
1
2
OEA1  
QA0  
Input (PU)  
Output  
Controls output enable functions for Bank A. LVCMOS/LVTTL input levels.  
Positive differential clock output. Included in Bank A. Refer to Output Drivers section for  
additional details.  
3
4
5
nQA0  
QA1  
Output  
Output  
Output  
Negative differential clock output. Included in Bank A. Refer to Output Drivers section for  
additional details.  
Positive differential clock output. Included in Bank A. Refer to Output Drivers section for  
additional details.  
nQA1  
Negative differential clock output. Included in Bank A. Refer to Output Drivers section for  
additional details.  
6
7
VCCOA  
QA2  
Power  
Output  
Output voltage supply for output Bank A.  
Positive differential clock output. Included in Bank A. Refer to Output Drivers section for  
additional details.  
8
9
nQA2  
QA3  
Output  
Output  
Output  
Negative differential clock output. Included in Bank A. Refer to Output Drivers section for  
additional details.  
Positive differential clock output. Included in Bank A. Refer to Output Drivers section for  
additional details.  
10  
nQA3  
Negative differential clock output. Included in Bank A. Refer to Output Drivers section for  
additional details.  
11  
12  
13  
IOA  
VCC  
Input (PU/PD)  
Power  
Controls output mode functions for Bank A. 3-level input.  
Core Logic voltage supply.  
CLK_SEL  
Input (PU/PD)  
Input Clock Selection Control pin. 3-level input. This pin’s function is described in the  
Input Selection section.  
14  
15  
IOB  
Input (PU/PD)  
Output  
Controls output mode functions for Bank B. 3-level input.  
nQB3  
Negative differential clock output. Included in Bank B. Refer to Output Drivers section for  
additional details.  
16  
17  
18  
QB3  
nQB2  
QB2  
Output  
Output  
Output  
Positive differential clock output. Included in Bank B. Refer to Output Drivers section for  
additional details.  
Negative differential clock output. Included in Bank B. Refer to Output Drivers section for  
additional details.  
Positive differential clock output. Included in Bank B. Refer to Output Drivers section for  
additional details.  
19  
20  
VCCOB  
nQB1  
Power  
Output  
Output voltage supply for Output Bank B.  
Negative differential clock output. Included in Bank B. Refer to Output Drivers section for  
additional details.  
21  
22  
QB1  
Output  
Output  
Positive differential clock output. Included in Bank B. Refer to Output Drivers section for  
additional details.  
nQB0  
Negative differential clock output. Included in Bank B. Refer to Output Drivers section for  
additional details.  
©2016 Integrated Device Technology  
3
November 28, 2016  
8P79208 Datasheet  
Table 1: Pin Description (Continued)  
23  
QB0  
Output  
Positive differential clock output. Included in Bank B. Refer to Output Drivers section for  
additional details.  
24  
25  
26  
OEB1  
CLK1  
Input (PU)  
Input (PD)  
Controls output enable functions for Bank B. LVCMOS/LVTTL input levels.  
Non-inverting differential clock input.  
nCLK1  
Input (PU/PD)  
Inverting differential clock input. VCC/2 when left floating (set by the internal pull-up and  
pulldown resistors).  
27  
28  
29  
30  
31  
VCC  
OEB0  
OEA0  
VCC  
Power  
Input (PU)  
Input (PU)  
Power  
Core Logic voltage supply.  
Controls output enable functions for Bank B. LVCMOS/LVTTL input levels.  
Controls output enable functions for Bank A. LVCMOS/LVTTL input levels.  
Core Logic voltage supply.  
nCLK0  
Input (PU/PD)  
Inverting differential clock input. VCC/2 when left floating (set by the internal pull-up and  
pull-down resistors).  
32  
CLK0  
Input (PD)  
Ground  
Non-inverting differential clock input.  
Must be connected to GND.  
EP  
Exposed Pad  
[1] Pull-up (PU) and pull-down (PD) resistors are indicated in parentheses. Pull-up and pull-down refers to internal input resistors.  
See Table 10, DC Input Characteristics, for typical values.  
©2016 Integrated Device Technology  
4
November 28, 2016  
8P79208 Datasheet  
Principles of Operation  
Input Selection  
The 8P791208 supports two input references: CLK0 and CLK1 that may be driven with differential or single-ended clock signals. Either may be  
used as the source frequency for either or both output banks under control of the CLK_SEL input pin.  
Table 2: Input Selection Control  
CLK_SEL  
Description  
Banks A & B both driven from CLK1  
High  
Middle[1]  
Low  
Bank A driven from CLK0 & Bank B driven from CLK1  
Banks A & B both driven from CLK0  
[1] A ‘middle’ voltage level is defined in Table 11. Leaving the input pin open will  
also generate this level via a weak internal resistor network.  
Output Drivers  
The QA[0:3] and QB[0:3] clock outputs are provided with pin-controlled output drivers. The following table shows how each bank can be  
controlled. Each bank is separately controlled and all outputs within a single bank will behave the same way.  
Table 3: Output Mode Control  
IOx  
Output Bank Mode Function  
All outputs in the bank are LVDS  
High  
Middle  
Low  
All outputs in the bank are LVPECL  
All outputs in the bank are LVCMOS  
The operating voltage ranges of each output is determined by its independent output power pin (VCCOA or VCCOB) and thus each can have  
different output voltage levels. Output voltage levels of 1.8V, 2.5V or 3.3V are supported for differential operation and LVCMOS operation. In  
addition, LVCMOS output operation supports 1.5V VCCO.  
LVCMOS Operation  
When a given output is configured to provide LVCMOS levels, then both the Q and nQ outputs will toggle at the selected output frequency. All  
the previously described configuration and control apply equally to both outputs. Frequency, voltage levels and enable / disable status apply to  
both the Q and nQ pins. When configured as LVCMOS, the Q & nQ outputs are in-phase relative to one another.  
Output Enable Control  
The 8P791208 has separate pins that control the output enable behavior for each bank as shown in Table 4.  
Table 4: Output Enable Control  
Output Enable Function  
OEx1  
OEx0  
Qx3  
Qx2  
Qx1  
Qx0  
High  
High  
Low  
Low  
High  
Low  
High  
Low  
On  
Hi-Z  
On  
On  
Hi-Z  
On  
On  
On  
On  
On  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
©2016 Integrated Device Technology  
5
November 28, 2016  
8P79208 Datasheet  
Absolute Maximum Ratings  
NOTE: The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the  
device. Functional operation of the 8P79208 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may  
affect device reliability.  
Table 5: Absolute Maximum Ratings  
Item  
Supply Voltage, VCCX[1] to GND  
Rating  
3.63V  
Inputs OEA[1:0], OEB[1:0], IOA, IOB, CLK_SEL, CLK0, nCLK0,  
CLK1, nCLK1  
–0.5V to VCC 0.5V  
Outputs, IO QA[0:3], nQA[0:3]; QB[0:3], nQB[0:3]  
Continuous Current  
40mA  
60mA  
Surge Current  
Outputs, VO QA[0:3], nQA[0:3]; QB[0:3], nQB[0:3]  
Maximum Junction Temperature  
–0.5V to VCCOx[2] 0.5V  
125°C  
Storage Temperature, TSTG  
–65°C to 150°C  
260°C  
Lead Temperature (Soldering, 10s)  
[1] VCCX denotes VCC, VCCOA, or VCCOB  
[2] VCCOX denotes VCCOA or VCCOB  
.
.
Supply Voltage Characteristics  
Table 6: Power Supply Characteristics, V  
= V  
= V  
= 3.3V ±5%, V = 0V, T = –40°C to 85°C  
CC  
CCOA  
CCOB  
EE  
A
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VCC  
Core supply voltage  
3.135  
3.135  
3.3  
3.3  
3.465  
VCC  
V
V
VCCOA, Output supply voltage  
VCCOB  
ICC  
Core supply current  
Output supply current[1] All outputs configured for LVDS logic levels;  
outputs unloaded  
Device configured for LVDS logic levels  
22  
25  
mA  
mA  
ICCOX  
136  
153  
[1] Internal dynamic switching current at maximum fOUT is included.  
©2016 Integrated Device Technology  
6
November 28, 2016  
8P79208 Datasheet  
Table 7: Power Supply Characteristics, V  
= V  
= V  
= 2.5V ±5%, V = 0V, T = –40°C to 85°C  
CC  
CCOA  
CCOB  
EE  
A
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VCC  
Core supply voltage  
2.375  
2.375  
2.5  
2.5  
2.625  
VCC  
V
V
VCCOA, Output supply voltage  
VCCOB  
ICC  
Core supply current  
Output supply current[1] All outputs configured for LVDS logic levels;  
outputs unloaded  
Device configured for LVDS logic levels  
21  
24  
mA  
mA  
ICCOX  
135  
151  
[1] Internal dynamic switching current at maximum fOUT is included.  
Table 8: Power Supply Characteristics, V = V  
= V  
= 1.8V ±5%, V = 0V, T = –40°C to 85°C  
CC  
CCOA  
CCOB  
EE  
A
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VCC  
Core supply voltage  
1.71  
1.71  
1.8  
1.8  
1.89  
VCC  
V
V
VCCOA, Output supply voltage  
VCCOB  
ICC  
Core supply current  
Device configured for LVDS logic levels  
18  
20  
mA  
mA  
ICCOX Output supply current[1] All outputs configured for LVDS logic levels;  
outputs unloaded  
122  
137  
[1] Internal dynamic switching current at maximum fOUT is included.  
Table 9: Typical Output Supply Current, V  
= V  
= 3.3V±5%, 2.5V±5% or 1.8V±5%, V = 0V,  
CCOA  
CCOB EE  
T = –40°C to 85°C  
A
VCCOx[3] = 3.3V ±5%  
VCCOx[3] = 2.5V ±5%  
VCCOx[3] = 1.8V ±5%  
VCCOx[3] = 1.5V ±5%  
All outputs  
enabled  
77  
49  
42  
77  
49  
42  
52  
37  
23  
52  
37  
23  
46  
41  
40  
46  
41  
40  
76  
49  
36  
76  
49  
36  
51  
34  
19  
51  
34  
19  
27  
25  
21  
27  
25  
21  
69  
49  
28  
69  
49  
28  
46  
32  
32  
46  
32  
32  
25  
20  
20  
25  
20  
20  
21  
17  
17  
21  
17  
17  
mA  
mA  
mA  
mA  
mA  
mA  
Bank B  
output  
2 outputs  
supply enabled  
ICCOB  
current  
No outputs  
enabled  
All outputs  
enabled  
Bank A  
output  
2 outputs  
supply enabled  
ICCOA  
current  
No outputs  
enabled  
[1] Internal dynamic switching current at maximum fOUT is included.  
[2] Tested with outputs unloaded.  
[3] VCCOx denotes VCCOA, VCCOB  
.
©2016 Integrated Device Technology  
7
November 28, 2016  
8P79208 Datasheet  
DC Electrical Characteristics  
Table 10: Pin Characteristics  
Symbol  
Parameter  
Input capacitance  
Input pull-up resistor  
Test Conditions[1]  
Minimum  
Typical  
Maximum  
Units  
CIN  
2
pF  
k  
k  
RPULLUP  
51  
51  
24  
RPULLDOWN Input pull-down resistor  
LVCMOS output type selected  
VCCOx = 3.3V +5%  
LVCMOS output type selected  
15  
25  
48  
QA[3:0],  
V
CCOx = 2.5V +5%  
LVCMOS output type selected  
CCOx = 1.8V +5%  
LVCMOS output type selected  
CCOx = 1.5V +5%  
Output  
impedance  
nQA[3:0],  
QB[3:0],  
nQB[3:0]  
ROUT  
V
V
LVPECL  
LVDS  
4.2  
5.8  
pF  
pF  
VCCOx = 3.465V or 2.625V  
Power dissipation  
capacitance   
(per output pair)  
QA[3:0], nQA[3:0],  
QB[3:0], nQB[3:0]  
LVCMOS  
LVPECL  
LVDS  
CPD  
VCCOx = 1.89V  
CCOx = 1.89V or 1.545V  
4.7  
5.2  
pF  
pF  
V
LVCMOS  
[1] VCCOx refers to VCCOA for QA[3:0], nQA[3:0], or VCCOB for QB[3:0], nQB[3:0].  
©2016 Integrated Device Technology  
8
November 28, 2016  
8P79208 Datasheet  
Table 11: LVCMOS/LVTTL Control / Status Signals DC Characteristics for 3-level Pins, V = 0V,   
EE  
T = –40°C to 85°C  
A
Parameter  
Signals  
Test Conditions  
Minimum Typical Maximum Units  
VCC = 3.3V  
0.85 VCC  
0.85 VCC  
0.85 VCC  
0.45 VCC  
0.45 VCC  
0.45 VCC  
–0.3  
3.63  
V
V
Input  
high voltage  
IOA, IOB,  
CLK_SEL  
VIH  
VIM  
VIL  
V
V
CC = 2.5V  
CC = 1.8V  
2.625  
1.89  
V
VCC = 3.3V  
0.55 VCC  
0.55 VCC  
0.55 VCC  
0.15 VCC  
0.15 VCC  
0.15 VCC  
150  
V
Input  
IOA, IOB,  
CLK_SEL  
middle  
V
V
CC = 2.5V  
CC = 1.8V  
V
voltage[1]  
V
VCC = 3.3V  
V
Input  
low voltage  
OEA[1:0], OEB[1:0]  
IOA, IOB, CLK_SEL  
V
V
CC = 2.5V  
CC = 1.8V  
–0.3  
V
–0.3  
V
IIH  
IIM  
IIL  
Input  
IOA, IOB,  
VCC = VIN = 3.465V or 2.625V or 1.89V  
A  
high current  
CLK_SEL  
Input  
IOA, IOB,  
VCC = 3.465V or 2.625V or 1.89V,   
VIN = VCC /2  
A  
A  
middle current CLK_SEL  
Input  
low current  
OEA[1:0], OEB[1:0]VCC = 3.465V or 2.625V or 1.89V,   
IOA, IOB, CLK_SEL IN = 0V  
–150  
V
[1] For 3-level input pins, a mid-level voltage is used to select the 3rd state. This voltage will be maintained by a weak internal pull-up /  
pull-down network for each pin to select this state if the pin is left open. It is recommended that any external resistor networks used to  
select a middle-level input voltage be terminated to the device’s core VCC voltage level.  
Table 12: LVCMOS/LVTTL Control / Status Signals DC Characteristics for 2-Level Pins, V = 0V,   
EE  
T = –40°C to 85°C  
A
Symbol Parameter  
Signals  
Test Conditions  
Minimum Typical Maximum Units  
VCC = 3.3V  
2
1.7  
3.63  
2.625  
1.89  
V
V
Input  
high voltage  
VIH  
OEA[1:0], OEB[1:0]  
V
V
CC = 2.5V  
CC = 1.8V  
0.65 VCC  
–0.3  
V
VCC = 3.3V  
0.8  
V
Input  
low voltage  
VIL  
OEA[1:0], OEB[1:0]  
V
V
CC = 2.5V  
CC = 1.8V  
–0.3  
0.7  
V
–0.3  
0.35 VCC  
150  
V
IIH  
IIL  
Input  
high current  
OEA[1:0], OEB[1:0] VCC = VIN = 3.465V or 2.625V or 1.89V  
A  
Input  
OEA[1:0], OEB[1:0] VCC = VIN = 3.465V or 2.625V or 1.89V  
–150  
A  
low current  
©2016 Integrated Device Technology  
9
November 28, 2016  
8P79208 Datasheet  
,
Table 13: Differential Input DC Characteristics, V  
= 3.3V±5%, 2.5V±5% or 1.8V±5%, V = 0V,   
EE  
CC  
T = –40°C to 85°C  
A
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum Units  
IIH  
Input high current  
CLKx,  
V
CC = VIN = 3.465V or 2.625V  
150  
A  
nCLKx[1]  
CLKx[1]  
nCLKx[1]  
Peak-to-peak voltage[2]  
Common mode input voltage[2], [3]  
VCC = 3.465V or 2.625V, VIN = 0V  
VCC = 3.465V or 2.625V, VIN = 0V  
–5  
A  
A  
V
IIL  
Input low current  
–150  
0.15  
VEE  
VPP  
1.3  
VCMR  
VCC – 1.2  
V
[1] CLKx denotes CLK0, CLK1. nCLKx denotes nCLK0, nCLK1.  
[2] VIL should not be less than –0.3V. VIH should not be higher than VCC  
[3] Common mode voltage is defined as the cross-point.  
.
[1]  
Table 14: LVDS DC Characteristics, V  
= 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, V  
= 3.3V ±5%, V = 0V,  
EE  
CC  
CCOx  
T = –40°C to 85°C  
A
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VOD  
VOD  
VOS  
Differential output voltage  
VOD magnitude change  
Offset voltage  
Qx, nQx[2]  
Qx, nQx[2]  
Qx, nQx[2]  
Qx, nQx[2]  
247  
465  
50  
mV  
mV  
V
Terminated 100across  
Qx and nQx  
1.1  
1.375  
50  
VOS  
VOS magnitude change  
mV  
[1] VCCOx denotes VCCOA, VCCOB  
.
[2] Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.  
nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3.  
[1]  
Table 15: LVDS DC Characteristics, V  
= 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, V  
= 2.5V ±5%, V = 0V,  
EE  
CC  
CCOx  
T = –40°C to 85°C  
A
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VOD  
VOD  
VOS  
Differential output voltage Qx, nQx[2]  
247  
465  
50  
mV  
mV  
V
VOD magnitude change  
Offset voltage  
Qx, nQx[2]  
Qx, nQx[2]  
Qx, nQx[2]  
Terminated 100across  
Qx and nQx  
1.1  
1.375  
50  
VOS  
VOS magnitude change  
mV  
[1] VCCOx denotes VCCOA, VCCOB  
.
[2] Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.  
nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3.  
©2016 Integrated Device Technology  
10  
November 28, 2016  
8P79208 Datasheet  
[1]  
Table 16: LVDS DC Characteristics, V  
= 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, V  
= 1.8V ±5%, V = 0V,  
EE  
CC  
CCOx  
T = –40°C to 85°C  
A
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VOD  
VOD  
VOS  
Differential output voltage  
VOD magnitude change  
Offset voltage  
Qx, nQx[2]  
Qx, nQx[2]  
Qx, nQx[2]  
Qx, nQx[2]  
247  
454  
50  
mV  
mV  
V
Terminated 100across  
Qx and nQx  
1.1  
1.375  
50  
VOS  
VOS magnitude change  
mV  
[1] VCCOx denotes VCCOA, VCCOB  
.
[2] Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.  
nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3.  
[1]  
Table 17: LVCMOS Clock Outputs DC Characteristics, V  
= 3.3V±5%, 2.5V±5% or 1.8V±5%, V = 0V,   
EE  
CCOx  
T = –40°C to 85°C  
A
[1]  
[1]  
VCCOx  
=
VCCOx  
=
3.3V ±5%  
2.5V ±5%  
VCCOx[1] = 1.8V ±5%  
VCCOx[1] = 1.5V ±5%  
Test  
Symbol Parameter Conditions Min Typ Max Min Typ Max  
Min  
VCC 0.45  
Typ Max  
Min  
Typ Max Units  
VOH  
Output   
IOH = –8mA 2.4  
1.8  
VCC 0.38  
V
high voltage  
Qx, nQx[2]  
VOL  
Output   
IOL = 8mA  
0.8  
0.6  
0.45  
0.38  
V
low voltage  
Qx, nQx[2]  
[1] VCCOx denotes VCCOA, VCCOB  
.
[2] Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3.  
Table 18: Input Frequency Characteristics, V  
= 3.3V±5%, 2.5V±5% or 1.8V±5%, V = 0V,   
EE  
CC  
T = –40°C to 85°C  
A
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
fIN  
Input Frequency  
Input duty cycle[2]  
CLKx, nCLKx[1]  
1Hz  
700MHz  
idc  
50  
%
[1] CLKx denotes CLK0, CLK1. nCLKx denotes nCLK0, nCLK1.  
[2] Any deviation from a 50% / 50% duty cycle on the input may be reflected in the output duty cycle.  
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8P79208 Datasheet  
AC Electrical Characteristics  
[1]  
Table 19: AC Characteristics, V  
= 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, V  
= 3.3V ±5%, 2.5V ±5% or   
CC  
A
CCOx  
1.8V ±5%, V = 0V, T = –40°C to 85°C  
EE  
Symbol Parameter[2]  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
fOUT  
Output  
frequency  
LVDS, LVPECL  
LVCMOS  
1PPS  
700MHz  
fOUT  
Output  
1PPS  
125MHz  
frequency  
LVPECL  
20% to 80%  
125  
150  
175  
200  
250  
200  
300  
200  
700  
550  
575  
600  
775  
915  
950  
1400  
60  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
%
20% to 80%, VCCOx = 3.3V  
20% to 80%, VCCOx = 2.5V  
20% to 80%, VCCOx = 1.8V  
20% to 80%, VCCOx = 3.3V  
20% to 80%, VCCOx = 2.5V  
20% to 80%, VCCOx = 1.8V  
20% to 80%, VCCOx = 1.5V  
LVDS  
Output rise  
and fall times  
tR / tF  
LVCMOS  
LVPECL, LVDS[6]  
LVCMOS[7]  
Bank skew[3],  
tsk(b)  
odc  
[4], [5]  
100  
55  
LVPECL, LVDS  
LVPECL, LVDS  
VCCOx = 3.3V or 2.5V  
45  
43  
45  
43  
40  
V
CCOx = 1.8V  
57  
%
Output   
VCCOx = 3.3V or 2.5V  
55  
duty cycle[8], [9]  
LVCMOS  
V
V
CCOx = 1.8V  
CCOx = 1.5V  
57  
%
60  
MUXISOL Mux Isolation  
Noise Floor  
70  
dB  
LVPECL, LVDS  
Offset >10MHz from156.25MHz carrier  
157  
dBc/Hz  
[1] VCCOx denotes VCCOA, VCCOB  
.
[2] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal  
equilibrium has been reached under these conditions.  
[3] This parameter is guaranteed by characterization. Not tested in production.  
[4] This parameter is defined in accordance with JEDEC Standard 65.  
[5] Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.  
[6] Measured at the output differential crosspoint.  
[7] Measured at VCCOx/2 of the rising edge.  
[8] Measured using 50% /50% duty cycle on input reference.  
[9] Measurements taken for the following output frequencies:   
LVDS and LVPECL: 50MHz, 100MHz, 156.25MHz, 250MHz, 312.5MHz, 491.52MHz, 700MHz  
LVCMOS: 25MHz, 50MHz, 100MHz, 125MHz.  
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8P79208 Datasheet  
[1]  
Table 20: Typical Additive Jitter, V  
= 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, V  
= 3.3V ±5%, 2.5V ±5%,  
CC  
CCOx  
1.8V ±5% or 1.5V ±5% (1.5V only supported for LVCMOS outputs), V = 0V, T = –40°C to 85°C  
EE  
A
Symbol  
Parameter  
LVPECL  
Test Conditions[2]  
fOUT = 156.25MHz, VCCOx = 3.3V or 2.5V  
CCOx = 1.8V  
Minimum  
Typical  
Maximum  
Units  
64  
81  
fs  
fs  
Integration Range:  
12kHz to 20MHz  
V
f
OUT = 156.25MHz,  
VCCOx = 3.3V or 2.5V  
CCOx = 1.8V  
70  
fs  
fs  
RMS  
Additive Jitter  
(Random)  
LVDS  
Integration Range:  
12kHz to 20MHz  
tjit(f)  
V
114  
VCCOx = 3.3V or 2.5V  
VCCOx = 1.8V  
105  
140  
192  
fs  
fs  
fs  
f
OUT = 125MHz,  
LVCMOS Integration Range:  
12kHz to 20MHz  
V
CCOx = 1.5V  
[1] VCCOx denotes VCCOA, VCCOB  
.
[2] All outputs configured for the specific output type, as shown in the table.  
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8P79208 Datasheet  
Applications Information  
Recommendations for Unused Input and Output Pins  
Inputs:  
CLK/nCLK Inputs  
For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional  
protection, a 1kresistor can be tied from CLK to ground.  
LVCMOS LVTTL Level Control Pins  
All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k  
resistor can be used.  
LVCMOS 3-level I/O Control Pins  
These pins are 3-level pins and if left unconnected this is interpreted as a valid input selection option (Middle).  
Outputs:  
LVCMOS Outputs  
All unused LVCMOS outputs can be left floating. It is recommended that there is no trace attached.  
LVPECL Outputs  
All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should  
either be left floating or terminated.  
LVDS Outputs  
All unused LVDS output pairs can be either left floating or terminated with 100across. If they are left floating, there should be no trace  
attached.  
©2016 Integrated Device Technology  
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8P79208 Datasheet  
Wiring the Differential Input to Accept Single-ended Levels  
Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage V1 = VCC/2 is generated by the bias  
resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the  
input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1in the center of the input voltage swing. For example,  
if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set V1 at 1.25V. The values below are for when both the  
single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and  
the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in  
half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50  
applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS  
driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input  
can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced while maintaining an edge rate faster than 1V/ns. The  
datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing  
can be larger, however VIL cannot be less than –0.3V and VIH cannot be more than VCC 0.3V. Though some of the recommended  
components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet  
specifications are characterized and guaranteed by using a differential signal.  
Figure 2: Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels  
©2016 Integrated Device Technology  
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8P79208 Datasheet  
3.3V Differential Clock Input Interface  
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR  
input requirements. Figure 3 to Figure 7 show interface examples for the CLK/nCLK input driven by the most common driver types. The input  
interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination  
requirements. For example, in Figure 3, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver  
from another vendor, use their termination recommendation..  
Figure 3. CLKx/nCLKx Input Driven by an  
Figure 4. CLKx/nCLKx Input Driven by a  
IDT Open Emitter LVHSTL Driver  
3.3V LVPECL Driver  
3.3V  
1.8V  
Zo = 50Ω  
CLK  
Zo = 50Ω  
nCLK  
Differential  
Input  
LVHSTL  
R1  
50Ω  
R2  
50Ω  
IDT  
LVHSTL Driver  
Figure 5. CLK/nCLK Input Driven by a  
Figure 6. CLK/nCLK Input Driven by a   
3.3V LVPECL Driver  
3.3V LVDS Driver  
3.3V  
3.3V  
*R3  
*R4  
CLK  
nCLK  
Differential  
Input  
HCSL  
Figure 7. CLK/nCLK Input Driven by a   
3.3V HCSL Driver  
©2016 Integrated Device Technology  
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8P79208 Datasheet  
2.5V Differential Clock Input Interface  
CLKx/nCLKx accepts LVDS, LVPECL, LVHSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input  
requirements. Figure 8 to Figure 12 show interface examples for the CLKx/nCLKx input driven by the most common driver types. The input  
interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination  
requirements. For example, in Figure 8, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver  
from another vendor, use their termination recommendation.  
Figure 8. CLKx/nCLKx Input Driven by an   
Figure 9. CLKx/nCLKx Input Driven by a   
IDT Open Emitter LVHSTL Driver  
2.5V LVPECL Driver  
2.5V  
1.8V  
Zo = 50  
CLK  
Zo = 50  
nCLK  
Differential  
Input  
LVHSTL  
R1  
50  
R2  
50  
IDT Open Emitter  
LVHSTL Driver  
Figure 10. CLK/nCLK Input Driven by a   
Figure 11. CLK/nCLK Input Driven by a   
2.5V LVPECL Driver  
2.5V LVDS Driver  
Figure 12. CLK/nCLK Input Driven by a   
2.5V HCSL Driver  
2.5V  
2.5V  
Zo = 50Ω  
*R3  
33Ω  
CLK  
Zo = 50Ω  
nCLK  
Differential  
Input  
*R4  
33Ω  
HCSL  
R1  
50Ω  
R2  
50Ω  
*Optional – R3 and R4 can be 0Ω  
©2016 Integrated Device Technology  
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8P79208 Datasheet  
LVDS Driver Termination  
For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90and 132. The actual value should  
be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100parallel  
resistor at the receiver and a 100differential transmission-line environment. In order to avoid any transmission-line reflection issues, the  
components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant  
devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 13 can  
be used with either type of output structure. Figure 14, which can also be used with both output types, is an optional termination with center tap  
capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is  
recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are  
LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output.  
Figure 13: Standard LVDS Termination  
ZO ZT  
LVDS  
Driver  
LVDS  
Receiver  
ZT  
Figure 14: Optional LVDS Termination  
Z
T
T
2
ZO ZT  
LVDS  
LVDS  
Driver  
Receiver  
C
Z
2
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8P79208 Datasheet  
Termination for 3.3V LVPECL Outputs  
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended  
only as guidelines.  
The differential output is a low impedance follower output that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC  
current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50transmission lines.  
Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figure 15 and Figure 16  
show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended  
that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.  
Figure 15: 3.3V LVPECL Output Termination  
Figure 16: 3.3V LVPECL Output Termination  
3.3V  
R3  
R4  
125  
125  
3.3V  
3.3V  
Zo = 50  
Zo = 50  
+
_
Input  
R1  
84  
R2  
84  
©2016 Integrated Device Technology  
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8P79208 Datasheet  
Termination for 2.5V LVPECL Outputs  
Figure 17 and Figure 18 show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50to VCCO  
– 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground level. The R3 in Figure 18 can be eliminated and the termination is shown in  
Figure 19.  
Figure 17: 2.5V LVPECL Driver Termination Example  
2.5V  
2.5V  
VCCO = 2.5V  
R1  
R3  
250  
250  
50  
50  
+
–
2.5V LVPECL Driver  
R2  
62.5  
R4  
62.5  
Figure 18: 2.5V LVPECL Driver Termination Example  
2.5V  
VCCO = 2.5V  
50  
+
50  
–
2.5V LVPECL Driver  
R1  
50  
R2  
50  
Figure 19: 2.5V LVPECL Driver Termination Example  
2.5V  
VCCO = 2.5V  
50  
+
50  
–
2.5V LVPECL Driver  
R1  
50  
R2  
50  
R3  
18  
©2016 Integrated Device Technology  
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8P79208 Datasheet  
Power Dissipation and Thermal Considerations  
The 8P791208 is a multi-functional, high speed device that targets a wide variety of clock frequencies and applications. Since this device is  
highly programmable with a broad range of features and functionality, the power consumption will vary as each of these features and functions  
is enabled.  
The 8P791208 device was designed and characterized to operate within the ambient industrial temperature range of TA = -40°C to 85°C. The  
ambient temperature represents the temperature around the device, not the junction temperature. When using the device in extreme cases,  
such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe and reliable  
junction temperature. Extreme care must be taken to avoid exceeding 125°C junction temperature.  
The power calculation examples below were generated using a maximum ambient temperature and supply voltage. For many applications, the  
power consumption will be much lower. Please contact IDT technical support for any concerns on calculating the power dissipation for your  
own specific configuration.  
Power Domains  
The 8P791208 device has a number of separate power domains that can be independently enabled and disabled via register accesses (all  
power supply pins must still be connected to a valid supply voltage). Figure 20 below indicates the individual domains and the associated  
power pins.  
Figure 20: 8P791208 Power Domains  
©2016 Integrated Device Technology  
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8P79208 Datasheet  
Power Consumption Calculation  
Determining total power consumption involves several steps:  
1. Determine the power consumption using maximum current values for core voltage from Table 6, Table 7, Table 8 and Table 9, Page 7 for  
the appropriate case of how many banks or outputs are enabled.  
2. Determine the nominal power consumption of each enabled output path.  
a. This consists of a base amount of power that is independent of operating frequency, as shown in Table 21 through Table 27 (depending  
on the chosen output protocol).  
b. Then there is a variable amount of power that is related to the output frequency. This can be determined by multiplying the output  
frequency by the FQ_Factor shown in Table 21 through Table 27.  
3. All of the above totals are then summed.  
Thermal Considerations  
Once the total power consumption has been determined, it is necessary to calculate the maximum operating junction temperature for the  
device under the environmental conditions it will operate in. Thermal conduction paths, air flow rate and ambient air temperature are factors  
that can affect this. The thermal conduction path refers to whether heat is to be conducted away via a heat-sink, via airflow or via conduction  
into the PCB through the device pads (including the ePAD). Thermal conduction data is provided for typical scenarios in Table 29, Page 25.  
Please contact IDT for assistance in calculating results under other scenarios.  
©2016 Integrated Device Technology  
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8P79208 Datasheet  
Current Consumption Data and Equations  
Table 24: 3.3V LVCMOS Output Calculation Table  
Table 21: 3.3V LVDS Output Calculation Table  
LVCMOS  
Base_Current (mA)  
FQ_Factor  
LVDS  
(mA/MHz)  
Base_Current (mA)  
Bank A  
Bank B  
31.522  
31.522  
Bank A  
Bank B  
0.08  
0.08  
25.309  
25.309  
Table 25: 2.5V LVCMOS Output Calculation Table  
Table 22: 2.5V LVDS Output Calculation Table  
LVCMOS  
Base_Current (mA)  
FQ_Factor  
(mA/MHz)  
Bank A  
Bank B  
18.665  
18.665  
LVDS  
Base_Current (mA)  
Bank A  
Bank B  
0.05  
0.05  
35.476  
35.476  
Table 26: 1.8V LVCMOS Output Calculation Table  
LVCMOS  
Base_Current (mA)  
Table 23: 1.8V LVDS Output Calculation Table  
Bank A  
Bank B  
14.704  
14.704  
FQ_Factor  
(mA/MHz)  
LVDS  
Base_Current (mA)  
Bank A  
Bank B  
0.05  
0.05  
35.330  
35.330  
Table 27: 1.5V LVCMOS Output Calculation Table  
LVCMOS  
Base_Current (mA)  
Bank A  
Bank B  
12.522  
12.522  
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8P79208 Datasheet  
Applying the values to the following equation will yield output current by frequency:  
Qx Current (mA) = FQ_Factor Frequency (MHz) Base_Current  
where:  
Qx Current is the specific output current according to output type and frequency  
FQ_Factor is used for calculating current increase due to output frequency  
Base_Current is the base current for each output path independent of output frequency  
The second step is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient, using the following  
equation:  
TJ = TA (JA Pdtotal  
where:  
)
TJ is the junction temperature (°C)  
TA is the ambient temperature (°C)  
JA is the thermal resistance value from Table 29, Page 25, dependent on ambient airflow (°C/W).  
Pdtotal is the total power dissipation of the 8P791208 under usage conditions, including power dissipated due to loading (W).  
Note: For LVPECL outputs the power dissipation through the load is assumed to be 27.95mW. When selecting LVCMOS outputs, power  
dissipation through the load will vary based on a variety of factors including termination type and trace length. For these examples, power  
dissipation through loading will be calculated using CPD (found in Table 10, Page 8) and output frequency:  
2
PdOUT = CPD fOUT VCCO  
where:  
Pdout is the power dissipation of the output (W)  
C
PD is the power dissipation capacitance (pF)  
fOUT is the output frequency of the selected output (MHz)  
VCCO is the voltage supplied to the appropriate output (V)  
Example Calculations  
Table 28: Example 1 – Common Customer Configuration (3.3V Core Voltage)  
Configuration  
Frequency (MHz)  
VCCO  
Bank A  
Bank B  
LVDS  
LVDS  
3.3V  
3.3V  
125  
Core supply current, ICC = 25mA (maximum)  
• Output supply current, Bank A current = 0.08mA x 125MHz + 30mA = 40mA  
• Output supply current, Bank B current = 0.08mA x 125MHz + 30mA = 40mA  
Total device current = 25mA + 40mA + 40mA = 105mA  
Total device power = 3.465V 105mA = 363.825mW or 0.364W  
With an ambient temperature of 85°C and no airflow, the junction temperature is:  
• TJ = 85°C + 35.23°C/W 0.364W = 97.82°C  
©2016 Integrated Device Technology  
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8P79208 Datasheet  
LVPECL Power Considerations (700MHz)  
This section provides information on power dissipation and junction temperature for the 8P791208.   
Equations and example calculations are also provided.  
4. Power Dissipation.  
The total power dissipation for the 8P791208 is the sum of the core power plus the power dissipated in the load(s).   
The following is the power dissipation for VCC = 3.465V, which gives worst case results.  
NOTE: IEE_MAX @ 85°C is 124mA  
Please refer to section,Calculations and Equations. for details on calculating power dissipated in the load.  
▪ Power (core)MAX = VCC_MAX IEE_MAX = 3.465V 124mA = 429.66mW  
▪ Power (outputs)MAX = 27.95mW/Loaded Output pair  
If all outputs are loaded, the total power is 8 27.95mW = 223.6mW  
▪ Total Power_MAX = 429.66W 223.6mW = 653.26mW  
5. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the  
bond wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 35.23°C/W per Table 29 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C 0.653W 35.23°C/W = 108°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 29: Thermal Resistance JA for 32-Lead VFQFN, Forced Convection  
JA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
35.23°C/W  
31.6°C/W  
30.0°C/W  
©2016 Integrated Device Technology  
25  
November 28, 2016  
8P79208 Datasheet  
6. Calculations and Equations.  
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.  
LVPECL output driver circuit and termination are shown in Figure 21.  
Figure 21: LVPECL Driver Circuit and Termination  
VCCO  
Q1  
VOUT  
RL  
50Ω  
VCCO - 2V  
To calculate worst case power dissipation into the load, use the following equations which assume a 50load, and a termination voltage of  
CCO – 2V.  
V
▪ For logic high, VOUT = VOH_MAX = VCCO_MAX 0.8V  
(VCCO_MAX VOH_MAX) = 0.8V  
▪ For logic low, VOUT = VOL_MAX = VCCO_MAX 1.75V  
(VCCO_MAX VOL_MAX) = 1.75V  
Pd_H is power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
Pd_H = [(VOH_MAX (VCCO_MAX 2V))/RL] (VCCO_MAX VOH_MAX) = [(2V (VCCO_MAX VOH_MAX))/RL] (VCCO_MAX VOH_MAX) =  
[(2V – 0.8V)/50] * 0.8V = 19.2mW  
Pd_L = [(VOL_MAX (VCCO_MAX 2V))/RL] (VCCO_MAX VOL_MAX) = [(2V (VCCO_MAX VOL_MAX))/RL] (VCCO_MAX VOL_MAX) =  
[(2V – 1.75V)/50] 1.75V = 8.75mW  
Total Power Dissipation per output pair = Pd_H Pd_L = 27.95mW  
©2016 Integrated Device Technology  
26  
November 28, 2016  
8P79208 Datasheet  
LVDS Power Considerations (700MHz)  
This section provides information on power dissipation and junction temperature for the 8P791208.   
Equations and example calculations are also provided.  
7. Power Dissipation.  
The total power dissipation for the 8P791208 is the sum of the core power plus the power dissipated in the load(s).   
The following is the power dissipation for VCC = 3.465V, which gives worst case results.  
▪ Power (core)MAX = VCC_MAX ICC_MAX = 3.465V 25mA = 86.625mW  
▪ Power (outputs)MAX = VCCOx_MAX ICCO_MAX = 3.465V 153mA = 530.145mW  
• Total Power_MAX = 86.625W 530.145mW = 616.77mW  
8. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the  
bond wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 35.23°C/W per Table 29, Page 25.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C 0.617W 35.23°C/W = 107°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
©2016 Integrated Device Technology  
27  
November 28, 2016  
8P79208 Datasheet  
LVCMOS Power Considerations (125MHz)  
This section provides information on power dissipation and junction temperature for the 8P791208.   
Equations and example calculations are also provided.  
9. Power Dissipation.  
The total power dissipation for the 8P791208 is the sum of the core power plus the power dissipated in the load(s).   
The following is the power dissipation for VCC = 3.465V, which gives worst case results.  
▪ Power (core)MAX = VCC_MAX ICC_MAX = 3.465V 63mA = 217.81mW  
Dynamic Power Dissipation at f  
OUT(max)  
Total Power:  
Total Power (FOUT_MAX) = [(CPD N) Frequency (VCCO)2] = [(0.58pF 2) 125MHz (3.456V)2] = 13.92722mW per output  
N = number of outputs  
Dynamic Power Dissipation:  
= Static Power Dynamic Power Dissipation  
= 217.81mW 13.927mW  
= 231.737mW  
10. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the  
bond wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 35.23°C/W per Table 29, Page 25.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C 0.232W 35.23°C/W = 93.27°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
©2016 Integrated Device Technology  
28  
November 28, 2016  
8P79208 Datasheet  
32-Lead VFQFN Package Outline and Package Dimensions  
©2016 Integrated Device Technology  
29  
November 28, 2016  
8P79208 Datasheet  
32-Lead VFQFN Package Outline and Package Dimensions (Continued)  
©2016 Integrated Device Technology  
30  
November 28, 2016  
8P79208 Datasheet  
Marking Diagram  
1. IDT  
2. Line 2 and line 3 indicates the part number.  
3. Line 3:  
▪ “#” indicates stepping.  
▪ “YYWW” indicates the date code (YY are the last two digits of the year, and   
“WW” is a work week number that the part was assembled.  
▪ “$” indicates the mark code.  
Ordering Information  
Part/Order Number  
Marking  
Package  
Shipping Packaging  
Temperature  
8P791208NLGI  
8P791208NLGI8  
IDT8P791208NLGI  
IDT8P791208NLGI  
32-lead VFQFN, Lead Free  
32-lead VFQFN, Lead Free  
Tray  
–40°C to 85°C  
–40°C to 85°C  
Tape & Reel, Pin 1  
Orientation: EIA-481-C  
8P791208NLGI/W  
IDT8P791208NLGI  
32-lead VFQFN, Lead Free  
Tape & Reel, Pin 1  
–40°C to 85°C  
Orientation: EIA-481-D  
Table 30: Pin 1 Orientation in Tape and Reel Packaging  
Part Number Suffix  
Pin 1 Orientation  
Illustration  
NLGI8  
Quadrant 1 (EIA-481-C)  
CARRIER TAPE TOPSIDE  
(Round Sprocket Holes)  
Correct Pin 1 ORIENTATION  
USER DIRECTION OF FEED  
NLGI/W  
Quadrant 2 (EIA-481-D)  
CARRIER TAPE TOPSIDE  
(Round Sprocket Holes)  
Correct Pin 1 ORIENTATION  
USER DIRECTION OF FEED  
©2016 Integrated Device Technology  
31  
November 28, 2016  
8P79208 Datasheet  
Revision History  
Date  
Description of Change  
11/28/16  
Initial Final datasheet.  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
www.idt.com/go/support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,  
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are  
not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to,  
the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey  
any license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to  
significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and  
designs, are the property of IDT or their respective third party owners.  
Copyright ©2016 Integrated Device Technology, Inc. All rights reserved.  
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