8P791208_18,PDF,8P791208_18 PDF资料,Datasheet,下载8P791208

Low Additive Jitter 2:8 Buffer with

CMOS / Differential Outputs

8P791208

Datasheet

Description

Features

▪ Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz

The 8P791208 is a low additive jitter 2:8 buffer with CMOS/

differential outputs The device takes one or two reference clocks,

selects between them using a pin selection, and generates up to

eight outputs that are the same as the reference frequency.

▪ Two differential inputs support LVPECL, LVDS, LVHSTL,

HCSL, or LVCMOS reference clocks

▪ Generates 8 differential or 16 LVCMOS outputs

▪ Outputs arranged in two banks of four outputs each

The 8P791208 supports two output banks, each with its own

power supply. All outputs in one bank would generate the same

output frequency, but each output can be individually controlled for

output type or output enable.

▪ Select pins control which input drives which of two output

banks

▪ Controlled by 3-level input pins that are 3.3V tolerant for all

The device can operate over the -40°C to 85°C temperature

range.

core voltages

▪ Output type may be selected from LVPEC, LVDS or

2xLVCMOS

▪ Each bank supports a separate power supply of 3.3V, 2.5V,

or 1.8V

▪ LVCMOS outputs are limited to 125MHz maximum and support

swings of 3.3V, 2.5V, 1.8V, and 1.5V

▪ Individual output enables and output type selection supported

▪ Output noise floor of –158dBc/Hz at 156.25MHz

▪ Core voltage supply of 3.3V, 2.5V, or 1.8V

▪ –40°C to 85°C ambient operating temperature

▪ Lead-free (RoHS 6) QFN-32 (5 x 5mm) packaging

Block Diagram

8P791208 transistor count: 9,703

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May 8, 2018

8P791208 Datasheet

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Principles of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Output Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

LVCMOS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Output Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Supply Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Recommendations for Unused Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Wiring the Differential Input to Accept Single-ended Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3V Differential Clock Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.5V Differential Clock Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

LVDS Driver Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Termination for 3.3V LVPECL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Termination for 2.5V LVPECL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Power Dissipation and Thermal Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Power Consumption Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Current Consumption Data and Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Example Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

LVPECL Power Considerations (700MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

LVDS Power Considerations (700MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

LVCMOS Power Considerations (125MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Dynamic Power Dissipation at fOUT(max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Package Outline Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Marking Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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May 8, 2018

8P791208 Datasheet

Pin Assignments

Figure 1. Pin Assignment for 5mm × 5mm VFQFN Package – Top V ie w

31 30 29 28 27 26 25

32

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

OEB1

QB0

OEA1

QA0

nQB0

QB1

nQA0

QA1

nQA1

V_CCOA

QA2

nQB1

V_CCOB

QB2

nQA2

nQB2

10 11 12 13 14 15 16

9

Pin Descriptions

Table 1. Pin Description

[a]

Number

Name

Type

Description

1

2

OEA1

QA0

Input (PU)

Output

Controls output enable functions for Bank A. LVCMOS/LVTTL input levels.

Positive differential clock output. Included in Bank A. Refer to Output Drivers for

additional details.

3

4

5

nQA0

QA1

Output

Negative differential clock output. Included in Bank A. Refer to Output Drivers for

additional details.

Positive differential clock output. Included in Bank A. Refer to Output Drivers for

additional details.

nQA1

Negative differential clock output. Included in Bank A. Refer to Output Drivers for

additional details.

6

7

V

Power

Output

Output voltage supply for output Bank A.

CCOA

QA2

nQA2

QA3

Positive differential clock output. Included in Bank A. Refer to Output Drivers for

additional details.

8

9

Output

Negative differential clock output. Included in Bank A. Refer to Output Drivers for

additional details.

Positive differential clock output. Included in Bank A. Refer to Output Drivers for

additional details.

10

nQA3

Negative differential clock output. Included in Bank A. Refer to Output Drivers for

additional details.

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May 8, 2018

8P791208 Datasheet

Table 1. Pin Description (Cont.)

[a]

Number

Name

Type

Description

11

12

13

IOA

Input (PU/PD)

Power

Controls output mode functions for Bank A. 3-level input.

Core Logic voltage supply.

V

CC

CLK_SEL

Input (PU/PD)

Input Clock Selection Control pin. 3-level input. This pin’s function is described in the

Input Selection section.

14

15

IOB

Input (PU/PD)

Output

Controls output mode functions for Bank B. 3-level input.

nQB3

Negative differential clock output. Included in Bank B. Refer to Output Drivers for

additional details.

16

17

18

QB3

nQB2

QB2

Output

Positive differential clock output. Included in Bank B. Refer to Output Drivers for

additional details.

Negative differential clock output. Included in Bank B. Refer to Output Drivers for

additional details.

Positive differential clock output. Included in Bank B. Refer to Output Drivers for

additional details.

19

20

V

Power

Output

Output voltage supply for Output Bank B.

CCOB

nQB1

Negative differential clock output. Included in Bank B. Refer to Output Drivers for

additional details.

21

22

23

QB1

Output

Positive differential clock output. Included in Bank B. Refer to Output Drivers for

additional details.

nQB0

QB0

Negative differential clock output. Included in Bank B. Refer to Output Drivers for

additional details.

Positive differential clock output. Included in Bank B. Refer to Output Drivers for

additional details.

24

25

26

OEB1

CLK1

Input (PU)

Input (PD)

Controls output enable functions for Bank B. LVCMOS/LVTTL input levels.

Non-inverting differential clock input.

nCLK1

Input (PU/PD)

Inverting differential clock input. V /2 when left floating (set by the internal pull-up and

CC

pulldown resistors).

27

28

29

30

31

V

Power

Input (PU)

Power

Core Logic voltage supply.

CC

OEB0

OEA0

Controls output enable functions for Bank B. LVCMOS/LVTTL input levels.

Controls output enable functions for Bank A. LVCMOS/LVTTL input levels.

Core Logic voltage supply.

V

CC

nCLK0

Input (PU/PD)

Inverting differential clock input. V /2 when left floating (set by the internal pull-up and

CC

pull-down resistors).

32

CLK0

Input (PD)

Ground

Non-inverting differential clock input.

Must be connected to GND.

EP

Exposed Pad

[a] Pull-up (PU) and pull-down (PD) resistors are indicated in parentheses. Pull-up and pull-down refers to internal input resistors.

See Table 10, DC Input Characteristics, for typical values.

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May 8, 2018

8P791208 Datasheet

Principles of Operation

Input Selection

The 8P791208 supports two input references: CLK0 and CLK1 that may be driven with differential or single-ended clock signals. Either

may be used as the source frequency for either or both output banks under control of the CLK_SEL input pin.

Table 2. Input Selection Control

CLK_SEL

Description

High

Banks A and B both driven from CLK1

[a]

Middle

Bank A driven from CLK0 & Bank B driven from CLK1

Banks A and B both driven from CLK0

Low

[a] A ‘middle’ voltage level is defined in Table 11. Leaving the input pin open will also

generate this level via a weak internal resistor network.

Output Drivers

The QA[0:3] and QB[0:3] clock outputs are provided with pin-controlled output drivers. The following table shows how each bank can be

controlled. Each bank is separately controlled and all outputs within a single bank will behave the same way.

Table 3. Output Mode Control

IOx

Output Bank Mode Function

All outputs in the bank are LVDS

High

Middle

Low

All outputs in the bank are LVPECL

All outputs in the bank are LVCMOS

The operating voltage ranges of each output is determined by its independent output power pin (V_CCOAor V_CCOB) and thus each can

have different output voltage levels. Output voltage levels of 1.8V, 2.5V or 3.3V are supported for differential operation and LVCMOS

operation. In addition, LVCMOS output operation supports 1.5V V_CCO.

LVCMOS Operation

When a given output is configured to provide LVCMOS levels, then both the Q and nQ outputs will toggle at the selected output

frequency. All the previously described configuration and control apply equally to both outputs. Frequency, voltage levels and enable /

disable status apply to both the Q and nQ pins. When configured as LVCMOS, the Q & nQ outputs are in-phase relative to one another.

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May 8, 2018

8P791208 Datasheet

Output Enable Control

The 8P791208 has separate pins that control the output enable behavior for each bank as shown in the following table.

Table 4. Output Enable Control

Output Enable Function

OEx1

OEx0

Qx3

Qx2

Qx1

Qx0

High

Low

High

Low

High

Low

On

Hi-Z

On

Hi-Z

On

Hi-Z

Absolute Maximum Ratings

NOTE: The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to

the device. Functional operation of the 8P79208 at absolute maximum ratings is not implied. Exposure to absolute maximum rating

conditions may affect device reliability.

Table 5. Absolute Maximum Ratings

Item

Rating

[a]

Supply Voltage, V

to GND

3.63V

CCX

Inputs OEA[1:0], OEB[1:0], IOA, IOB, CLK_SEL, CLK0, nCLK0,

CLK1, nCLK1

–0.5V to V  0.5V

CC

Outputs, I QA[0:3], nQA[0:3]; QB[0:3], nQB[0:3]

O

Continuous Current

Surge Current

40mA

60mA

[b]

Outputs, V QA[0:3], nQA[0:3]; QB[0:3], nQB[0:3]

–0.5V to V

125°C

 0.5V

O

CCOx

Maximum Junction Temperature

Storage Temperature, T

–65°C to 150°C

STG

Lead Temperature (Soldering, 10s)

260°C

[a] V_CCXdenotes V_CC, V_CCOA, or V_CCOB.

[b] V_CCOXdenotes V_CCOAor V_CCOB.

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May 8, 2018

8P791208 Datasheet

Supply Voltage Characteristics

Table 6. Power Supply Characteristics, V_CC= V_CCOA= V_CCOB= 3.3V ±5%, V_EE= 0V, T_A= –40°C to 85°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V

Core supply voltage

Output supply voltage

3.135

3.3

3.465

V

CC

V

CC

CCOA,

V

CCOB

I

Core supply current

Device configured for LVDS logic levels

22

25

153

mA

CC

[a]

I

Output supply current

All outputs configured for LVDS logic levels;

outputs unloaded

136

CCOX

[a] Internal dynamic switching current at maximum f_OUTis included.

Table 7. Power Supply Characteristics, V_CC= V_CCOA= V_CCOB= 2.5V ±5%, V_EE= 0V, T_A= –40°C to 85°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V

Core supply voltage

Output supply voltage

2.375

2.5

2.625

V

CC

V

CC

CCOA,

V

CCOB

I

Core supply current

Device configured for LVDS logic levels

21

24

151

mA

CC

[a]

I

Output supply current

All outputs configured for LVDS logic levels;

outputs unloaded

135

CCOX

[a] Internal dynamic switching current at maximum f_OUTis included.

Table 8. Power Supply Characteristics, V_CC= V_CCOA= V_CCOB= 1.8V ±5%, V_EE= 0V, T_A= –40°C to 85°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V

Core supply voltage

Output supply voltage

1.71

1.8

1.89

V

CC

V

CC

CCOA,

V

CCOB

I

Core supply current

Device configured for LVDS logic levels

18

20

137

mA

CC

[a]

I

Output supply current

All outputs configured for LVDS logic levels;

outputs unloaded

122

CCOX

[a] Internal dynamic switching current at maximum f_OUTis included.

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May 8, 2018

8P791208 Datasheet

Table 9. Typical Output Supply Current, V_CCOA= V_CCOB= 3.3V±5%, 2.5V±5% or 1.8V±5%, V_EE= 0V,

T_A= –40°C to 85°C

[c]

V

= 3.3V 5%

V

^[c]= 2.5V 5%

V

= 1.8V 5%

V

CCOx

= 1.5V 5%

CCOx

I

Bank B All outputs

77

52

37

23

52

37

23

46

41

40

46

41

40

76

49

36

76

49

36

51

34

19

51

34

19

27

25

21

27

25

21

69

46

32

46

32

25

20

25

20

21

17

21

17

mA

CCOB

output

supply

current

enabled

2 outputs

enabled

49

42

77

49

42

49

28

69

49

28

No outputs

enabled

Bank A All outputs

CCOA

output

supply

current

enabled

2 outputs

enabled

No outputs

enabled

[a] Internal dynamic switching current at maximum f_OUTis included.

[b] Tested with outputs unloaded.

[c] V_CCOxdenotes V_CCOA, V_CCOB

.

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May 8, 2018

8P791208 Datasheet

DC Electrical Characteristics

Table 10. Pin Characteristics

[a]

Symbol

Parameter

Input capacitance

Test Conditions

Minimum

Typical

Maximum

Units

C

2

pF

k

IN

R

Input pull-up resistor

51

PULLUP

R

Input pull-down resistor

PULLDOWN

LVCMOS output type selected

= 3.3V +5%

24

15

25

48



V

CCOx

LVCMOS output type selected

= 2.5V +5%

QA[3:0],

nQA[3:0],

QB[3:0],

nQB[3:0]

V

CCOx

Output

impedance

R

OUT

LVCMOS output type selected

= 1.8V +5%

V

CCOx

LVCMOS output type selected

V

= 1.5V +5%

CCOx

LVPECL

LVDS

4.2

5.8

4.7

5.2

pF

= 3.465V or 2.625V

Power dissipation

capacitance

(per output pair)

LVCMOS

LVPECL

LVDS

C

PD

QA[3:0], nQA[3:0],

QB[3:0], nQB[3:0]

V

= 1.89V

CCOx

LVCMOS

= 1.89V or 1.545V

[a] V_CCOxrefers to V_CCOAfor QA[3:0], nQA[3:0], or V_CCOBfor QB[3:0], nQB[3:0].

Table 11. LVCMOS/LVTTL Control / Status Signals DC Characteristics for 3-level Pins, V_EE= 0V,

T_A= –40°C to 85°C

Symbol Parameter

Signals

Test Conditions

= 3.3V

Minimum

Typical

Maximum

Units

V

Input

IOA, IOB,

CLK_SEL

V

0.85  V

0.45  V

–0.3

3.63

2.625

1.89

V

IH

CC

high voltage

= 2.5V

= 1.8V

= 3.3V

= 2.5V

= 1.8V

= 3.3V

= 2.5V

= 1.8V

V

Input

IOA, IOB,

CLK_SEL

0.55  V

0.15  V

IM

CC

middle

voltage

[a]

V

Input

OEA[1:0], OEB[1:0]

IOA, IOB, CLK_SEL

IL

low voltage

–0.3

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May 8, 2018

8P791208 Datasheet

Table 11. LVCMOS/LVTTL Control / Status Signals DC Characteristics for 3-level Pins, V_EE= 0V,

T_A= –40°C to 85°C

Symbol Parameter

Signals

Test Conditions

= V = 3.465V or 2.625V or

Minimum

Typical

Maximum

Units

I

Input

IOA, IOB,

CLK_SEL

V

150

A

IH

CC

IN

high current

1.89V

I

Input

middle current

IOA, IOB,

CLK_SEL

V

= 3.465V or 2.625V or 1.89V,

A

IM

CC

IN

= V /2

CC

I

Input

low current

OEA[1:0], OEB[1:0]

IOA, IOB, CLK_SEL

V

= 3.465V or 2.625V or 1.89V,

= 0V

–150

IL

CC

IN

[a] For 3-level input pins, a mid-level voltage is used to select the 3^rdstate. This voltage will be maintained by a weak internal pull-up / pull-down

network for each pin to select this state if the pin is left open. It is recommended that any external resistor networks used to select a middle-level

input voltage be terminated to the device’s core V_CCvoltage level.

Table 12. LVCMOS/LVTTL Control / Status Signals DC Characteristics for 2-Level Pins, V_EE= 0V,

T_A= –40°C to 85°C

Symbol Parameter

Signals

Test Conditions

= 3.3V

Minimum

Typical

Maximum

Units

V

Input

OEA[1:0], OEB[1:0]

V

2

3.63

2.625

1.89

0.8

V

IH

CC

high voltage

= 2.5V

= 1.8V

= 3.3V

= 2.5V

= 1.8V

1.7

0.65  V

–0.3

V

CC

V

Input

OEA[1:0], OEB[1:0]

V

IL

low voltage

–0.3

0.7

V

–0.3

0.35  V

V

CC

I

Input

OEA[1:0], OEB[1:0]

= V = 3.465V or 2.625V or

150

A

IH

IN

high current

1.89V

I

Input

V

= V = 3.465V or 2.625V or

–150

A

IL

CC

IN

low current

1.89V

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May 8, 2018

8P791208 Datasheet

Table 13. Differential Input DC Characteristics, V_CC= 3.3V±5%, 2.5V±5% or 1.8V±5%, V_EE= 0V,

T_A= –40°C to 85°C

Symbol Parameter

Test Conditions

= V = 3.465V or 2.625V

Minimum

Typical

Maximum

Units

[a]

I

Input high current

Input low current

CLKx, nCLKx

[a]

V

150

A

V

IH

CC

IN

I

CLKx

= 3.465V or 2.625V, V = 0V

–5

IL

IN

[a]

nCLKx

= 3.465V or 2.625V, V = 0V

–150

0.15

IN

[b]

V

Peak-to-peak voltage

1.3

PP

[b], [c]

V

Common mode input voltage

V

V – 1.2

CC

V

CMR

EE

[a] CLKx denotes CLK0, CLK1. nCLKx denotes nCLK0, nCLK1.

[b] V_ILshould not be less than –0.3V. V_IHshould not be higher than V_CC

[c] Common mode voltage is defined as the cross-point.

.

Table 14. LVPECL DC Characteristics, V_CC= 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, V_EE= 0V, T_A= -40°C to

+85°C

Symbol

Parameter

Test Conditions

Min

- 1.3

Typ

Max

V - 0.8

CCOX

Unit

V

Output High Voltage

Qx, nQx

V

mV

OH

CCOX

V

Output Low Voltage

V

- 2.05

V - 1.75

CCOX

mV

OL

CCOX

[a]

Table 15. LVDS DC Characteristics, V_CC= 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, V_CCOx

= 3.3V ±5%,

V_EE= 0V, T_A= –40°C to 85°C

Symbol Parameter

Differential output voltage

magnitude change

Test Conditions

Minimum

Typical

Maximum

Units

[b]

V

Qx, nQx

Terminated 100 across

Qx and nQx

247

465

50

mV

V

OD

V

V

OD

V

Offset voltage

magnitude change

1.1

1.375

50

OS

V

V

mV

OS

[a] V_CCOxdenotes V_CCOA, V_CCOB

.

[b] Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.

nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3.

[a]

Table 16. LVDS DC Characteristics, V_CC= 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, V_CCOx

= 2.5V ±5%,

V_EE= 0V, T_A= –40°C to 85°C

Symbol Parameter

Differential output voltage

magnitude change

Test Conditions

Minimum

Typical

Maximum

Units

[b]

V

Qx, nQx

Terminated 100 across

Qx and nQx

247

465

50

mV

V

OD

V

V

OD

V

Offset voltage

magnitude change

1.1

1.375

50

OS

V

V

mV

OS

[a] V_CCOxdenotes V_CCOA, V_CCOB

.

[b] Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.

nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3.

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May 8, 2018

8P791208 Datasheet

[a]

Table 17. LVDS DC Characteristics, V_CC= 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, V_CCOx

= 1.8V ±5%,

V_EE= 0V, T_A= –40°C to 85°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

[b]

V

Differential output voltage

Qx, nQx

Terminated 100

across

Qx and nQx

247

454

50

mV

V

OD

V

V

magnitude change

OD

V

Offset voltage

magnitude change

1.1

1.375

50

OS

V

V

mV

OS

[a] V_CCOxdenotes V_CCOA, V_CCOB

.

[b] Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.

nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3.

[a]

Table 18. LVCMOS Clock Outputs DC Characteristics, V_CCOx

= 3.3V±5%, 2.5V±5% or 1.8V±5%,

V_EE= 0V, T_A= –40°C to 85°C

[a]

V

3.3V 5%

=

V

2.5V 5%

=

CCOx

[a]

V

= 1.8V 5%

Typ Max

V

= 1.5V 5%

Typ Max

CCOx

Test

Symbol Parameter Conditions Min Typ Max Min Typ Max

Min

Units

V

Output

I

= –8mA 2.4

1.8

V

0.45

V

0.38

V

OH

CC

high voltage

[b]

Qx, nQx

V

Output

I

= 8mA

0.8

0.6

0.45

0.38

V

OL

low voltage

[b]

Qx, nQx

[a] V_CCOxdenotes V_CCOA, V_CCOB

.

[b] Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3.

Table 19. Input Frequency Characteristics, V_CC= 3.3V±5%, 2.5V±5% or 1.8V±5%, V_EE= 0V,

T_A= –40°C to 85°C

Symbol Parameter

Input Frequency

Test Conditions

Minimum

Typical

Maximum

Units

[a]

f

CLKx, nCLKx

1Hz

700MHz

IN

[b]

idc

[a] CLKx denotes CLK0, CLK1. nCLKx denotes nCLK0, nCLK1.

[b] Any deviation from a 50% / 50% duty cycle on the input may be reflected in the output duty cycle.

Input duty cycle

50

%

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May 8, 2018

8P791208 Datasheet

AC Electrical Characteristics

[a]

Table 20. AC Characteristics, V_CC= 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, V_CCOx

= 3.3V ±5%, 2.5V ±5% or

1.8V ±5%, V_EE= 0V, T_A= –40°C to 85°C

[b]

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

f

Output

frequency

LVDS, LVPECL

LVCMOS

1PPS

700MHz

OUT

Output

1PPS

125MHz

frequency

t

Propagation

delay

LVCMOS

LVDS

V

= 3.3V ±5%

DDOx

1.25

0.85

125

150

175

200

250

200

300

200

2.25

2.0

700

550

575

600

775

915

950

1400

60

ns

ps

%

PD

LVPECL

t / t

Output rise and LVPECL

fall times

20% to 80%

R

F

LVDS

20% to 80%, V

= 3.3V

= 2.5V

= 1.8V

= 3.3V

= 2.5V

= 1.8V

= 1.5V

CCOx

LVCMOS

[c],

[f]

t (b)

Bank skew

LVPECL,LVDS

sk

[d], [e]

[g]

LVCMOS

100

55

odc

Output

duty cycle

LVPECL, LVDS

LVCMOS

V

= 3.3V or 2.5V

= 1.8V

45

43

45

43

40

CCOx

[h], [i]

57

%

= 3.3V or 2.5V

= 1.8V

55

57

%

= 1.5V

60

MUX

Mux Isolation

Noise Floor

70

dB

ISOL

Offset >10MHz from156.25MHz carrier

LVPECL, LVDS

157

dBc/Hz

[a] V_CCOxdenotes V_CCOA, V_CCOB

.

[b] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted

in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been

reached under these conditions.

[c] This parameter is guaranteed by characterization. Not tested in production.

[d] This parameter is defined in accordance with JEDEC Standard 65.

[e] Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.

[f] Measured at the output differential crosspoint.

[g] Measured at V_CCOx/2 of the rising edge.

[h] Measured using 50% /50% duty cycle on input reference.

[i] Measurements taken for the following output frequencies:

LVDS and LVPECL: 50MHz, 100MHz, 156.25MHz, 250MHz, 312.5MHz, 491.52MHz, 700MHz

LVCMOS: 25MHz, 50MHz, 100MHz, 125MHz.

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May 8, 2018

8P791208 Datasheet

[a]

Table 21. Typical Additive Jitter, V_CC= 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, V_CCOx

= 3.3V ±5%, 2.5V ±5%,

1.8V ±5% or 1.5V ±5% (1.5V only supported for LVCMOS outputs), V_EE= 0V, T_A= –40°C to 85°C

[b]

Symbol

t (f)

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

RMS

LVPECL

f

= 156.25MHz,

V

= 3.3V or 2.5V

= 1.8V

64

81

fs

jit

OUT

CCOx

Additive Jitter

(Random)

Integration Range:

12kHz to 20MHz

LVDS

f

= 156.25MHz,

V

= 3.3V or 2.5V

= 1.8V

70

fs

OUT

CCOx

Integration Range:

12kHz to 20MHz

114

LVCMOS

f

= 125MHz,

V

= 3.3V or 2.5V

= 1.8V

105

140

192

fs

OUT

CCOx

Integration Range:

12kHz to 20MHz

= 1.5V

[a] V_CCOxdenotes V_CCOA, V_CCOB

.

[b] All outputs configured for the specific output type, as shown in the table.

Applications Information

Recommendations for Unused Input and Output Pins

Inputs

CLK/nCLK Inputs

For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for

additional protection, a 1k resistor can be tied from CLK to ground.

LVCMOS LVTTL Level Control Pins

All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A

1k resistor can be used.

LVCMOS 3-level I/O Control Pins

These pins are 3-level pins and if left unconnected this is interpreted as a valid input selection option (Middle).

Outputs

LVCMOS Outputs

All unused LVCMOS outputs can be left floating. It is recommended that there is no trace attached.

LVPECL Outputs

All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair

should either be left floating or terminated.

LVDS Outputs

All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace

attached.

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May 8, 2018

8P791208 Datasheet

Wiring the Differential Input to Accept Single-ended Levels

Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage V₁= V_CC/2 is generated by the

bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as

close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V₁in the center of the input voltage

swing. For example, if the input clock swing is 2.5V and V_CC= 3.3V, R1 and R2 value should be adjusted to set V₁at 1.25V. The values

below are for when both the single ended swing and V_CCare at the same voltage. This configuration requires that the sum of the output

impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at

the input will attenuate the signal in half.

This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50

applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker

LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the

differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced while maintaining an edge rate

faster than 1V/ns. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For

single-ended applications, the swing can be larger, however V_ILcannot be less than –0.3V and V_IHcannot be more than V_CC 0.3V.

Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for

debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal.

Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

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May 8, 2018

8P791208 Datasheet

3.3V Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other differential signals. Both V_SWINGand V_OHmust meet the V_PPand

_CMRinput requirements. Figure 3 to Figure 7 show interface examples for the CLK/nCLK input driven by the most common driver types.

V

The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver

termination requirements. For example, in Figure 3, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an

LVHSTL driver from another vendor, use their termination recommendation.

Figure 3. CLKx/nCLKx Input Driven by an

IDT Open Emitter LVHSTL Driver

Figure 4. CLKx/nCLKx Input Driven by a

3.3V LVPECL Driver

3.3V

1.8V

Zo = 50Ω

CLK

nCLK

Differential

Input

LVHSTL

R1

50Ω

R2

50Ω

IDT

LVHSTL Driver

Figure 5. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 6. CLK/nCLK Input Driven by a

3.3V LVDS Driver

3.3V

*R3

CLK

nCLK

Differential

Input

*R4

HCSL

Figure 7. CLK/nCLK Input Driven by a

3.3V HCSL Driver

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May 8, 2018

8P791208 Datasheet

2.5V Differential Clock Input Interface

CLKx/nCLKx accepts LVDS, LVPECL, LVHSTL, HCSL and other differential signals. Both V_SWINGand V_OHmust meet the V_PPand V_CMR

input requirements. Figure 8 to Figure 12 show interface examples for the CLKx/nCLKx input driven by the most common driver types.

The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver

termination requirements. For example, in Figure 8, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an

LVHSTL driver from another vendor, use their termination recommendation.

Figure 8. CLKx/nCLKx Input Driven by an

IDT Open Emitter LVHSTL Driver

Figure 9. CLKx/nCLKx Input Driven by a

2.5V LVPECL Driver

2.5V

1.8V

Zo = 50฀

CLK

nCLK

Differential

Input

LVHSTL

R1

50฀

R2

50฀

IDT Open Emitter

LVHSTL Driver

Figure 10. CLK/nCLK Input Driven by a

2.5V LVPECL Driver

Figure 11. CLK/nCLK Input Driven by a

2.5V LVDS Driver

Figure 12. CLK/nCLK Input Driven by a

2.5V HCSL Driver

2.5V

Zo = 50Ω

*R3

33Ω

CLK

Zo = 50Ω

nCLK

Differential

Input

*R4

33Ω

HCSL

R1

50Ω

R2

50Ω

*Optional – R3 and R4 can be 0Ω

17

May 8, 2018

8P791208 Datasheet

LVDS Driver Termination

For a general LVDS interface, the recommended value for the termination impedance (Z_T) is between 90 and 132. The actual value

should be selected to match the differential impedance (Z₀) of your transmission line. A typical point-to-point LVDS design uses a 100

parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection

issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS

compliant devices with two types of output structures: current source and voltage source.

The standard termination schematic as shown in Figure 13 can be used with either type of output structure. Figure 14, which can also be

used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value

should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is

current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and

common-mode input range should be verified for compatibility with the output.

Figure 13. Standard LVDS Termination

Figure 14. Optional LVDS Termination

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May 8, 2018

8P791208 Datasheet

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

The differential output is a low impedance follower output that generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50

transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion.

Figure 15 and Figure 16 show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist

and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component

process variations.

Figure 15. 3.3V LVPECL Output Termination

Figure 16. 3.3V LVPECL Output Termination

3.3V

R3

R4

125฀

3.3V

Z_o= 50฀

+

_

Input

R1

84฀

R2

84฀

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May 8, 2018

8P791208 Datasheet

Termination for 2.5V LVPECL Outputs

Figure 17 and Figure 18 show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to

_CCO– 2V. For V_CCO= 2.5V, the V_CCO– 2V is very close to ground level. The R3 in Figure 18 can be eliminated and the termination is

V

shown in Figure 19.

Figure 17. 2.5V LVPECL Driver Termination Example

2.5V

V_CCO= 2.5V

R1

R3

250

50฀

+

–

2.5V LVPECL Driver

R2

62.5

R4

62.5

Figure 18. 2.5V LVPECL Driver Termination Example

2.5V

V_CCO= 2.5V

50฀

+

–

2.5V LVPECL Driver

R1

50

R2

50

Figure 19. 2.5V LVPECL Driver Termination Example

2.5V

V_CCO= 2.5V

50฀

+

50฀

–

2.5V LVPECL Driver

R1

50

R2

50

R3

18

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May 8, 2018

8P791208 Datasheet

Power Dissipation and Thermal Considerations

The 8P791208 is a multi-functional, high speed device that targets a wide variety of clock frequencies and applications. Since this device

is highly programmable with a broad range of features and functionality, the power consumption will vary as each of these features and

functions is enabled.

The 8P791208 device was designed and characterized to operate within the ambient industrial temperature range of T_A= -40°C to 85°C.

The ambient temperature represents the temperature around the device, not the junction temperature. When using the device in extreme

cases, such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe

and reliable junction temperature. Extreme care must be taken to avoid exceeding 125°C junction temperature.

The power calculation examples below were generated using a maximum ambient temperature and supply voltage. For many

applications, the power consumption will be much lower. Please contact IDT technical support for any concerns on calculating the power

dissipation for your own specific configuration.

Power Domains

The 8P791208 device has a number of separate power domains that can be independently enabled and disabled via register accesses

(all power supply pins must still be connected to a valid supply voltage). Figure 20 indicates the individual domains and the associated

power pins.

Figure 20. 8P791208 Power Domains

Power Consumption Calculation

Determining total power consumption involves several steps:

1. Determine the power consumption using maximum current values for core voltage from Table 6 to Table 9 for the appropriate case of

how many banks or outputs are enabled.

2. Determine the nominal power consumption of each enabled output path.

a. This consists of a base amount of power that is independent of operating frequency, as shown in Table 22 to Table 28 (depending

on the chosen output protocol).

b. Then there is a variable amount of power that is related to the output frequency. This can be determined by multiplying the output

frequency by the FQ_Factor shown in Table 22 to Table 28.

3. All of the above totals are then summed.

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May 8, 2018

8P791208 Datasheet

Thermal Considerations

Once the total power consumption has been determined, it is necessary to calculate the maximum operating junction temperature for the

device under the environmental conditions it will operate in. Thermal conduction paths, air flow rate and ambient air temperature are

factors that can affect this. The thermal conduction path refers to whether heat is to be conducted away via a heat-sink, via airflow or via

conduction into the PCB through the device pads (including the ePAD). Thermal conduction data is provided for typical scenarios in

Table 30. Please contact IDT for assistance in calculating results under other scenarios.

Current Consumption Data and Equations

Table 22. 3.3V LVDS Output Calculation Table

FQ_Factor

(mA/MHz)

LVDS

Base_Current (mA)

Bank A

Bank B

0.08

25.309

Table 23. 2.5V LVDS Output Calculation Table

FQ_Factor

(mA/MHz)

LVDS

Base_Current (mA)

Bank A

Bank B

0.05

35.476

Table 24. 1.8V LVDS Output Calculation Table

FQ_Factor

(mA/MHz)

LVDS

Base_Current (mA)

Bank A

Bank B

0.05

35.330

Table 25. 3.3V LVCMOS Output Calculation Table

LVCMOS

Base_Current (mA)

Bank A

Bank B

31.522

Table 26. 2.5V LVCMOS Output Calculation Table

LVCMOS

Base_Current (mA)

Bank A

Bank B

18.665

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May 8, 2018

8P791208 Datasheet

Table 27. 1.8V LVCMOS Output Calculation Table

LVCMOS

Base_Current (mA)

Bank A

Bank B

14.704

Table 28. 1.5V LVCMOS Output Calculation Table

LVCMOS

Base_Current (mA)

Bank A

Bank B

12.522

Applying the values to the following equation will yield output current by frequency:

Qx Current (mA) = FQ_Factor  Frequency (MHz)  Base_Current

where:

Qx Current is the specific output current according to output type and frequency

FQ_Factor is used for calculating current increase due to output frequency

Base_Current is the base current for each output path independent of output frequency

The second step is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient, using the

following equation:

T_J= T_A (_JA Pd_total

)

where:

T_Jis the junction temperature (°C)

T_Ais the ambient temperature (°C)

_JAis the thermal resistance value from Table 30, dependent on ambient airflow (°C/W).

Pd_totalis the total power dissipation of the 8P791208 under usage conditions, including power dissipated due to loading (W).

Note: For LVPECL outputs the power dissipation through the load is assumed to be 27.95mW. When selecting LVCMOS outputs, power

dissipation through the load will vary based on a variety of factors including termination type and trace length. For these examples, power

dissipation through loading will be calculated using C_PD(located in Table 10) and output frequency:

2

Pd_OUT= C_PD f_OUT V_CCO

where:

Pd_outis the power dissipation of the output (W)

C_PDis the power dissipation capacitance (pF)

f

_OUTis the output frequency of the selected output (MHz)

V_CCOis the voltage supplied to the appropriate output (V)

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May 8, 2018

8P791208 Datasheet

Example Calculations

Table 29. Example 1 – Common Customer Configuration (3.3V Core Voltage)

Circuit

Configuration

Frequency (MHz)

V

CCO

Bank A

Bank B

LVDS

125

3.3V

Core supply current, I_CC= 25mA (maximum)

▪ Output supply current, Bank A current = 0.08mA x 125MHz + 30mA = 40mA

▪ Output supply current, Bank B current = 0.08mA x 125MHz + 30mA = 40mA

Total device current = 25mA + 40mA + 40mA = 105mA

Total device power = 3.465V  105mA = 363.825mW or 0.364W

With an ambient temperature of 85°C and no airflow, the junction temperature is:

▪ T_J= 85°C + 35.23°C/W  0.364W = 97.82°C

LVPECL Power Considerations (700MHz)

This section provides information on power dissipation and junction temperature for the 8P791208.

Equations and example calculations are also provided.

4. Power Dissipation.

The total power dissipation for the 8P791208 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V_CC= 3.465V, which gives worst case results.

Note: I_{EE_MAX}@ 85°C is 124mA

For information on calculating power dissipated in the load, see Calculations and Equations.

▪ Power (core)_MAX= V_{CC_MAX} I_{EE_MAX}= 3.465V  124mA = 429.66mW

▪ Power (outputs)_MAX= 27.95mW/Loaded Output pair

If all outputs are loaded, the total power is 8  27.95mW = 223.6mW

▪ Total Power__MAX= 429.66W  223.6mW = 653.26mW

5. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that

the bond wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA Pd_total + T_A

Tj = Junction Temperature

_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow

and a multi-layer board, the appropriate value is 35.23°C/W per Table 30.

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May 8, 2018

8P791208 Datasheet

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C  0.653W  35.23°C/W = 108°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the

type of board (multi-layer).

Table 30. Thermal Resistance _JAfor 32-Lead VFQFN, Forced Convection



by Velocity

0

JA

Meters per Second

1

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

35.23°C/W

31.6°C/W

30.0°C/W

6. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination

are shown in Figure 21.

Figure 21. LVPECL Driver Circuit and Termination

V_CCO

Q1

V_OUT

RL

50Ω

V_CCO- 2V

To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage

of V_CCO– 2V.

▪ For logic high, V_OUT= V_{OH_MAX}= V_{CCO_MAX} 0.8V

(V_{CCO_MAX} V_{OH_MAX}) = 0.8V

▪ For logic low, V_OUT= V_{OL_MAX}= V_{CCO_MAX} 1.75V

(V_{CCO_MAX} V_{OL_MAX}) = 1.75V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

25

May 8, 2018

8P791208 Datasheet

Pd_H = [(V_{OH_MAX} (V_{CCO_MAX} 2V))/R_L]  (V_{CCO_MAX} V_{OH_MAX}) = [(2V  (V_{CCO_MAX} V_{OH_MAX}))/R_L]  (V_{CCO_MAX} V_{OH_MAX}) =

[(2V – 0.8V)/50] * 0.8V = 19.2mW

Pd_L = [(V_{OL_MAX} (V_{CCO_MAX} 2V))/R_L]  (V_{CCO_MAX} V_{OL_MAX}) = [(2V  (V_{CCO_MAX} V_{OL_MAX}))/R_L] (V_{CCO_MAX} V_{OL_MAX}) =

[(2V – 1.75V)/50]  1.75V = 8.75mW

Total Power Dissipation per output pair = Pd_H  Pd_L = 27.95mW

LVDS Power Considerations (700MHz)

This section provides information on power dissipation and junction temperature for the 8P791208.

Equations and example calculations are also provided.

7. Power Dissipation.

The total power dissipation for the 8P791208 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V_CC= 3.465V, which gives worst case results.

▪ Power (core)_MAX= V_{CC_MAX} I_{CC_MAX}= 3.465V  25mA = 86.625mW

▪ Power (outputs)_MAX= V_{CCOx_MAX} I_{CCO_MAX}= 3.465V  153mA = 530.145mW

▪ Total Power__MAX= 86.625W  530.145mW = 616.77mW

8. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that

the bond wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA Pd_total + T_A

Tj = Junction Temperature

_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow

and a multi-layer board, the appropriate value is 35.23°C/W per Table 30.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C  0.617W  35.23°C/W = 107°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the

type of board (multi-layer).

26

May 8, 2018

8P791208 Datasheet

LVCMOS Power Considerations (125MHz)

This section provides information on power dissipation and junction temperature for the 8P791208.

Equations and example calculations are also provided.

9. Power Dissipation.

The total power dissipation for the 8P791208 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V_CC= 3.465V, which gives worst case results.

▪ Power (core)_MAX= V_{CC_MAX} I_{CC_MAX}= 3.465V  63mA = 217.81mW

Dynamic Power Dissipation at f_OUT(max)

Total Power:

Total Power (F_{OUT_MAX}) = [(C_PD N)  Frequency  (V_CCO)²] = [(0.58pF  2)  125MHz  (3.456V)²] = 13.92722mW per

output

N = number of outputs

Dynamic Power Dissipation:

= Static Power  Dynamic Power Dissipation

= 217.81mW  13.927mW

= 231.737mW

10. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that

the bond wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA Pd_total + T_A

Tj = Junction Temperature

_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow

and a multi-layer board, the appropriate value is 35.23°C/W per Table 30.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C  0.232W  35.23°C/W = 93.27°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the

type of board (multi-layer).

Package Outline Draw ings

The package outline drawings are appended at the end of this document and are accessible from the link below. The package information

is the most current data available.

www.idt.com/document/psc/32-vfqfpn-package-outline-drawing-50-x-50-x-090-mm-body-epad-315-x-315-mm-nlg32p1

27

May 8, 2018

8P791208 Datasheet

Marking Diagram

1. IDT

2. Line 2 and line 3 indicates the part number.

3. Line 3:

▪ “#” indicates stepping.

▪ “YYWW” indicates the date code (YY are the last two digits of the year, and

“WW” is a work week number that the part was assembled.

▪ “$” indicates the mark code.

Ordering Information

Orderable Part Number

Marking

Package

Carrier Type

Temperature

8P791208NLGI

8P791208NLGI8

IDT8P791208NLGI

32-lead VFQFN, Lead Free

Tray

–40°C to 85°C

Tape and Reel, Pin 1

Orientation: EIA-481-C

8P791208NLGI/W

IDT8P791208NLGI

32-lead VFQFN, Lead Free

Tape and Reel, Pin 1

Orientation: EIA-481-D

–40°C to 85°C

Table 31. Pin 1 Orientation in Tape and Reel Packaging

Part Number Suffix

Pin 1 Orientation

Illustration

NLGI8

Quadrant 1 (EIA-481-C)

CARRIER TAPE TOPSIDE

(Round Sprocket Holes)

Correct Pin 1 ORIENTATION

USER DIRECTION OF FEED

NLGI/W

Quadrant 2 (EIA-481-D)

CARRIER TAPE TOPSIDE

(Round Sprocket Holes)

Correct Pin 1 ORIENTATION

USER DIRECTION OF FEED

28

May 8, 2018

8P791208 Datasheet

Revision History

Date

Description of Change

▪ Updated the propagation delay minimum and maximum numbers for LVCMOS in Table 20

▪ Updated the Package Outline Drawings; however, no technical changes

May 8, 2018

November 5, 2017

August 23, 2017

November 28, 2016

▪ Added t symbol to Table 20

PD

▪ Added Table 14

▪ Updated the package outline drawings. No mechanical changes.

Initial release.

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA

www.IDT.com

Sales

Tech Support

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

www.IDT.com/go/support

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,

without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same

way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability

of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not

convey any license under intellectual property rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-

sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property

29

May 8, 2018

32-VFQFPN, Package Outline Drawing

5.0 x 5.0 x 0.90 mm Body, Epad 3.15 x 3.15 mm.

NLG32P1, PSC-4171-01, Rev 02, Page 1

ꢀ,QWHJUDWHGꢀ'HYLFHꢀ7HFKQRORJ\ꢁꢀ,QFꢂ

32-VFQFPN, Package Outline Drawing

5.0 x 5.0 x 0.90 mm Body, Epad 3.15 x 3.15 mm.

NLG32P1, PSC-4171-01, Rev 02, Page 2

Package Revision History

Description

Date Created Rev No.

April 12, 2018

Feb 8, 2016

Rev 02 New Format

Rev 01 Added "k: Value

ꢀ,QWHJUDWHGꢀ'HYLFHꢀ7HFKQRORJ\ꢁꢀ,QFꢂ

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IDT	8P73S674	[ Clock signal division and distribution ]	15 页
IDT	8P73S674NLGI	[ 1.8V LVPECL Clock Divider ]	15 页
IDT	8P73S674NLGI8	[ 1.8V LVPECL Clock Divider ]	15 页
IDT	8P73S674_16	[ 1.8V LVPECL Clock Divider ]	15 页
IDT	8P791208	[ Low Additive Jitter 2:8 Buffer with CMOS/ Differential Outputs ]	32 页
IDT	8P791208NLGI	[ Low Additive Jitter 2:8 Buffer with CMOS/ Differential Outputs ]	32 页
IDT	8P791208NLGI/W	[ Low Additive Jitter 2:8 Buffer with CMOS/ Differential Outputs ]	32 页
IDT	8P791208NLGI8	[ Low Additive Jitter 2:8 Buffer with CMOS/ Differential Outputs ]	32 页
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