AZP81
APPLICATION
The AZP81 is a “filter-based” oscillator gain stage and multiplier. Generating a spectrum of harmonics from a sine-
wave input, an external bandpass filter selects the desired harmonic.
A crystal or SAW (with associated passive discrete components) is connected between D and Q¯ (pins 1 and 16,
respectively) to form an high stability oscillator stage. Alternatively, an external Colpitts, Pierce or similar sine-
wave oscillator may be fed into D (pin 1) to drive the AZP81. In this case, input amplitude should be less than 1 VPP
on D for best results. Also, tie the Q¯ pin to VCC to reduce fundamental subharmonic and other noise source coupling
into the circuit board.
The D input also drives another higher gain stage. This stage generates fast edges with resultant high harmonic
spectral content. In one mode, the signal on FLTRDR (pin 14) is a square wave with greater spectral energy at odd
harmonics (3x, 5x, 7x). Figure 4 illustrates the typical spectral output at FLTRDR. Another mode is selected by
connecting F¯L¯¯T¯R¯D¯¯R and FLTRDR. This mode generates a pulse wave which contains greater spectral energy at
even harmonics (2x, 4x, 6x, 8x). Figure 5 illustrates the typical spectral output at FLTRDR when the two pins are
shorted together.
An external bandpass filter inserted between FLTRDR (or FLTRDR/F¯L¯T¯¯R¯D¯¯R) and AMPIN (pin 7) selects the
desired harmonic and attenuates the rest. This filter is typically either an LC or SAW implementation. The bandpass
filter is AC coupled since both the FLTDR and AMPIN signals are internally biased. The filter must be designed for
the drive impedance found at FLTRDR and the input impedance at AMPIN.
Graphs that follow in this data sheet show the S-parameters for these pins. Also included are graphs of the output
impedance magnitude of FLTRDR and the input impedance magnitude of AMPIN. These impedance graphs provide
a way to approximate the filter required without the use of S-parameter based design software.
The filter and other elements on the circuit board must be placed carefully to minimize subharmonic feed-through.
The resultant signal level at AMPIN should be 150 mV peak-peak or greater for best limiting amplifier performance.
The limiting amplifier provides a high bandwidth PECL/ECL output into the standard load of 50Ω to VCC – 2V.
Figure 1 shows the large signal output swing versus frequency.
It may be desirable to hold off the limiting amplifier operation until the sine-wave oscillator has started. A capacitor
may be used with the EN pin to create a delay. Connect the capacitor from EN to VCC (if EN-SEL is open) or VEE (if
EN-SEL is connected to VEE). This modification will avoid high-frequency parasitic feedback from the circuit board
during oscillator startup. A 220ρF capacitor will provide approximately 10μs delay.
Arizona Microtek’s website (www.azmicrotek.com) contains S-parameters for all signal paths in industry-standard
.s1p and .s2p format supporting an easier RF design process.
June 2009 Rev - 4
www.azmicrotek.com
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