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AZP53

型号:

AZP53

描述:

低相位噪声的正弦波LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave to LVPECL Buffer/Divider ]

品牌:

AZM[ ARIZONA MICROTEK, INC ]

页数:

9 页

PDF大小:

224 K

ARIZONA MICROTEK, INC.  
AZP51  
AZP52  
AZP53  
AZP54  
Low Phase Noise Sine Wave to LVPECL Buffer/Divider  
PACKAGE AVAILABILITY  
FEATURES  
BASE PART  
AZP51 (÷1)  
PACKAGE  
SC-70 Green /  
PART NO.  
MARKING  
NOTES  
3.0 to 3.6 V  
operating supply  
range  
D1G  
<Date Code>  
RoHS Compliant /  
Lead (Pb) Free  
SC-70 Green /  
RoHS Compliant /  
Lead (Pb) Free  
QFN 8 (1.5x1.5  
mm) Green / RoHS  
Compliant / Lead  
(Pb) Free  
AZP51SG  
1,2  
D2G  
<Date Code>  
LVPECL Outputs  
Optimized for  
Low Phase Noise  
Frequency Input  
to >650 MHz  
QFN 8 (1.5x1.5  
mm), SC-70 or  
SOT-23 packages  
AZP52SG  
AZP53PG  
AZP54VG  
1,2  
1,3  
1,2  
AZP52 (÷2)  
AZP53 (÷1,2)  
AZP54 (÷1)  
D3  
<Date Code>  
SOT-23 Green /  
RoHS Compliant /  
Lead (Pb) Free  
D4G  
<Date Code>  
All Packages  
Green / RoHS  
Compliant / Lead  
(Pb) Free  
1
2
3
Add R1 at end of part number for 7 inch , R2 for 13 inch Tape & Reel.  
Date code format: “Y” for year followed by “WW” for week.  
See Arizona Microtek web site for date code format.  
DESCRIPTION  
The AZP51 series is a family of sine wave to LVPECL buffers optimized for low phase noise. It is particularly  
useful in converting sine wave crystal or SAW based oscillator outputs into LVPECL outputs. The IC also includes  
an optional ÷2 function to provide better frequency range coverage when using a SAW based oscillator.  
The D input is internally biased to VDD/2. A sine wave input of at least 750 mv p-p ensures the AZP51 series  
meets its AC specifications. This input (D) should be capacitively coupled from the oscillator stage to ensure best  
output duty cycle.  
AZP51S (÷1), AZP52S (÷2), SC-70 Package  
The Enable input (EN) is active high with an internal pullup. When EN is high or not connected, the outputs  
(Q,Q¯) are active. When EN is low, Q and Q¯ are disabled in a high impedance (tri-state) condition. Refer to the  
Functional Operation table for more information.  
AZP53P (÷1, ÷2), QFN 8 1.5x1.5mm Package  
The EN_SEL input selects the operational polarity for the EN input, so the EN input can be set to active high or  
active low operation. Refer to the Functional Operation table for more information.  
1630 S. STAPLEY DR., SUITE 127 MESA, ARIZONA 85204 USA (480) 962-5881 FAX (623) 505-2414  
www.azmicrotek.com  
AZP51  
AZP52  
AZP53  
AZP54  
AZP54V (÷1) SOT-23 Package  
The Enable input (EN) is active low with an internal pulldown. When EN is low or not connected, the outputs  
(Q,Q¯) are active. When EN is high, Q and Q¯ are disabled in a high impedance (tri-state) condition. Refer to the  
Functional Operation table for more information.  
BLOCK DIAGRAMS  
AZP51  
AZP52  
AZP53  
AZP54  
December 2009 * REV - 2  
www.azmicrotek.com  
2
AZP51  
AZP52  
AZP53  
AZP54  
SIGNAL DESCRIPTION  
PIN/PAD  
D
Q,Q¯  
EN  
FUNCTION  
Sine or LVCMOS Input  
LVPECL Outputs  
Output Enable  
DIV_SEL Divide Select (AZP53 only)  
EN_SEL  
VDD  
Enable Select (AZP53 only)  
Positive Supply  
GND  
Negative Supply (Ground)  
DIV-SEL OPERATION  
PART  
NUMBER  
AZP51  
AZP54  
AZP52  
DIV-SEL  
DIVIDE  
RATIO  
2
-
÷1  
2
-
÷2  
÷1  
÷2  
NC1,L  
H
AZP53  
1. NC – no connection  
2. Internally connected  
FUNCTIONAL OPERATION  
INPUTS  
EN  
OUTPUTS  
PART  
NUMBER  
EN LOGIC  
Active High4  
Active Low3  
Active High4  
Active Low3  
PULLUP/  
PULLDOWN  
EN_SEL7  
EN  
D
Q
Q¯  
L
H
L8  
H8  
Z6  
L8  
H8  
Z6  
L8  
H8  
Z6  
L
H8  
L8  
Z6  
H8  
L8  
Z6  
H8  
L8  
Z6  
H
NC1, H  
AZP51  
AZP52  
2
-
Pullup  
Pulldown  
Pullup  
L
X5  
L
NC1, L  
H
NC1, H  
NC1, H  
L
H
X5  
L
AZP53  
AZP54  
H
L
X5  
L
NC1, L  
H
2
-
Pulldown  
H
H
L
X5  
Z6  
Z6  
1. NC – no connection  
2. Internally tied  
3. Active Low: Output enabled when EN low, Tri-state when EN high  
4. Active High: Output enabled when EN high, Tri-state when EN low  
5. X – Don’t care  
6. Z – High impedance  
7. EN_SEL input has an internal pullup resistor  
8. ÷1 modes only  
December 2009 * REV - 2  
www.azmicrotek.com  
3
AZP51  
AZP52  
AZP53  
AZP54  
AZP53P  
QFN 8, 1.5x1.5 mm  
TOP VIEW  
AZP51S, 52S  
SC-70  
TOP VIEW  
AZP54V  
SOT-23  
TOP VIEW  
December 2009 * REV - 2  
www.azmicrotek.com  
4
AZP51  
AZP52  
AZP53  
AZP54  
Absolute Maximum Ratings are those values beyond which device life may be impaired.  
Symbol  
Characteristic  
Rating  
Unit  
VDD  
VI  
TA  
Power Supply  
Input Voltage  
Operating Temperature Range  
Storage Temperature Range  
0 to +5.5  
-0.5 to VDD+0.5  
-40 to +85  
Vdc  
Vdc  
°C  
TSTG  
-65 to +150  
°C  
DC Characteristics (VDD = 3.0V to 3.6V unless otherwise specified, TA = -40 to 85 C)  
Symbol  
Characteristic  
Conditions  
Min  
Typ  
Max  
Unit  
-40 C  
25 C  
85 C  
-40 C  
25 C  
85 C  
2.05  
2.05  
2.05  
1.365  
1.430  
1.490  
2.415  
2.480  
2.540  
1.615  
1.680  
1.740  
VOH  
VOL  
Output HIGH Voltage1  
VDD = 3.3V  
V
Output LOW Voltage1  
VDD = 3.3V  
V
Output Leakage Current, Tri-  
state2  
High Level Input Voltage  
IZ  
EN=Disable3  
-10  
2.0  
10  
μA  
V
VIH  
VIL  
EN_SEL4  
DIV_SEL4  
EN  
EN_SEL  
DIV_SEL  
EN  
Low Level Input Voltage  
0.8  
V
RPU  
RPD  
RP  
Pullup Resistor4  
50k  
50k  
50k  
Pulldown Resistor4  
Pullup/Pulldown Resistor5  
D Input to Internal  
VDD/2 Reference  
RBIAS  
IDD  
Bias Resistor  
10k  
Power Supply Current  
22  
35  
mA  
1.  
2.  
3.  
4.  
5.  
Specified with outputs terminated through 50Ω resistors to VDD - 2V or Thevenin equivalent.  
Measured at Q/Q¯ pins.  
See functional tables for Disable state definition.  
AZP53 only.  
See functional operation table for pullup/pulldown mode selection.  
AC Characteristics (VDD = 3.0V to 3.6V, TA = -40 to 85 C)  
Symbol  
tr / tf  
fMAX  
tpd  
Characteristic  
Unit  
Min  
Max  
Output Rise/Fall1  
(20% - 80%)  
0.25  
0.7  
ns  
Maximum Input  
Frequency – Sine wave2  
Propagation Delay1,3,6  
D to Q/Q¯  
650  
3.0  
MHz  
ns  
1.0  
Enable1,4  
ten  
200  
80  
ns  
EN to Q/Q¯  
Disable1,5  
tdis  
ns  
EN to Q/Q¯  
Phase Noise1,3  
10 MHz offset  
dBc/  
Hz  
nP  
-158  
1.  
2.  
3.  
4.  
5.  
6.  
Specified with outputs terminated through 50Ω resistors to VCC - 2V or Thevenin equivalent.  
750 mv p-p sine wave, AC coupled to D input.  
155 MHz 750 mv p-p sine wave input.  
EN asserted (enabled) to Q/Q¯ outputs producing specified VOH & VOL levels.  
EN deasserted (disabled) to Q/Q¯ outputs VOL min.  
Measured from 50% D to 50% Q/Q¯.  
December 2009 * REV - 2  
www.azmicrotek.com  
5
AZP51  
AZP52  
AZP53  
AZP54  
PACKAGE DIAGRAM  
P – QFN 8 1.5x1.5mm  
Note: All dimensions are in mm  
December 2009 * REV - 2  
www.azmicrotek.com  
6
AZP51  
AZP52  
AZP53  
AZP54  
PACKAGE DIAGRAM  
S – SC-70 6L  
2.467  
D
e
e
L
C
HE  
E
L
C
C
L
b
SYMBOL MIN  
MAX  
1.35  
E
1.15  
D
1.85  
2.00  
2.25  
2.30  
A2  
A
A1  
HE  
A
0.80  
0.80  
0.00  
1.00  
0.91  
0.09  
A2  
A1  
e
0.65 BSC  
b
c
0.15  
0.08  
0.30  
0.25  
NOTE:  
1. ALL DIMENSIONS ARE IN MILLIMETERS.  
2. DIMENSIONS ARE EXCLUSIVE OF  
MOLD FLASH & GATE BURR.  
L
0.21  
0.41  
December 2009 * REV - 2  
www.azmicrotek.com  
7
AZP51  
AZP52  
AZP53  
AZP54  
PACKAGE DIAGRAM  
V – SOT-23 6L  
5
2.90±0.100  
C
L
0.950  
TYP.  
0.950  
TYP.  
NOTE:  
1. Dimensions and tolerances are as per ANSI  
Y14.5M, 1982.  
2. Package surface to be matte finish VDI 11~13.  
3. Die is facing up for mold. Die is facing  
down for trim/form, ie. reverse trim/form.  
C
L
4. The footlength measuring is based on the  
gauge plane method.  
5. Dimension are exclusive of mold flash and gate burr.  
6. Dimension are exclusive of solder plating.  
0.350(MIN)  
0.500(MAX)  
(6 PLCS)  
10° TYP.  
(2 plcs)  
SEATING PLANE  
0.05(MIN)  
0.15(MAX)  
10° TYP.  
(2 plcs)  
10° TYP.  
(2 plcs)  
0°~3°  
±0.10  
0.20 BSC  
Gauge Plane  
0.45  
0.127  
5
10° TYP.  
(2 plcs)  
December 2009 * REV - 2  
www.azmicrotek.com  
8
AZP51  
AZP52  
AZP53  
AZP54  
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc.  
makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona  
Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all  
liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license  
rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems  
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a  
situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such  
unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries,  
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly  
or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that  
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.  
December 2009 * REV - 2  
www.azmicrotek.com  
9
厂商 型号 描述 页数 下载

AZM

AZP51 低相位噪声的正弦波LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave to LVPECL Buffer/Divider ] 9 页

AZM

AZP51SG 低相位噪声的正弦波LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave to LVPECL Buffer/Divider ] 9 页

AZM

AZP51_12 低相位噪声正弦波/ CMOS到LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider ] 9 页

AZM

AZP52 低相位噪声的正弦波LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave to LVPECL Buffer/Divider ] 9 页

AZM

AZP52SG 低相位噪声的正弦波LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave to LVPECL Buffer/Divider ] 9 页

AZM

AZP52_13 低相位噪声正弦波/ CMOS到LVPECL缓冲器/转换器[ Low Phase Noise Sine Wave / CMOS to LVPECL Buffer / Translator ] 9 页

AZM

AZP53PG 低相位噪声的正弦波LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave to LVPECL Buffer/Divider ] 9 页

AZM

AZP53QG 低相位噪声正弦波/ CMOS[ Low Phase Noise Sine Wave/CMOS ] 13 页

AZM

AZP53_13 低相位噪声正弦波/ CMOS到LVPECL缓冲器/转换器[ Low Phase Noise Sine Wave / CMOS to LVPECL Buffer / Translator ] 13 页

AZM

AZP54 低相位噪声的正弦波LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave to LVPECL Buffer/Divider ] 9 页

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