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AZP63QG

型号：

AZP63QG

描述：

低相位噪声正弦波/ CMOS到LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider ]

品牌：

AZM[ ARIZONA MICROTEK, INC ]

页数：

12 页

PDF大小：

529 K

下载PDF手册
AZP63  
www.azmicrotek.com  
Low Phase Noise Sine Wave/CMOS  
to LVPECL Buffer/Divider  
DESCRIPTION  
FEATURES  
The AZP63 is a sine wave/CMOS to LVPECL buffer/divider optimized for  
very low phase noise (-165dBc/Hz). It is particularly useful in converting  
crystal or SAW based oscillators into LVPECL outputs for greater than  
•
LVPECL outputs optimized  
for very low phase noise  
(-165dBc/Hz)  
1GHz of bandwidth.  
bandwidth, refer to the AZP5x family.  
For lower power consumption and reduced  
•
•
•
•
High bandwidth, > 1GHz  
Selectable ÷1, ÷2 output  
Selectable Enable logic  
3.0V to 3.6V operation  
The AZP63 is one of a family of parts that provide options of fixed ÷1,  
fixed ÷2 and selectable ÷1, ÷2 modes as well as active high enable or active  
low enable to oscillator designers. Refer to Table 2 for the comparison of  
parts within the AZP5x and AZP63 family.  
BLOCK DIAGRAM  
APPLICATIONS  
•
Converting crystal or SAW  
based oscillators to LVPECL  
output  
PACKAGE AVAILABILITY  
•
•
•
Available in die  
SON8  
Green/RoHS Compliant/Pb-Free  
Order Number  
AZP63QG1  
Package  
Marking  
E <Date Code>2  
SON8  
1
2
Tape & Reel - Add 'R1' at end of order number for 7in (1k parts), 'R2' (2.5k) for 13in  
See www.azmicrotek.com for date code format  
www.azmicrotek.com  
+1-480-962-5881  
1630 S Stapley Dr, Suite 127  
Mesa, AZ 85204 USA  
Request a Sample  
May 2012, Rev 2.1  
Arizona Microtek, Inc.  
AZP63  
Low Phase Noise Sine Wave CMOS  
to LVPECL Buffer/Divider  
PIN DESCRIPTION AND CONFIGURATION  
Table 1 - Pin Description  
Pin  
Name  
Type  
Function  
1
Q
Output  
Output  
LVPECL Output  
LVPECL Output  
2
Q
3
4
5
6
7
8
EN  
GND  
Input  
Power  
Input  
Input  
Input  
Power  
Enable  
Negative Supply  
Sine or CMOS Input  
Enable Select  
D  
EN_SEL  
DIV_SEL  
VDD  
Divide Select  
Positive Supply  
Q
Q
1
2
3
4
8
7
6
5
VDD  
DIV_SEL  
EN_SEL  
D
EN  
GND  
Figure 1 - Pin Configuration  
www.azmicrotek.com  
+1-480-962-5881  
2
Request a Sample  
May 2012, Rev 2.1  
Arizona Microtek, Inc.  
AZP63  
Low Phase Noise Sine Wave CMOS  
to LVPECL Buffer/Divider  
ENGINEERING NOTES  
FUNCTIONALITY  
The AZP63 is one of a family of parts that provide options of fixed ÷1, fixed ÷2 and selectable ÷1, ÷2 modes as well as  
active high enable or active low enable to oscillator designers. Table 2 details the differences between the parts to assist  
designers in selecting the optimal part for their design.  
Table 3 lists the specific AZP63 functional operation.  
Figure 2 plots the S-parameters of theD input. S-parameter and IBIS model files for the AZP63 are also available for  
download.  
Table 2 - AZP51-54 & AZP63 Family  
EN pull-  
up/pull-down  
Part Number  
Divide Ratio  
EN Logic  
Bandwidth  
AZP51  
AZP52  
AZP53  
AZP54  
AZP63  
÷1  
÷2  
active HIGH  
active HIGH  
selectable  
active LOW  
selectable  
Pull-up  
Pull-up  
selectable  
Pull-down  
selectable  
> 800MHz  
> 800MHz  
> 800MHz  
> 800MHz  
≥ 1GHz  
Selectable ÷1 or ÷2  
÷1  
Selectable ÷1 or ÷2  
Table 3 – AZP63 Functional Operation, ÷1 mode  
Inputs  
Outputs  
Q  
Part Number  
EN_SEL  
EN  
Low, NC1  
High  
Q
D  
Low Low  
High High  
High  
Low  
Z3  
High, NC1  
X2  
Z3  
Low Low  
High  
High, NC1  
High High  
Low  
Z3  
Low  
AZP63  
Low  
X2  
Z3  
DIV_SEL  
Divide Ratio  
Low, NC1  
÷1  
÷2  
High  
1
2
3
Not connected  
Don't care  
Tri-State  
www.azmicrotek.com  
+1-480-962-5881  
3
Request a Sample  
May 2012, Rev 2.1  
 
 
Arizona Microtek, Inc.  
AZP63  
Low Phase Noise Sine Wave CMOS  
to LVPECL Buffer/Divider  
Figure 2- S11, Parameters,D Input  
INPUT TERMINATION  
TheD input bias is VDD/2 fed through an internal 10kΩ resistor. For clock applications, an input signal of at least  
750mVpp ensures the AZP63 meets AC specifications. The input should also be AC coupled to maintain a 50% duty cycle  
on the outputs. The input can be driven to any voltage between 0V and VDD without damage or waveform degradation.  
Input signal  
D
10kΩ  
A/R  
VDD/2  
Figure 3 - Input Termination  
www.azmicrotek.com  
+1-480-962-5881  
4
Request a Sample  
May 2012, Rev 2.1  
 
Arizona Microtek, Inc.  
AZP63  
Low Phase Noise Sine Wave CMOS  
to LVPECL Buffer/Divider  
OUTPUT TERMINATION TECHNIQUES  
The LVPECL compatible output stage of the AZP63 uses a current drive topology to maximize switching speed as  
illustrated below in Figure 4. Two current source PMOS transistors (M1-M2) feed the output pins. M5 is an NMOS  
current source which is switched by M3 and M4. When M4 is on, M5 takes current from M2. This produces an output  
current of 5.1mA (low output state). M3 is off, and the entire 21.1mA flows through the output pin. The associated output  
voltage swings match LVPECL levels when external 50Ω resistors terminate the outputs.  
Both Q and Q¯ should always be terminated identically to avoid waveform distortion and circulating current caused by  
unsymmetrical loads. This rule should be followed even if only one output is in use.  
VDD (+3.3 V)  
Output  
Stage  
M1  
M2  
External  
Circuitry  
Vbp  
21.1mA  
21.1mA  
Q
Q
21.1mA - High  
5.1mA - Low  
50Ω  
50Ω  
M3  
M4  
D
M5  
VTT = VDD - 2.0V  
Vbn  
16mA  
Figure 4 - Typical Output Termination  
DUAL SUPPLY LVPECL OUTPUT TERMINATION  
The standard LVPECL loads are a pair of 50Ω resistors connected between the outputs and VDD-2.0V (Figure 4). The  
resistors provide both the DC and the AC loads, assuming 50Ω interconnect. If an additional supply is available within the  
application, a four resistor termination configuration is possible (Figure 5).  
www.azmicrotek.com  
+1-480-962-5881  
5
Request a Sample  
May 2012, Rev 2.1  
 
Arizona Microtek, Inc.  
AZP63  
Low Phase Noise Sine Wave CMOS  
to LVPECL Buffer/Divider  
VDD (+3.3 V)  
M2  
Output  
Stage  
VDD (+3.3 V)  
External  
Circuitry  
M1  
Vbp  
130Ω  
130Ω  
21.1mA  
21.1mA  
Q
Q
21.1mA - High  
5.1mA - Low  
82Ω  
82Ω  
M3  
M4  
D
M5  
Vbn  
16mA  
Figure 5 - Dual Supply Output Termination  
THREE RESISTOR TERMINATION  
Another termination variant eliminates the need for the additional supply (Figure 6). Alternately three resistors and  
one capacitor accomplish the same termination and reduce power consumption.  
VDD (+3.3 V)  
Output  
Stage  
M1  
M2  
External  
Circuitry  
Vbp  
21.1mA  
21.1mA  
Q
Q
21.1mA - High  
5.1mA - Low  
50Ω  
50Ω  
M3  
M4  
D
0.01µF  
50Ω  
M5  
Vbn  
16mA  
Figure 6 - Three Resistor Termination  
www.azmicrotek.com  
+1-480-962-5881  
6
Request a Sample  
May 2012, Rev 2.1  
 
 
Arizona Microtek, Inc.  
AZP63  
Low Phase Noise Sine Wave CMOS  
to LVPECL Buffer/Divider  
EVALUATION BOARD (EBP53)  
Arizona Microtek’s evaluation board EBP53 provides the most convenient way to test and prototype AZP63 series  
circuits. Built for the AZP53Q 1.5x1.0 mm package, it is designed to support both dual and single supply operation. Dual  
supply operation (VDD=+2.0V, VSS=-1.3V) enables direct coupling to 50Ω time domain test equipment (Figure 7).  
VDD (+2.0 V)  
Output  
Stage  
Test  
Equipment  
M1  
M2  
Vbp  
Terminations  
21.1mA  
21.1mA  
Q
Q
21.1mA - High  
5.1mA - Low  
50Ω  
50Ω  
M3  
M4  
D
M5  
Vbn  
16mA  
VSS (-1.3 V)  
Figure 7 - Split Supply LVPECL Output Termination  
AC TERMINATION  
Clock applications or phase noise/frequency domain testing scenarios typically require AC coupling. Figure 8 below  
shows the AC coupling technique. The 200Ω resistors form the required DC loads, and the 50Ω resistors provide the AC  
termination. The parallel combination of the 200Ω and 50Ω resistors results in a net 40Ω AC load termination. In many  
cases this will work well. If necessary, the 50Ω resistors can be increased to about 56Ω. Alternately, bias tees combined  
with current setting resistors will eliminate the lowered AC load impedance. The 50Ω resistors are typically connected to  
ground but can be connected to the bias level needed by the succeeding stage.  
www.azmicrotek.com  
+1-480-962-5881  
7
Request a Sample  
May 2012, Rev 2.1  
 
Arizona Microtek, Inc.  
AZP63  
Low Phase Noise Sine Wave CMOS  
to LVPECL Buffer/Divider  
VDD (+3.3 V)  
M2  
Output  
Stage  
M1  
External  
Circuitry  
Vbp  
21.1mA  
21.1mA  
0.01µF  
Q
Q
0.01µF  
21.1mA - High  
5.1mA - Low  
200Ω  
200Ω  
50Ω  
50Ω  
M3  
M4  
D
M5  
Vbn  
16mA  
GND or VT  
Figure 8 - AC Termination  
PERFORMANCE DATA  
Table 4 - Absolute Maximum Ratings  
Absolute Maximum Ratings are those values beyond which device life may be impaired.  
Symbol  
VDD  
Characteristic  
Power Supply  
Rating  
0 to +5.5  
-0.5 to VDD + 0.5  
-40 to +85  
-65 to +150  
2000  
Unit  
V
VI  
Input Voltage  
V
TA  
Operating Temperature Range  
Storage Temperature Range  
Human Body Model  
Machine Model  
°C  
°C  
V
TSTG  
ESDHBM  
ESDMM  
ESDCDM  
100  
V
Charged Device Model  
2000  
V
www.azmicrotek.com  
+1-480-962-5881  
8
Request a Sample  
May 2012, Rev 2.1  
 
Arizona Microtek, Inc.  
AZP63  
Low Phase Noise Sine Wave CMOS  
to LVPECL Buffer/Divider  
Table 5 - DC Characteristics  
DC Characteristics (VDD = 3.0V to 3.6V unless otherwise specified, TA = -40 to 85 °C)  
Unit  
V
Symbol  
Characteristic  
Conditions  
Min Typ Max  
-40 C  
25 C  
85 C  
-40 C  
25 C  
85 C  
2.2  
2.2  
2.2  
1.4  
1.4  
1.4  
2.45  
2.45  
2.45  
1.68  
1.68  
1.68  
VOH  
Output HIGH Voltage1  
VDD = 3.3V  
VOL  
Output LOW Voltage1  
VDD = 3.3V  
V
IZ  
Output Leakage Current, Tri-state2  
High Level Input Voltage  
EN=Disable  
-10  
2
10  
μA  
V
EN_SEL  
VIH  
VIL  
DIV_SEL  
Low Level Input Voltage  
EN  
0.8  
V
IPU  
IPD  
Pullup Current  
EN_SEL  
2.2  
μA  
μA  
Pulldown Current  
DIV_SEL  
-2.2  
IP  
Pullup/Pulldown Current  
EN  
±2.2  
μA  
RBIAS  
IDD  
Bias Resistor  
10k  
64  
Ω
D Input to Internal VDD/2 Reference  
Power Supply Current  
70  
88  
mA  
mA  
IDDSW  
Power Supply Current Fast Switching1,3,4  
Input Freq >1GHz  
IDDZ  
Power Supply Current Outputs Tri-State1  
8
mA  
D Input ≤ VIL EN=Disables  
1 Specified with outputs terminated through 50Ω resistors to VDD - 2V or Thevenin equivalent.  
2 Measured at Q pins.  
3 Includes load current through external 50Ω resistors to VDD - 2V  
4 Current measured in ÷1 mode, D and Q /Q pins switching at 1000MHz  
www.azmicrotek.com  
+1-480-962-5881  
9
Request a Sample  
May 2012, Rev 2.1  
Arizona Microtek, Inc.  
AZP63  
Low Phase Noise Sine Wave CMOS  
to LVPECL Buffer/Divider  
Table 6 - AC Characteristics  
AC Characteristics (VDD = 3.0V to 3.6V, TA = -40 to 85 °C)  
Symbol  
Characteristic  
Output Rise/Fall1,2  
Min  
Max  
Unit  
tr / tf  
80  
250  
ps  
(20% - 80%)  
Maximum Input Frequency - Sine wave2  
fMAX  
÷1  
1000  
1500  
VDD  
MHz  
÷2  
VINMAX  
VINMIN  
Maximum Recommended Input Signal  
Minimum Recommended Input Signal  
Phase Noise1,2 - 1MHz offset  
V p-p  
V p-p  
0.2  
nP  
-165 dBc/Hz  
1 Specified with outputs terminated through 50W resistors to VCC - 2V or Thevenin equivalent.  
2 1.5 v p-p sine wave input, AC coupled toD pin.  
www.azmicrotek.com  
+1-480-962-5881  
10  
Request a Sample  
May 2012, Rev 2.1  
Arizona Microtek, Inc.  
AZP63  
Low Phase Noise Sine Wave CMOS  
to LVPECL Buffer/Divider  
PACKAGE DIAGRAM  
SON8 (1.5x1.0x0.4mm)  
Green/RoHS compliant/Pb-Free  
MSL =1  
www.azmicrotek.com  
+1-480-962-5881  
11  
Request a Sample  
May 2012, Rev 2.1  
Arizona Microtek, Inc.  
AZP63  
Low Phase Noise Sine Wave CMOS  
to LVPECL Buffer/Divider  
DIE SPECIFICATIONS  
Die Size 754µ x 354µ  
Pad Size 52.1µ Octagonal  
Die Coordinates (Center 0,0)  
X Coordinate  
(µm)  
Y Coordinate  
(µm)  
Pad Name  
D
EN_SEL  
DIV_SEL  
VDD  
Q
-273.875  
-140.350  
-43.625  
302.875  
170.925  
72.550  
-106.575  
-106.650  
-106.650  
-20.450  
105.725  
105.725  
106.000  
72.325  
QN  
EN  
-175.300  
-296.350  
GND  
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice.  
Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for  
any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of  
any product or circuit and specifically disclaims any and all liability, including without limitation special,  
consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of  
others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems  
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc.  
product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona  
Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold  
Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all  
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of  
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that  
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.  
www.azmicrotek.com  
+1-480-962-5881  
12  
Request a Sample  
May 2012, Rev 2.1  
厂商 型号 描述 页数 下载

AZM

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 		AZP51SG 低相位噪声的正弦波LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave to LVPECL Buffer/Divider ] 9 页

AZM

 		AZP51_12 低相位噪声正弦波/ CMOS到LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider ] 9 页

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 		AZP52 低相位噪声的正弦波LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave to LVPECL Buffer/Divider ] 9 页

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 		AZP52SG 低相位噪声的正弦波LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave to LVPECL Buffer/Divider ] 9 页

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 		AZP52_13 低相位噪声正弦波/ CMOS到LVPECL缓冲器/转换器[ Low Phase Noise Sine Wave / CMOS to LVPECL Buffer / Translator ] 9 页

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 		AZP53 低相位噪声的正弦波LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave to LVPECL Buffer/Divider ] 9 页

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