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AZP92_12

型号：

AZP92_12

描述：

PECL / ECL ÷ 1 ， ÷ 2时钟发生器芯片，可选择启用[ PECL/ECL ÷1, ÷2 Clock Generation Chip with Selectable Enable ]

品牌：

AZM[ ARIZONA MICROTEK, INC ]

页数：

8 页

PDF大小：

480 K

下载PDF手册
AZP92  
www.azmicrotek.com  
PECL/ECL ÷1, ÷2 Clock Generation  
Chip with Selectable Enable  
FEATURES  
DESCRIPTION  
• 3.0V to 5.5V Operation  
• Selectable Divide Ratio  
• Selectable Enable Polarity and  
Threshold (CMOS or PECL)  
• High Bandwidth  
The AZP92 is a ÷1 or ÷2 clock generation part specifically designed to  
accommodate Colpitts or Pierce based oscillators. Features are incorporated  
to reduce board components. A voltage reference and input biasing allows  
for easy oscillator interface.  
The AZP92 provides a ÷ 2 mode of operation for more frequency options  
and is selectable with a single connection. A selectable enable is also  
provided which doubles as a reset when the AZP92 is in ÷2 mode. With a  
single connection, the enable can be selected to operate as active high or  
active low.  
o
o
1.5+ GHz (÷1)  
3.0+ GHz (÷2)  
• -145 dBc/Hz (÷1) Typical  
Noise Floor  
•
-151 dBc/Hz (÷2) Typical  
Noise Floor  
BLOCK DIAGRAM  
APPLICATIONS  
• Colpitts or Pierce based  
oscillators  
PACKAGE AVAILABILITY  
•
MLP8  
o
Green/RoHS Compliant/Pb-Free  
Part Number (PN)  
Package  
Marking  
P1G <Date Code>2  
AZP92NAG1  
MLP8  
1
2
Tape & Reel - Add 'R1' at end of PN for 7in (1k parts), 'R2' (2.5k) for 13in  
See www.azmicrotek.com for date code format  
www.azmicrotek.com  
+1-480-962-5881  
1630 S Stapley Dr, Suite 127  
Mesa, AZ 85204 USA  
Request a Sample  
May 2012, Rev 1.0  
Arizona Microtek, Inc.  
AZP92  
PECL/ECL ÷1, ÷2 Clock Generation  
Chip with Selectable Enable  
PIN DESCRIPTION AND CONFIGURATION  
Table 1 - Pin Description  
Pin  
1
Name  
Type  
Function  
Enable Polarity Select  
EN-SEL  
Input  
Input  
Input  
Input  
2
Data Input  
Reference Voltage  
Output Enable  
D
VBB  
EN  
3
4
5
DIV-SEL Input  
Divide Select  
6
Q¯  
Q
Output  
Output  
Power  
Power  
Inverted PECL Output  
PECL Output  
7
8
VCC  
VEE  
Positive Supply  
Negative Supply  
9
VCC  
8
1
EN-SEL  
D
Q
7
6
5
2
3
VEE  
VBB  
Q
EN  
4
DIV-SEL  
Figure 1 - Pin Configuration  
www.azmicrotek.com  
+1-480-962-5881  
2
Request a Sample  
May 2012, Rev 1.0  
Arizona Microtek, Inc.  
AZP92  
PECL/ECL ÷1, ÷2 Clock Generation  
Chip with Selectable Enable  
ENGINEERING NOTES  
The AZP92’s divide ratio is selected with the DIV-SEL pin. When DIV-SEL is open (NC), the AZP92 functions as a  
standard receiver. When the DIV-SEL is connected to VEE, it functions as a ÷2 divider. In ÷2 mode, the latches reset to a  
logic 0 level when disabled.  
The Enable (EN) functionality is selected with the EN-SEL pin which has three valid states: open (NC), VEE, or connected  
to VEE via a 20kΩ resistor. Leaving EN-SEL open or connecting it to VEE will select the EN pin to function as an active  
high CMOS/TTL enable. When EN-SEL is open, an internal 75kΩ pull-up resistor is selected which enables the outputs  
whenever EN is left open. When EN-SEL is connected to VEE, an internal 75kΩ pull-down resistor is selected which  
disables the outputs whenever EN is left open. Connecting the EN-SEL to VEE with a 20kΩ resistor will select the EN pin  
to function as an active low PECL/ECL enable with an internal 75kΩ pull-down resistor. In this mode, outputs are  
enabled when EN is left open. This default logic condition can be overridden by connecting the EN to VCC with an  
external resistor of ≤20kΩ.  
Table 2 - Divide Truth Table  
÷Ratio  
÷1  
DIV-SEL  
NC  
1
VEE  
÷2  
1 DIV-SEL connection must be ≤1Ω.  
Table 3 - Enable Truth Table  
EN  
EN-SEL  
Q
Q¯  
CMOS Low or VEE  
CMOS High, VCC or NC  
CMOS Low, VEE or NC  
CMOS High or VCC  
PECL Low, VEE or NC  
PECL High or VCC  
Low  
Data  
Low  
Data  
Low  
Data  
High  
Data  
High  
Data  
High  
Data  
NC  
VEE  
20kΩ to VEE  
Figure 2 illustrates the timing sequences for the AZP92 in the ÷1 mode which is determined by leaving the DIV-SEL open  
(NC). It also illustrates the enable in the active High mode being controlled by a CMOS signal. This mode is determined  
by leaving the EN-SEL open (NC).  
D
EN  
Q
(CMOS)  
Figure 2 - Timing Diagram  
www.azmicrotek.com  
+1-480-962-5881  
3
Request a Sample  
May 2012, Rev 1.0  
Arizona Microtek, Inc.  
AZP92  
PECL/ECL ÷1, ÷2 Clock Generation  
Chip with Selectable Enable  
Figure 3 illustrates the timing sequences for the AZP92 in the ÷2 mode which is determined by connecting the DIV-SEL  
to VEE. It also illustrates the enable in the active Low mode being controlled by a PECL signal. This mode is determined  
by connecting the EN-SEL to VEE via 20kΩ resistor.  
D
(PECL)  
EN  
Q
Figure 3 - Timing Diagram  
1000  
900  
800  
700  
600  
500  
400  
300  
200  
0
1000  
2000  
3000  
4000  
5000  
6000  
Input Frequency (MHz)  
Figure 4 - Typical Large Signal Output Swing  
Measured with 750mv D input, Q/Q¯ each terminated to VCC-2V via 50 Ω resistors  
www.azmicrotek.com  
+1-480-962-5881  
4
Request a Sample  
May 2012, Rev 1.0  
Arizona Microtek, Inc.  
AZP92  
PECL/ECL ÷1, ÷2 Clock Generation  
Chip with Selectable Enable  
PERFORMANCE DATA  
Table 4 - Absolute Maximum Ratings  
Absolute Maximum Ratings are those values beyond which device life may be impaired.  
Symbol  
VCC  
Characteristic  
Power Supply  
Input Voltage  
Condition  
Rating  
0 to + 6.0  
0 to + 6.0  
±1.2  
Unit  
V
VEE = 0V  
VI  
VEE = 0V  
V
D/D¯ Input Voltage  
Referenced to VBB  
V
VD/D¯  
Continuous  
50  
IOUT  
Output Current  
mA  
Surge  
100  
TA  
Operating Temperature Range  
Storage Temperature Range  
-
-
-
-
-
-40 to +85  
-65 to +150  
2500  
°C  
°C  
V
TSTG  
ESDHBM  
ESDMM  
ESDCDM  
Human Body Model Electro Static Discharge  
Machine Model Electro Static Discharge  
Charged Device Model Electro Static Discharge  
200  
V
2000  
V
Table 5 - 100K ECL DC Characteristics  
100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND)  
-40°C  
Min  
0°C  
25°C  
85°C  
Min  
Symbol  
Characteristic  
Unit  
Max  
-880  
Min  
Max  
-880  
Min  
Max  
-880  
Max  
-880  
VOH  
VOL  
VBB  
Output HIGH Voltage1  
Output LOW Voltage1  
Reference Voltage  
-1085  
-1900  
-1390  
-1165  
-1025  
-1900  
-1390  
-1165  
-1025  
-1900  
-1390  
-1165  
-1025  
-1900  
-1390  
-1165  
mV  
mV  
mV  
mV  
-1555  
-1250  
-390  
-1620  
-1250  
-390  
-1620  
-1250  
-390  
-1620  
-1250  
-390  
Input HIGH Voltage D/EN2  
VIH  
VIL  
VEE+  
2000  
VEE+  
2000  
VEE+  
2000  
VEE+  
2000  
Input HIGH Voltage EN3  
Input LOW Voltage D/EN2  
Input LOW Voltage EN3  
VCC  
VCC  
VCC  
VCC  
mV  
mV  
mV  
-2250  
-1475  
-2250  
-1475  
-2250  
-1475  
-2250  
-1475  
VEE+  
800  
VEE+  
800  
VEE+  
800  
VEE+  
800  
VEE  
VEE  
VEE  
VEE  
IIH  
IIL  
Input HIGH Current EN  
Input LOW Current EN (ECL)  
Power Supply Current4  
150  
150  
150  
150  
µA  
µA  
mA  
0.5  
0.5  
0.5  
0.5  
IEE  
31  
31  
31  
34  
1.  
2.  
3.  
4.  
Specified with outputs terminated through 50Ω resistors to VCC - 2V.  
EN-SEL connected to VEE through a 20kΩ resistor.  
EN-SEL connected VEE or left open (NC).  
DIV-SEL left open (NC).  
www.azmicrotek.com  
+1-480-962-5881  
5
Request a Sample  
May 2012, Rev 1.0  
Arizona Microtek, Inc.  
AZP92  
PECL/ECL ÷1, ÷2 Clock Generation  
Chip with Selectable Enable  
Table 6 - 100K LVPECL DC Characteristics  
100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V)  
-40°C  
Min  
0°C  
25°C  
85°C  
Min  
Symbol  
Characteristic  
Unit  
Max  
-880  
-1555  
-1250  
-390  
VCC  
Min  
-1025  
-1900  
-1390  
-1165  
-1165  
-2250  
VEE  
Max  
-880  
-1620  
-1250  
-390  
VCC  
Min  
Max  
-880  
-1620  
-1250  
-390  
VCC  
Max  
-880  
-1620  
-1250  
-390  
VCC  
VOH  
VOL  
VBB  
Output HIGH Voltage1,2  
Output LOW Voltage1,2  
Reference Voltage1  
Input HIGH Voltage D1,3  
Input HIGH Voltage EN1,4  
Input LOW Voltage1,3  
Input LOW Voltage EN1,4  
Input HIGH Current EN  
Input LOW Current EN (ECL)  
Power Supply Current2  
-1085  
-1900  
-1390  
-1165  
-1165  
-2250  
VEE  
-1025  
-1900  
-1390  
-1165  
-1165  
-2250  
VEE  
-1025  
-1900  
-1390  
-1165  
-1165  
-2250  
VEE  
mV  
mV  
mV  
mV  
mV  
VIH  
VIL  
-1475  
-1475  
150  
-1475  
-1475  
150  
-1475  
-1475  
150  
-1475  
-1475  
150  
mV  
mV  
µA  
µA  
mA  
IIH  
IIL  
0.5  
0.5  
0.5  
0.5  
IEE  
31  
31  
31  
34  
1.  
2.  
3.  
4.  
5.  
For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value.  
Specified with outputs terminated through 50Ω resistors to VCC - 2V.  
EN-SEL connected to VEE through a 20kΩ resistor.  
EN-SEL connected VEE or left open (NC).  
DIV-SEL left open (NC).  
Table 7 - 100K PECL DC Characteristics  
100K PECL DC Characteristics (VEE = GND, VCC = +5.0V)  
-40°C  
0°C  
25°C  
85°C  
Symbol  
Characteristic  
Unit  
Min  
-1085  
-1900  
-1390  
-1165  
-1165  
-2250  
VEE  
Max  
-880  
-1555  
-1250  
-390  
VCC  
Min  
-1025  
-1900  
-1390  
-1165  
-1165  
-2250  
VEE  
Max  
-880  
-1620  
-1250  
-390  
VCC  
Min  
Max  
-880  
-1620  
-1250  
-390  
VCC  
Min  
-1025  
-1900  
-1390  
-1165  
-1165  
-2250  
VEE  
Max  
-880  
-1620  
-1250  
-390  
VCC  
VOH  
VOL  
VBB  
Output HIGH Voltage1,2  
Output LOW Voltage1,2  
Reference Voltage1  
Input HIGH Voltage D1,3  
Input HIGH Voltage EN1,4  
Input LOW Voltage1,3  
Input LOW Voltage EN1,4  
Input HIGH Current EN  
Input LOW Current EN (ECL)  
Power Supply Current2  
-1025  
-1900  
-1390  
-1165  
-1165  
-2250  
VEE  
mV  
mV  
mV  
mV  
mV  
VIH  
VIL  
-1475  
-1475  
150  
-1475  
-1475  
150  
-1475  
-1475  
150  
-1475  
-1475  
150  
mV  
mV  
µA  
µA  
mA  
IIH  
IIL  
0.5  
0.5  
0.5  
0.5  
IEE  
31  
31  
31  
34  
1.  
2.  
3.  
4.  
5.  
For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.  
Specified with outputs terminated through 50Ω resistors to VCC - 2V.  
EN-SEL connected to VEE through a 20kΩ resistor.  
EN-SEL connected VEE or left open (NC).  
DIV-SEL left open (NC).  
www.azmicrotek.com  
+1-480-962-5881  
6
Request a Sample  
May 2012, Rev 1.0  
Arizona Microtek, Inc.  
AZP92  
PECL/ECL ÷1, ÷2 Clock Generation  
Chip with Selectable Enable  
Table 8 - AC Characteristics  
AC Characteristics (VEE = -3.0V to -5.5V; VCC=GND or VEE=GND; VCC = +3.0V to +5.5V)  
-40°C  
0°C  
25°C  
85°C  
Symbol  
Characteristic  
Unit  
Min Typ Max Min Typ Max Min Typ Max Min Typ Max  
Propagation Delay  
tPLH/tPHL  
D to Q1  
EN to Q1  
Duty Cycle Skew2  
Input Swing3  
Differential 150  
Single Ended4 300  
Output Rise/Fall1  
(20%-80%)  
450  
600  
20  
450  
600  
20  
450  
600  
20  
450  
600  
20  
ps  
ps  
ps  
tSKEW  
5
5
5
5
VPP (AC)  
1000 150  
2000 300  
1000 150  
2000 300  
1000 150  
2000 300  
1000 mV  
2000 mV  
tr/tf  
80  
200  
80  
200  
80  
200  
80  
200  
ps  
1.  
2.  
3.  
4.  
Specified with outputs terminated through 50Ω resistors to VCC - 2V.  
Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.  
The peak-to-peak input swing is the range for which AC parameters are guaranteed.  
Range valid for AC coupled signals only.  
www.azmicrotek.com  
+1-480-962-5881  
7
Request a Sample  
May 2012, Rev 1.0  
Arizona Microtek, Inc.  
AZP92  
PECL/ECL ÷1, ÷2 Clock Generation  
Chip with Selectable Enable  
PACKAGE DIAGRAM  
MLP8  
Green/RoHS compliant/Pb-Free  
MSL=1  
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice.  
Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for  
any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of  
any product or circuit and specifically disclaims any and all liability, including without limitation special,  
consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of  
others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems  
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc.  
product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona  
Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold  
Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all  
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of  
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that  
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.  
www.azmicrotek.com  
+1-480-962-5881  
8
Request a Sample  
May 2012, Rev 1.0  
厂商 型号 描述 页数 下载

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