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CYIL1SM1300AA

LUPA-1300 1.3 MPxl High Speed CMOS

Image Sensor

Main Features

The main features of the image sensor are identified as:

■ SXGA resolution: 1280 x 1024 active pixels.

■ 14 µm²square pixels (based on the high-fill factor active pixel

sensor technology of FillFactory (US patent No. 6,225,670 and

others)).

■ Pixel rate of 40 MHz using 16 parallel outputs.

■ Random programmable windowing.

■ Dual slope integration possible.

■ 145-pin PGA package.

■ Peak QE x FF of 15%.

■ Optical format: 1,43" (17.9 mm x 14.3 mm).

■ Opticaldynamicrange:62dB(1330:1)insingleslopeoperation

and 80 to100 dB in double slope operation.

■ 16 parallel analog output amplifiers.

■ Synchronous pipelined shutter.

Preamble

■ Processing is done in a CMOS 0.50 µm triple metal process.

Overview

This document describes the interfacing and the driving of the

image sensor LUPA-1300, which is a 1280 by 1024 CMOS pixel

array working at 450 frames/sec. The sensor is an active pixel

sensor with synchronous shutter. The pixel size is 14 * 14 µm

and the sensor is designed to achieve a fame rate of 450

frames/sec at full resolution. This high frame rate can be

achieved by 16 parallel output amplifiers each working at 40 MHz

pixel rate.

The readout speed can be boosted by means of windowed

Region Of Interest (ROI) readout. High dynamic range scenes

can be captured using the double slope functionality.

The sensor uses a 3-wire Serial-Parallel Interface (SPI). It is

housed in a 145-pin ceramic PGA package.

In the following sections the different modules of the image

sensor are discussed more into detail. This data sheet allows the

user to develop a camera-system based on the described timing

and interfacing.

Ordering Information

Marketing Part Number

CYIL1SM1300AA-GDC

Description

Package

Mono with Glass

145-pin PGA

CYIL1SM1300AA-GWC

Mono without Glass

Cypress Semiconductor Corporation

Document Number: 38-05711 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 21, 2009

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Specifications

General Specifications

Table 1. General Specifications of the LUPA Sensor

Parameter

Pixel Architecture

Pixel Size

Specification

6T-pixel

Remarks

Based on the high-fill factor active pixel sensor technology of FillFactory.

14 µm x 14 μm

The resolution and pixel size results in a 17.9 mm x 14.3 mm optical active

area.

Resolution

1280 x1024

Pixel Rate

640 MHz

Using a 20 MHz system clock and 16 parallel outputs.

Full snapshot shutter with variable integration time.

Frame rate increase possible with ROI read out and/or sub sampling.

PGA pins with 0.46 mm diameter.

Shutter Type

Full Frame Rate

Package

Pipelined Snapshot Shutter

450 frames/second

Pin Grid Array 145 Pins

Electro-Optical Characteristics

Overview

Table 2. Electrical-Optical Specifications of the LUPA-1300 Sensor

Parameter Specification

<3% RMS

Remarks

FPN

<10% p/p.

PRNU

2% RMS

16 µV/electron

1V

Half saturation.

Conversion Gain

Output Signal

Amplitude

Unity gain.

Saturation Charge

62.500 e-

Is more then 60.000 (=1V/16µV/e-) due to non-linearity in saturated region.

Average white light.

1500 V.m2/W.s

8.33 V/lµx.s

21.43 V/lµx.s

50%

Sensitivity

Visible band only (180 lx = 1 W/m2).

Visible + NIR (70 lx = 1 W/m2).

Fill Factor

100%-metal and polycide coverage.

See spectral response curve.

Peak QE * FF

Peak SR * FF

15%

0.08 A/W

X: 67%

Y: 66%

At Nyquist.

MTF

Temporal Noise

S/N Ratio

45e-

Dark environment, measured at T=21 ^oC.

1330 = 60000:45 = 62 dB.

1330

Spectral Sensitivity

Range

400 - 1000 nm

Parasitic Light

Sensitivity

< 0.5%

i.e., sensitivity of the storage node compared to the sensitivity of photodiode.

Power Dissipation

Output Impedance

900 mWatt

Typical.

200-300 Ω

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Features and General Specifications

Table 3. Features and General Specifications

Feature

Specification/Description

Electronic Shutter Type

Windowing (ROI)

Readout Sequence

Extended Dynamic Range

X Clock

Synchronous pipelined shutter with variable integration time.

Programmable via SPI.

Progressive scan.

Double slope extended dynamic range.

20 MHz (pixel rate of 40 MHz).

16.

Number of Outputs

Image core supply: Range from 3V to 6 V.

Analog Supply: Nominal 5 V.

Digital: Nominal 5 V.

Supply Voltage Vdd

Logic Levels

5V (digital supply)

Operational Temperature Range

Package

0°C to 60°C, with degradation of dark current.

145-pins Pin Grid Array (PGA).

Spectral Response Curve

Figure 1. Spectral Response Curve

0.12

0.1

0.08

0.06

0.04

0.02

QE=10%

QE=15%

QE= 20%

LUPA-1300

0

400

500

600

700

800

900

1000

Wavelength (nm)

Figure 1 shows the spectral response characteristic. The curve

is measured directly on the pixels. It includes effects of

non-sensitive areas in the pixel, e.g., interconnection lines. The

sensor is light sensitive between 400 and 1000 nm. The peak QE

* FF is 15% approximately between 500 and 700 nm.

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Photo-Voltaic Response Curve

Figure 2. Output Voltage as Function of Number of Electrons

As one can see from Figure 2, the output signal ranges between

0 V to 1.1 V and is linear until around 800 mV. Note that the upper

part of the curve (near saturation) is actually a logarithmic

response.

Electrical Specifications

Absolute Maximum Ratings

Table 4. Absolute Maximum Ratings¹

Symbol

V_DC

Parameter

Value

-0.5 to +7

Unit

V

DC Supply Voltage

DC Input Voltage

DC Output Voltage

V_IN

V_OUT

I

0.5 to VDC + 0.5

-0.5 to VDC + 0.5

V

DC current per pin; any Single Input or Output (see Table 7 for more Exceptions). ± 50

mA

°C

T_STG

T_L

Storage Temperature Range

-40 to 100

300

Lead Temperature (10 Seconds Soldering)

Note

1. Absolute Ratings are those values beyond which damage to the device may occur.

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Recommended Operating Conditions

Table 5. Recommended Operation Conditions

Symbol

Parameter²

Typical

Unit

V

Vdda

Power Supply Column Read Out Module

5

Vdd

Power Supply Digital Modules

V

Vddr

Power Supply Logic For Drivers

Power Supply Output Stages

5

V

Voo

5

V

Vres

Power Supply Reset Drivers

6

V

Vres_ds

Vmem_h

Vmem_l

Vpix

Power Supply Multiple Slope Reset Driver

Power Supply Memory Element (High Level)

Power Supply Memory Element (Low Level)

Power Supply Pixel Array

4.5

6

V

4.5

5.5

V

Vstable

Power Supply Output Stages. Decouples Noise on the Voo Supply from the Output

Signal.

V

Sensor Architecture

The image sensor consists of the pixel array, the column readout

electronics, X-and Y addressing, on-chip drivers, the output

amplifiers and some logic.

Notes

2. All parameters are characterized for DC conditions after thermal equilibrium has been established.

3. Unused inputs must always be tied to an appropriate logic level, e.g., either VDD or GND.

4. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however it is recommended that normal precautions

be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit.

5. All power supplies should be sufficiently decoupled because spikes and drops in the power supplies will be immediately visible in the analog output signals.

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Figure 3. Architecture of the LUPA Sensor

Sensor

Imager core

Control signals

Drivers for the pixel array signals

Pixel

System clock

40 MHz

Y-addressing

16

15

Pixel core

14

Column amplifiers

Analog multiplexer

Output

amplifiers

3

2

1

X-addressing

SPI interface

Figure 3 shows a schematic representation of the image sensor

on which the different modules are displayed.

Figure 4. Schematic Representation of Synchronous Pixel

as used in LUPA Design

The image core is a pixel array of 1280 * 1024 pixels each of 14

*14 μm2 in size. The readout is from bottom left to top right. To

obtain a frame rate of 450 frames/sec for this resolution, 16

output amplifiers each capable of driving an output capacitance

of 10 pF at 40 MHz are placed on the image sensor.

Vpix

Row

select

reset

samp le

The column readout amplifiers bring the pixel data to the output

amplifiers. The logic and the x- and y addressing controls the

image sensor so that progressive scan and windowing is

possible. Extra pixel array drivers are foreseen at the top of the

image sensor to control the global pixel array signals.

precharge Mem

Pixel Architecture

The active pixels allow synchronous shutter, i.e., all pixels are

illuminated during the same integration time, starting from the

same moment in time. After a certain integration time, the pixels

are readout sequentially. Readout and integration are in parallel,

which means that when the image sensor is readout, the

integration time for the next frame is ongoing. This feature

requires a memory element inside the pixel, which affects the

maximum fill factor. A schematic representation of the pixel is

given in Figure 4.

Note

6. The signals mentioned in Figure 4 are the internal signals generated by the internal drivers required to have the synchronous shutter feature.

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The photodiode is designed to obtain sensitivity as high as

possible for a dynamic range of at least 60dB. Consequently the

photodiode capacitance is 10 fF at the output, resulting in a S/N

of more than 60 dB as the rms noise level is within the expec-

tation of 45 noise electrons. The pixel was specially designed to

have a very low parasitic light sensitivity (<0.5%). The pixels are

based on the high-fill factor active pixel sensor technology of

FillFactory (US patent No. 6,225,670 and others).

To obtain a high frame rate, the complexity and the number of

stages in the column readout amplifiers must be minimized, so

that the power dissipation remains as low as possible, but also

to minimize the row blanking time. Figure 5 is a schematic repre-

sentation of the column readout structure. It consists of two parts.

The first part is a module that reduces the row blanking time. The

second part shifts the signal to the correct level for the output

amplifiers and allows multiplexing in the x-direction.

From the moment that a new row is selected, the pixel data of

that row is placed onto the columns of the pixel array. These

columns are long lines and have a large parasitic capacitance.

As the pixel is small, it is not possible to match the transistor

inside the pixel, which drives this column. Consequently, the first

module in the column readout amplifiers must solve the

mismatch between the pixel driver and the large column capac-

itance.

Column Readout Amplifiers

The column readout amplifiers are the interface between the

pixels and the output amplifiers. The pixels in the array are

selected line by line and the pixels of the selected line are

connected to the column readout amplifiers, which bring the pixel

data in the correct format to the output amplifiers.

Figure 5. Schematic Representation of Column Readout Structure

column

Shkol

Module 1 : track & hold or reference set method

Norow sel

Module 2 : signal conditioning and multiplexing

X-mux

Output stage

Output Amplifiers

16 output amplifiers each capable of working at 40 MHz pixel rate are placed equidistant on the bottom of the image sensor. These

output amplifiers are required to obtain a frame rate of 450 frames/sec. A single output stage, not only to reduce power, but also to

achieve the required pixel rate is designed. Figure 6 is a schematic representation of this module

Figure 6. Schematic Representation of Single Output Stage

Stabilize

Vstable

Out

power supply

In

Cload d 10

pF

Output stage

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Each output stage is designed to drive a load of 10 pF at a pixel

rate of 40 MHz. The load in the output stage determines this pixel

rate. In case the load capacitance is less than 10 pF, the load in

the output stage can increase, resulting in less power dissipation

of the output stages and consequently of the whole sensor.

Additionally, decreasing the load of the output stage allows

having more current available for the output stage to charge or

discharge the load capacitance to obtain a higher pixel rate.

X-Y Addressing and Windowing

The pixel array is readout by means of programmable X and Y

shift registers. The pixel array is scanned line-by-line and

column-by-column. The starting point in X and Y is defined

individually for each register and is determined by the address

downloaded by the Serial-Parallel Interface (SPI). Both registers

work in the same way. A sync pulse that sets the address pointer

to the starting address of each register, initializes them. A clock

pulse for the x- and y-shift register shifts the pointer individually

and makes sure that the sequential selection of the lines and

columns is correct.

To avoid variations on the supply voltage to be seen on the output

signal, a special module to stabilize the power supply is required.

This module that requires an additional supply voltage (Vstable)

allows variation on the supply voltage Voo without being seen on

the output signal.

Temperature Reference Circuits

One can also choose to have a passive load of chip instead of

the active output stage load. This deteriorates the linearity of the

output stages, but decreases the power dissipation, as the dissi-

pation in the load is external.

Temperature Diode

The most commonly used temperature measurement is

monitoring of the junction voltage of a diode, therefore we also

added a temperature diode to measure the temperature of the

silicon die. This diode junction voltage is generated by a "small",

forward biased, constant current flow (in between 10 and 100

µA).

Frame Rate and Windowing

Frame Rate Calculation

The frame period of the LUPA-1300 sensor can be calculated as

follows:

This junction voltage has a nearly linear relationship with the

temperature of the die with a typical sensitivity of about 430°C

per volt (2.3 mV per °C) for silicon junctions.

Frame period = FOT + (Nr.Lns* (RBT + pixel period * Nr. Pxs/16)

with:

Temperature Module

FOT: Frame Overhead Time = 1 us.

On the same image sensor we have foreseen a module to verify

the temperature on chip and the variation of the output voltage

(dark level of the pixel array) due to a temperature variation. This

module contains a copy of the complete signal path, including a

blind pixel, the column amplifiers and an output stage. It DC

response may serve a temperature calibration for the real signal.

The temperature functionality is given in Figure 7. Between room

temperature and 60^oC we see a voltage variation of about 0.5

mV.

Nr. Lns: Number of Lines read out each frame (Y).

Nr. Pxs: Number of pixels read out each line (X).

RBT: Row blanking time = 200 ns (nominal; can be further

reduced).

Pixel period: clock_x period/2 (both rising and falling edge are

active edges).

- Example 1 read out of the full resolution at nominal speed (40

MHz pixel rate):

Due to different applied supply voltages, as there are: Vreset,

Vmem, Vpix an offset between the output voltage of the temper-

ature sensor and the output of a black signal of the pixel array

can occur. Depending on the working conditions of the image

sensor one can fine-tune the temperature module with its voltage

supply. In case one has a 6V signal for reset and a 4-6V signal

for Vmem, a supply voltage of 5.5V for the temperature sensor

will result in a closer match between this temperature sensor and

the black level of the image sensor. Changing the supply voltage

of the temperature sensor results only in a shift of the output

voltage therefore the supply voltage of the temperature module

can be tuned to make the output of the module equal to the dark

signal of the pixel array at a certain working temperature.

Frame period = 5 us + (1024 * (200 ns + 25 ns * 1280/16) = 2.25

ms => 444 fps.

- Example 2 read out of 800x600 at nominal speed (40 MHz pixel

rate):

Frame period = 5 us + (600 * (200 ns + 25 ns * 800/16) = 871 us

=> 1148 fps.

- Example 3 read out of 640x480 at nominal speed (40 MHz pixel

rate):

Frame period = 5 us + (480 * (200 ns + 25 ns * 640/16) = 577 us

=> 1733 fps.

- Example 4 read out of the full resolution at nominal speed (40

MHz pixel rate) with reduced overhead time:

Frame period = 5 us + (1024 * (100 ns + 25 ns * 1280/16) = 2.15

ms => 465 fps.

Note

7. The LUPA-1300 is designed to drive a capacitive load, not a resistive. When one wants to transport the output signals over long distances (more than 1 inch),

make sure to place buffers on the outputs with high input impedances (preferably >1Mohms). This is necessary because the output impedance of the LUPA-1300

is between 200-300 Ω typically.

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Vsupply (V)

Vout at 21^oC

5

5.5

0.8

6

6.1

6.2

6.3

6.4

6.5

0.58

1.03

1.07

1.12

1.17

1.22

1.27

Figure 7. Output Voltage of Temperature Module Versus Temperature

1.13

1.11

1.09

1.07

1.05

1.03

1.01

0.99

6

6.1

6.2

25

35

45

55

65

75

Te m pe ra t u re ( °C )

Synchronous Shutter

In a synchronous (snapshot) shutter light integration takes place on all pixels in parallel, although subsequent readout is sequential.

Figure 8. Synchronous Shutter Operation

Line number

Time axis

Integration time

Burst Readout time

Figure 8 shows the integration and read out sequence for the synchronous shutter. All pixels are light sensitive at the same period of

time. The whole pixel core is reset simultaneously and after the integration time all pixel values are sampled together on the storage

node inside each pixel. The pixel core is readout line by line after integration.

Note

8. Note that the integration and readout cycle can occur in parallel.

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Figure 9. Integration and Readout in Parallel

Read frame I

Read frame I + 1

Integration I + 2

Integration I + 1

The control of the readout of the frame and of the integration time are independent of each other with the only exception that the end

of the integration time from frame I+1 is the beginning of the readout of frame I+1.

Non-Destructive Readout (NDR)

The sensor can also be read out in a non-destructive way. After a pixel is initially reset, it can be read multiple times, without resetting.

The initial reset level and all intermediate signals can be recorded. High light levels will saturate the pixels quickly, but a useful signal

is obtained from the early samples. For low light levels, one has to use the later or latest samples.

Figure 10. Principle of Non-Destructive Readout

time

Essentially an active pixel array is read multiple times, and reset

only once. The external system intelligence takes care of the

interpretation of the data. Table 6 summarizes the advantages

and disadvantages of non-destructive readout.

Operation and Signaling

One can distinguish the different signals into different groups:

■ Power supplies and grounds

■ Biasing and analog signals

■ Pixel array signals

■ Digital signals

Table6. AdvantagesandDisadvantagesof Non-Destructive

Readout

Advantages

Disadvantages

Low noise – as it is true CDS. System memory required to

record the reset level and the

■ Test signals

intermediate samples.

Power Supplies and Grounds

High sensitivity – as the

conversion capacitance is kept each pixel, thus higher data

rather low. throughput.

Requires multiples readings of

Every module on chip, as there are: column readout, output

stages, digital modules, drivers, has its own power supply and

ground. Off chip the grounds can be combined, but not all power

supplies may be combined. This results in several power

supplies, but is required to reduce electrical crosstalk and to

improve shielding.

High dynamic range – as the Requires system level digital

results include signal for short calculations.

and long integrations times.

On chip we have the ground lines also separately for every

module to improve shielding and electrical crosstalk between

them. The only special ground is "Gnd_res", which can be used

to remove the blooming if any and which can improve optical

crosstalk.

An overview of the supplies is given in Table 7. The power

supplies related to the pixel array signals are described in the

paragraph concerning the pixel array signals.

Note

9. Normal application does not require this Gnd_res and it can be connected to ground.

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Table 7. Power Supplies Used in the LUPA Design

Name

Vdda

Max Current

50 mA

Typ.

Max

Description

Power supply column readout module

5V

Vdd

20 mA

Power supply digital modules

Power supply output stages

Voo

85 mA

Vstable

6 mA

5.5V

6V

Power supply output stages. Decouples noise on the Voo supply from the

output signal.

Vpix

200 mA

20 mA

50 mA

4.5V

5V

Power supply pixel array

Vddr

Power supply logic for drivers

Power supply to reset the pixels

Power supply for high DC level Vmem

Power supply for low DC level Vmem

Vres

6V

VmemH

VmemL

6V

4.5V

The maximum currents mentioned in Table 7 are peak currents. The power supplies need to be able to deliver these currents especially

the maximum supply current for Vpix.

It is important to notice that we don't do any power supply filtering on chip and that noise on these power supplies can contribute

immediately to the noise on the signal. Especially the voltage supplies Vpix and Vdda are important to be well noise free. With respect

to the power supply Voo, a special decoupling is used, for which an additional power supply Vstable is required.

Figure 11a. Schematic of Typical Decoupling of Power Supply (Source Current)

Figure 11b. Schematic of Typical Decoupling of Power Supply (Source Current)

Notes

10. At start up the Vpix supply draws a very high current (> 300 mA) which has to be limited (max. 200 mA) otherwise the bond wires of the particular supply will

be destroyed. One should make sure that the Vpix power supply limits the current draw to the Vpix sensor supply pins to max. 200 mA. When the bond wires

of Vpix are destroyed the sensor isn't operating normally and will not meet the described specifications.

11. VmemL must sink a current, not source it. All power supplies should be decoupled very close to the sensor pin (typical 100 nF to filter high frequency dips and

10 microF to filter slow dips). A typical decoupling circuit is shown in Figure 11. Vres_ds must be able to sink and source current.

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Biasing and Analog Signals

Besides the biasing signals, the only analog signals are the output signals Out1 - Out16. Each output signal is analog with respect to

the voltage level, but is discrete in time. This means that on the speed of Clock_x, the outputs change to a different level, depending

on the illumination of the corresponding pixels.

The biasing signals determine the speed and power dissipation of the different modules on chip. These biasing signals have to be

connected trough a resistor to ground or power supply and should be decoupled with a capacitor. If the sensor is working properly,

each of the biasing signals will have a dc-voltage depending on the resistor value and on the internal circuitry. These dc-voltages can

be used to check the operation of the image sensor. Table 8 gives the different biasing signals, the way they should be connected,

and the expected dc-voltage. Due to small process variations, these dc-voltages change from chip to chip and 10% variation is

possible.

Table 8. Overview of Biasing Signals

Signal

Comment

Expected DC Level

Pre_load

Col_load

Psf_load

Nsf_load

Load_out

Connect with 10 KΩ to Vdda and capacitor of 100 nF to Gnd

Connect with 2 MΩ to Vdda and capacitor of 100 nF to Gnd

Connect with 240 KΩ to Gnd and capacitor of 100 nF to Vdda

Connect with 100 KΩ to Vdda and capacitor of 100 nF to Gnd

Connect with 27 KΩ to Voo and capacitor of 100 nF to Gnd

Connect with 27 KΩ to Gnd and capacitor of 100 nF to Vdd

2.0V

0.9V

3.7V

1.3V

1.6V

2.8V

Decx_load

Decy_load

Each resistor controls the speed and power dissipation of the corresponding module, as this resistor determines the current required

to charge and/or discharge internal nodes inside the module.

A decoupling with a small capacitor is advisable to reduce the HF noise onto the analog signals. Only the capacitor on the Pre_load

signal can be omitted.

Pixel Array Signals

Figure 4 is a schematic representation of the pixel as used in the LUPA design. The applied signals to this pixel are: reset, sample,

Precharge, Vmemory, row select and Vpix. These are internal generated signals derived by on-chip drivers from external applied

signals. Consequently it is important to understand the relation between both internal and external signals and to understand the

operation of the pixel.

The timing of the pixel is given in Figure 12 in which only the internal signals are given.

Figure 12. Internal Timing of the Pixel

At the end of the integration time, the information on the photodiode node needs to be sampled and stored onto the pixel memory,

required to allow synchronous shutter. To do this, we need the signals "Precharge" and "Sample". "Precharge" resets the pixel memory

and "Sample" places the pixel information onto the pixel memory. Once this information stored, the readout of the pixel memories can

start in parallel with a new integration time. An additional signal "Vmem" is needed to obtain a larger output swing.

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Except from Vpix power supply, drivers generate the other pixel signals on chip. The external signals to obtain the required pulses

consist of two groups. One is the group of digital signals to indicate when the pulse must occur and the other group is dc-supply lines

indicating the levels of the pulses. Table 9 summarizes the relation between the internal and external pixel array signals.

Table 9. Overview of Internal and External Pixel Array Signals

Internal Signal

Precharge

Sample

Vlow

Vhigh

External Control Signal

Precharge

Low DC Level

Gnd

High DC Level

Vddr

0

5V

0

Sample

Gnd

Vddr

Reset

0V

4.5V

4 - 6V

6V

Reset & Reset_ds

Mem_hl

Gnd_res

Vmem_l

Vres & Vres_ds

Vmem_h

Vmemory

The Precharge and Sample signals are the most straightforward

signals. The internal signal Vmemory is a signal that switches

between a low voltage (3.5 - 5.5V) and a high voltage (5-6V). The

signal Mem_hl controls the applied level and the power supply

lines Vmem_l and Vmem_h determine the low and high

dc-levels.

■ Load_addr: when the SPI register is downloaded with the

desired address, the signal Load_addr signal loads the x-and

y-address into their address register as starting point of the

window of interest.

■ Sh_col: control signal of the column readout. Is only used in

sample & hold mode (see “Timing” on page 14).

The Reset signal is due to the dual slope technique a little more

complex. In case the dual slope is not used, the reset signal is

straightforward generated from the external reset pulse. In this

case the supply voltage Vres determines the level to which the

pixel is resetted.

■ Norow_sel: Control signal of the column readout. Is only used

in Norow_sel mode (see “Timing” on page 14).

■ Pre_col: Control signal of the column readout to reduce row

blanking time

In case the dual slope operation is desired, one needs to give a

second pulse to a lower reset level during integration. This can

be done by the control signal Reset_ds and by the power supply

Vres_ds that defines the level to which the pixel has to be

resetted.

■ Sel_active: activates the active load on chip for the output

amplifiers. If not used, a passive load can be used or one can

use this signal to put the output stages in standby mode

■ Eos_x: end of scan signal: an output signal, indicating when

end of line is reached. Is not generated when doing windowing

If a pulse is given on the Reset_ds signal, a second pulse on the

internal reset line is generated to a lower level, determined by

the supply Vres_ds. If no Reset_ds pulse is given, the dual slope

technique is not implemented.

■ Eos_y: end of scan signal: is an output signal, indicating when

the end of the frame is reached. Is not generated when doing

windowing.

Note that Reset is dominant over Reset_ds, which means that

the high voltage level will be applied for reset, if both pulses occur

at the same time.

All digital signals are buffered and filtered on chip to remove

spikes and achieve required on-chip driving speed. Applied

digital signals should be capable of driving 20 pF input capaci-

tance.

The external control signals should be capable of driving input

capacitance of about 20 pF.

Test Signals

Digital Signals

Some test signals are required to evaluate the optical perfor-

mance of the image sensor. Other test signals allow us to test

internal modules in the image sensor and some test signals will

give us information concerning temperature and influence of the

temperature on the black level.

The following digital signals control the readout of image sensor:

■ Sync_y: Starts the readout of the frame or window at the

address defined by the y-address register. This pulse synchro-

nizes the y-address register: active high. This signal is at the

same time the end of the frame or window and determines the

window width.

Evaluation on optical performance (spectral response, fill factor):

■ Array_diode

■ Full_diode

■ Clock_y:Clockofthey-register. Ontherisingedgeofthisclock,

the next line is selected.

Evaluation of the output stages:

■ Black

■ Sync_x: Starts the readout of the selected line at the address

defined by the x-address register. This pulse synchronizes the

x-address register: active high. This signal is at the same time

the end of the line and determines the window length.

■ Dc_black

Evaluation of the x and y -shift registers:

■ Eos_x

■ Address: the x- and y-address is downloaded serial through

this signal.

■ Eos_y

Indication of the temperature and influence on the black level:

■ Clock_spi: clock of the serial parallel interface. This clock

downloads the address into the SPI register.

■ Temp_diode_n

■ Temp_diode_p

Document Number: 38-05711 Rev. *D

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Timing

Timing of the Pixel Array

The timing of the image sensor can be divided in two major parts. The first part of the timing is related with the timing of the pixel

array. This implies the control of the integration time, the synchronous shutter operation, and the sampling of the pixel information

onto the memory element inside each pixel. The signals needed for this control are described earlier and Figure 12 shows the timing

of the internal signals. Figure 13 should make the timing of the external signals clear.

Figure 13. Timing of pixel array. All External Signals are Digital Signals Between 0 and 5V.

Reset_ds Only Required in Case Dual Slope is Desired.

Table 10. Typical Timings of Pixel Array

Symbol Name

preferred not to be less than 10 sec. The minimal integration time

is the minimal time between the falling edge of reset and the

rising edge of sample. Keeping the slow fall times of the corre-

sponding internal generated signals, a minimal integration time

is about 2 sec. An additional reset pulse can be given during

integration by Reset_ds to implement the double slope

integration mode.

Value

> 5 μsec

a

Mem_HL

b

c

d

e

f

MEM_HL -Precharge

Precharge

> 200 nsec

> 500 nsec

> 3.9 μsec

> 400 nsec

> 2 μsec

Sample

Readout of Pixel Array

Precharge-Sample

Integration time

Once the photodiode information is stored into the memory

element in each pixel, the total pixel array of 1280 * 1024 needs

to be readout in less than 2 msec (2 msec - frame overhead time

= 1995 μsec). Additionally, it is possible that only a part of the

whole frame is read out. This is controlled by the starting address

that has to be downloaded and from the end address, which is

controlled by the synchronisation pulses in x- and y direction.

The readout itself is straightforward. Line by line is selected by

means of a sync-pulse and by means of a Clock_y signal. Once

a new line selected, it takes a while (row blanking time) before

the information of that line is stable. After this row blanking time

the data is multiplexed in blocks of 16 to the output amplifiers. A

sync-pulse and a clock pulse in the x-direction do this multi-

plexing.

The timing of the pixel array is straightforward. Before the frame

is read, the information on the photodiode needs to be stored

onto the memory element inside the pixels. This is done by

means of the signals Vmemory, Precharge and Sample.

Precharge sets the memory element to a reference level and

Sample stores the photodiode information onto the memory

element. Vmemory pumps up this value to reduce the loss of

signal in the pixel and this signal must be the envelop of

Precharge and Sample. After Vmemory is high again, the

readout of the pixel array can start. The frame blanking time or

frame overhead time is thus the time that Vmemory is low, which

is about 5 sec. Once the readout starts, the photodiodes can all

be initialised by reset for the next integration time. The duration

of the reset pulse indicates the integration time for the next

frame. The longer this duration, the shorter the integration time

becomes. Maximum integration time is thus the time it takes to

readout the frame, minus the minimum pulse for reset, which is

Figure 14 shows the y-address timing. The top curves are the

selection signals of the pixels, which are sequentially active,

starting by the sync pulse. The next line is selected on the rising

edge of Clock_y. It is important that the Sync_y pulse covers 1

rising edge of the Clock_y signal. Otherwise the synchronization

will not work properly.

Document Number: 38-05711 Rev. *D

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Figure 14. Timing of y Shift Register

The first selected line after a Sync_y pulse is the line defined by

the y-address in the y-address register. Every select line is in

principle 1 clock period long, except for the first select line. The

first select line goes high as soon as a Sync_y pulse occurs

together with a rising edge of Clock_y. On the next rising edge

of Clock_y, the next row is selected, unless Sync_y is still active.

In Figure 15, a short Sync_y pulse makes sure that the first row

is selected during 1 period of Clock_y.

Once a line is selected, it needs to stabilize first of all, which is

called the row blanking time, and secondly the pixels need to be

read out. Figure 15 shows the principle.

Figure 15. Readout Time of Line is Sum of Row Blanking Time and on Line Readout Time

Symbol

Name

Value

> 100 nsec

a

b

c

d

Sync_Y

Sync_Y-Clock_Y

Clock_Y-Sync_Y

Sync_X -Clock_X

> 50 nsec

> 50 ns

Notes

12. The applied Clock_x, is filtered on chip to remove spikes. This is especially required at these high speeds. This filtering results in an on chip Clock_x that is

delayed in time with about 10 nsec. In other words, the data at the output has, with respect to the external Clock_x, a propagation delay of 20 nsec. This 20 nsec

come from 10 nsec of the generation of the internal Clock_x and 10 nsec due to other on chip generated signals.

13. The analog signal will come out of the sensor with a 60/40 duty cycle. Therefore, it is very important to have a very flexible ADC clock phase. This is necessary

to fine-tune the ADC to sample the analog signal at the correct moment.

Document Number: 38-05711 Rev. *D

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Once the information of the selected line is stable the addressing

of the pixels can start. This is done by means of a Sync_x and a

Clock_x pulse in the same way as the Y-addressing. The Sync_x

pulse downloads the address in the address register into the shift

register and connects the first block of 16 columns to the 16

outputs.

Reduced Row Overhead Time Timing

The row overhead time is the time between the selection of lines

that one has to wait to get the data stable at the column ampli-

fiers.

This row overhead time is a loss in time, which should be

reduced as much as possible.

In fact on chip is a 32-output bus instead of 16, but on the rising

edge of Clock_x the first 16 columns of the bus are connected to

the output stages. On the falling edge of Clock_x, the last 16

columns of the selected bus are connected to the output stages.

Reduced Timing

A straightforward way of reducing the R.O.T is by using a sample

and hold function.

The timing of the x-shift register is comparable with the timing of

the y-shift register, only that the timing is much faster. Again the

synchronization pulse must be high on the rising edge of

Clock_x.

By means of Sh_col the analog data is tracked during the first

200 nsec during the selection of a new set of lines. After 200

nsec, the analog data is stored. The ROT is in this case reduced

to 200 nsec, but as the internal data was not stable yet dynamic

range is lost because not the complete analog levels are reached

yet after 200 ns.

Figure 16 shows this principle. Sh_col is now a pulse of 100

ns-200 ns starting 25 ns after Norowsel. The duration of Sh_col

is equal to the ROT. The shorter this time the shorter the ROT

will be however this lowers also the dynamic range.

Figure 16. Reduced Standard ROT by Means of Sh_col Signal.

pre_col (short pulse), Norowsel (short pulse), and Sh_col (large pulse).

Document Number: 38-05711 Rev. *D

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Standard Timing (ROT = 200 ns

Figure 17. Only pre_col and Norowsel Control Signals are Required. SH_col is made active low.

In this case, the control signals Norowsel and pre_col are made

active for about 50 nsec from the moment the next line is

selected. The time these pulses have to be active is related with

the biasing resistance Pre_load. The lower this resistance, the

shorter the pulse duration of Norowsel and pre_col may be. After

these pulses are given, one has to wait for 180 nsec before the

first pixels can be sampled. For this mode Sh_col must be made

active low.

Timing of Serial Parallel Interface (SPI)

The serial parallel interface is used to upload the x- and

y-address into the x- and y-address registers. This address is the

starting point of the window of interest and is uploaded in the shift

register by means of the corresponding synchronization pulse.

The elementary unit cell of the serial to parallel interface is shown

in Figure 18. 16 of these cells are connected in parallel, having

a common Load_addr and Clock_spi form the entire uploadable

address block. The uploaded addresses are applied to the

sensor on the rising edge of signal Load_addr.

Figure 18. Schematic of SPI

16 outputs to sensor : 6 x-address

bits and 10 y-address bits

To address registers

Address

D

Q

Clock_spi

Load_address

C

E ntire uploadable address block

Load_addr

Address_in

Clock_spi

D

Address_out

Clock_spi

C

address

A1

A2

A3

A16

Unity Cell

Load_addr

command

applied to

sensor

The SPI clock can have a frequency of 20 MHz and the data is loaded into the register at the rising edge. The load_addr pulse should

go high together or after the last falling edge of the SPI_clock (see Figure 18).

The Y-address has to be applied first and the X-address last. With respect to the timing in Figure 18, A1 corresponds with the least

significant bit of the Y-address (Y0) and A16 corresponds with the most significant bit of the X-address (X5). The Y-address is a 10

bit and the X-address is a 6-bit address register.

Document Number: 38-05711 Rev. *D

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If the X-address register is 6-bit wide this means that 64 values

can be uploaded in this register. The X-start position however

can only be adjusted with steps of 32 so only the 40 LSB's are

accepted by the internal decoder (32 x 40=1280). The Y-address

register is 10 bit wide (1024 values), so the Y-start address can

be adjusted on a line by line basis.

Startup

When starting the sensor the following sequence should be

followed:

1. Apply all power supplies.

2. Upload SPI register.

3. Start driving/clocking of the sensor.

Make sure that the power supplies are completely stable before

the SPI is uploaded and the driving of the sensor can start.

Pin Configuration

The LUPA-1300 sensor will be packed in a PGA package with 145 pins. Each bond pad consists of 2 pad openings, one for wafer

probing and one for bonding. Table 11 gives an overview of the pin names and their functionality.

Table 11. Pin Description of Assembled LUPA-1300 Sensor in PGA 144 Package

fp

Name

Function

Description

B3

C3

D3

A2

B2

E3

C2

D2

E2

A1

F3

F2

B1

C1

D1

G3

E1

G2

F1

G1

H3

H2

H1

J1

1

n.c.

Not connected

2

n.c.

3

Voo

Supply 5V

Supply voltage output stages: 5V

Ground of the sensor

Output 1

4

Gnd

Out1

Voo

Ground

5

Analog out

Supply 5V

Analog out

Ground

6

Supply voltage output stages: 5V

Output 2

7

Out2

Gnd

Out3

Voo

8

Ground of the sensor

Output 3

9

Analog out

Supply 5V

Analog out

Ground

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Supply voltage output stages: 5V

Output 4

Out4

Gnd

Out5

Voo

Ground of the sensor

Output 5

Analog out

Supply 5V

Analog out

Ground

Supply voltage output stages: 5V

Output 6

Out6

Gnd

Out7

Voo

Ground of the sensor

Output 7

Analog out

Supply 5V

Analog out

Ground

Supply voltage output stages: 5V

Output 8

Out8

Gnd

Out9

Voo

Ground of the sensor

Output 9

Analog out

Supply 5V

Analog out

Ground

Supply voltage output stages: 5V

Output 10

Out10

Gnd

Out11

Voo

Ground of the sensor

Output 11

J2

Analog out

Supply 5V

Analog out

Ground

J3

Supply voltage output stages: 5V

Output 12

K1

K2

L1

K3

L2

Out12

Gnd

Out13

Voo

Ground of the sensor

Output 13

Analog out

Supply 5V

Analog out

Supply voltage output stages: 5V

Output 14

Out14

Document Number: 38-05711 Rev. *D

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Table 11. Pin Description of Assembled LUPA-1300 Sensor in PGA 144 Package (continued)

Pin fp Name Function Description

Ground

M1

N1

L3

32

33

34

35

36

37

38

39

40

41

42

43

Gnd

Out15

Voo

Ground of the sensor

Output 15

Analog out

Supply 5V

Analog out

Ground

Supply voltage output stages: 5V

Output 16

M2

P1

N2

M3

P2

N3

N4

N5

P3

Out16

Gnd

Voo

Ground of the sensor

Supply 5V

Supply voltage output stages: 5V

n.c.

Gnd

Voo

Ground

Ground of the sensor

Supply 5V

Biasing

Supply voltage output stages: 5V

Vstable

Supply voltage to stabilize output stages: 5.5V

Load_out

Analog bias for output amplifiers 27 KΩ to Voo and capacitor

of 100 nF to ground

P5

P4

Q1

N6

P6

Q2

Q3

44

45

46

47

48

49

50

Dc_black

Vdd

Testpin 6

Supply 5V

Ground

dc-black signal required to characterize the output stages

Supply voltage digital modules: 5V

Ground of the sensor

Gnd

Vdda

Gnd

Supply 5V

Ground

Supply voltage analog modules: 5V

Ground of the sensor

Vpix

Supply 4.5V

Digital I/O

Supply voltage pixel array: 4.5V

Eos_x

End of scan signal of the x-register: active high pulse indicates

the end of the shift register is reached

Q4

N7

P7

Q5

51

52

53

54

Nsf_load

Psf_load

Col_load

Pre_load

Biasing

Analog bias for column stages: 100 KΩ to Vdda and capacitor

of 100nF to ground

Analog bias for column stages: 240 KΩ to gnd and capacitor

of 100 nF to Vdda

Analog bias for column stages: 2 MΩ to Vdda and capacitor

of 100 nF to ground

Analog bias for column stages: 10 KΩ to Vdda and capacitor

of 100 nF to ground

Q6

Q7

N8

P8

Q8

Q9

P9

N9

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

n.c.

Array_diode

Testpin 3

Testpin 4

Testpin 1

Testpin 2

Array of pixels as designed in pixel array

Full diode with same array as array diode: 140 * 70 μm²

Temperature diode p side

Full_diode

Temp_diode_p

Temp_diode_n

Temperature diode n side

n.c.

Vpix

Q10

Q11

Q12

P10

N10

Q13

P11

Supply 4.5V

Supply voltage pixel array: 4.5V

Document Number: 38-05711 Rev. *D

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Table 11. Pin Description of Assembled LUPA-1300 Sensor in PGA 144 Package (continued)

Pin fp Name Function Description

Ground

P12

N11

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

Gnd

Vddr

n.c.

Ground of the sensor

Supply 5V

Supply voltage of the logic for the drivers: 5V

N12

P13

N13

M13

Q14

P14

L13

N14

M14

L14

Q15

K13

K14

P15

N15

M15

J13

Vmem_l

Vmem_h

Vres_ds

Vres

Gnd_res

n.c.

Supply

Voltage supply for Vmemory drivers: 3V- 5V (typ: 4.5V)

Voltage supply for Vmemory drivers: 4V- 6V (typ. 6V)

Voltage supply for reset double sloped drivers: 4V - 5V

Voltage supply for reset drivers: 5V - 6V (typ 6V)

Ground anti-blooming: 0 - 1V

Supply

Ground_ab

n.c.

L15

J14

n.c.

K15

J15

n.c.

H13

H14

H15

G15

n.c.

Gnd

Temp

Vdd

Ground

Testpin 5

Supply

Ground for temperature module

Dark level signal as function of temperature (Figure 7)

Supply voltage temperature module: 5V (has to be tunable to

adjust output of temperature module to analog output)

G14

G13

F15

F14

E15

F13

E14

D15

97

n.c.

98

n.c.

99

n.c.

100

101

102

103

104

n.c.

Reset_ds

Reset

Mem_hl

Sample

Digital I/O

Double slope reset of the pixels: active high pulse

Reset signal of the pixels: active high pulse

Control of Vmemory signal: 5V: Vmem_h, 0V: Vmem_l

Samples the photodiode voltage onto the memory cell inside

each pixel: active high pulse

C15

E13

105

106

Precharge

Eos_y

Digital I/O

Precharge the memory cell inside the pixel: active high pulse

End of scan signal of the y-register: active high pulse indicates

the end of the shift register is reached

D14

107

Gnd_Res

Ground_ab

Ground for the reset drivers. Can be used as anti-blooming

by applying 1V instead of 0V

B15

C14

108

109

Vres

Supply

Voltage supply for reset drivers: 5V - 6V (typ: 6V)

Vres_ds

Voltage supply for reset double sloped drivers: 4V - 5V

Document Number: 38-05711 Rev. *D

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Table 11. Pin Description of Assembled LUPA-1300 Sensor in PGA 144 Package (continued)

Pin fp Name Function Description

D13 Vmem_h Supply

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

Voltage supply for Vmemory drivers: 5V- 6V (typ: 6V)

Voltage supply for Vmemory drivers: 3V- 5V (typ: 4.5V)

Supply voltage of the logic for the drivers: 5V

Supply voltage pixel array: 4.5V

B14

C13

C12

C11

B13

B11

B12

A15

C10

B10

A14

A13

A12

C9

Vmem_l

Vddr

Supply

Supply 5V

Supply 4.5V

Supply 5V

Ground

Vpix

Vdd

Supply voltage digital modules: 5V

Gnd

Ground of the sensor

n.c.

B9

n.c.

A11

A10

A9

Load_addr

Address

Clock_spi

Decy_load

Digital I/O

Loads the address into the serial parallel interface (SPI)

Serial address to be downloaded into the SPI

Clock for the SPI

C8

Bias for y address register: 27KΩ to ground and capacitor of

100 nF to Vdd

B8

A8

A7

130

131

132

Sync_y

Digital I/O

Synchronisation of y-address register: active high

Clock of y-address register

Clock_y

Norow_sel

Control signal for Norow_sel mode to reduce row blanking

time: active low

B7

133

Sh_col

Digital I/O

Control signal for Sh_col mode to reduce row blanking time:

active low (baseline method): active low

C7

A6

A5

A4

134

135

136

137

Pre_col

Digital I/O

Biasing

Additional control signal for reducing the row blanking time

Synchronisation of the x-address register: active high

Clock of the x-address register

Sync_x

Clock_x

Decx_load

Bias for x address register: 27 KΩ to ground and capacitor of

100 nF to Vdd

B6

138

Black

Digital I/O

Controls black test function of the output stages: active high,

connect to ground if not used

C6

A3

B5

B4

C5

C4

139

140

141

142

143

144

Sel_active

Vdd

Digital I/O

Supply 5V

Ground

Supply 5V

Ground

Voo

set the output stages active or in standby mode: active low

Supply voltage digital modules: 5V

Ground of the sensor

Gnd

Vdda

Gnd

Supply voltage analog modules: 5V

Ground of the sensor

Voo

Supply voltage output stages: 5V

Document Number: 38-05711 Rev. *D

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Pad Positioning and Packaging

Package

Figure 19. Package Drawing of LUPA-1300 Sensor

8

,7

1

Ø

0,90

R

1

,2

7

40,01

7

,2

1

R

0,20

R

1

9

23,62

25,62

4,57

1,27

2,80

Document Number: 38-05711 Rev. *D

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Package and Die

Figure 20. Package Drawing with Die of LUPA-1300 Sensor

The center of the pixel array is located 200 μm to the right and 51 μm above the center of the package. The first pixel is located at

9160 μm to the left and 7219 to the bottom from this center. All distances are with a deviation of 50 μm.

Document Number: 38-05711 Rev. *D

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Color Filter

An optional color filter can be processed as well. The LUPA-1300 can also be processed with a Bayer RGB color pattern. Pixel (0,0)

has a red filter.

Figure 21. Color Filter Arrangement on Pixels

Glass Transmittance

Monochrome

A D263 glass will be used as protection glass lid on top of the LUPA-1300 monochrome sensors. Figure 22 shows the transmission

characteristics of the D263 glass.

Figure 22. Transmission Characteristics of D263 Glass Used as Protective Cover for LUPA-1300 Sensors

100

90

80

70

60

50

40

30

20

10

0

400

500

600

700

800

900

Wavelength [nm]

Document Number: 38-05711 Rev. *D

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Color

A S8612 glass will be used as NIR cut-off filter on top of the

LUPA-1300-C color image sensor. Figure 24 shows the trans-

mission characteristics of the S8612 glass.

For color devices a near infrared attenuating color filter glass is

used. The dominant wavelength is around 490 nm. Figure 23

shows the transmittance curve for the glass.

Figure 23. Transmission Characteristics of S8612 Glass Used as NIR Cut-Off Filter

Handling and Storage Precautions

Manual Soldering

When a soldering iron is used the following conditions should be

observed:

Handling Precautions

Special care should be given when soldering image sensors with

color filter arrays (RGB color filters), onto a circuit board, since

color filters are sensitive to high temperatures. Prolonged

heating at elevated temperatures may result in deterioration of

the performance of the sensor. The following recommendations

are made to ensure that sensor performance is not compromised

during end-users' assembly processes.

■ Use a soldering iron with temperature control at the tip.

■ The soldering iron tip temperature should not exceed 350°C.

■ The soldering period for each pin should be less than 5

seconds.

Precautions and Cleaning

Board Assembly

Avoid spilling solder flux on the cover glass; bare glass and

particularly glass with antireflection filters may be adversely

affected by the flux. Avoid mechanical or particulate damage to

the cover glass.

Device placement onto boards should be done in accordance

with strict ESD controls for Class 0, JESD22 Human Body Model,

and Class A, JESD22 Machine Model devices. Assembly

operators should always wear all designated and approved

grounding equipment; grounded wrist straps at ESD protected

workstations are recommended including the use of ionized

blowers. All tools should be ESD protected.

It is recommended that isopropyl alcohol (IPA) be used as a

solvent for cleaning the image sensor glass lid. When using other

solvents, it should be confirmed beforehand whether the solvent

will dissolve the package and/or the glass lid or not.

Document Number: 38-05711 Rev. *D

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Storage Conditions

Description

Temperature

Minimum

–10

Maximum

Units

°C

Conditions

at 15% RH

at 86% RH

66

38

–10

°C

Ordering Information

Marketing Part Number

CYIL1SM1300AA-GDC

Description

Package

Mono with Glass

145-pin PGA

CYIL1SM1300AA-GWC

Mono without Glass

Application Notes and FAQs

Q: Can the LUPA-1300 directly drive an ADC?

A: Yes, coupling the LUPA-1300 to a set of 16 ADC's close to the chip is the preferred way of operation. A suitable ADC must have thus

■ Input range equal or larger than the 1.2 V- 0 V sensor signal swing

■ In view of the LUPA-1300's S/N 10 bits are suitable. 11 or 12 bits may be considered too.

■ Input capacitance 20 pF or lower (high output loads will limit the speed). And no significant resistive loading.

■ Sampling frequency 40 MHz (or the application specific sample rate)

■ The ADC's input bandwidth must be sufficiently higher than the sampling frequency, in order to avoid RC contamination between

successive pixels.

Note

14. RH = Relative Humidity.

Document Number: 38-05711 Rev. *D

Page 26 of 29

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Q: How does the dual slope extended dynamic range mode works?

A:

Figure 24. Dual Slope Diagram

Reset

Read

Double slope reset

Reset level 1

Reset level 2

p1

p2

p3

p4

Saturation level

Double slope reset time (usually 5-10% of the total

integration time)

Total integration time

The green lines are the analog signal on the photodiode, which decrease as a result of exposure. The slope is determined by the

amount of light at each pixel (the more light the steeper the slope). When the pixels reach the saturation level the analog signal will

not change despite further exposure. As you can see without any double slope pulse pixels p3 and p4 will reach saturation before the

sample moment of the analog values, no signal will be acquired without double slope. When double slope is enabled a second reset

pulse will be given (blue line) at a certain time before the end of the integration time. This double slope reset pulse resets the analog

signal of the pixels BELOW this level to the reset level. After the reset the analog signal starts to decrease with the same slope as

before the double slope reset pulse. If the double slope reset pulse is placed at the end of the integration time (90% for instance) the

analog signal that would have reach the saturation levels aren't saturated anymore (this increases the optical dynamic range) at read

out. It's important to notice that pixel signals above the double slope reset level will not be influenced by this double slope reset pulse

(p1 and p2).

Look at the website to find pictures taken with double slope mode on: http://www.fillfactory.be/htm/technology/htm/dual-slope.htm.

Document Number: 38-05711 Rev. *D

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APPENDIX A: LUPA-1300 Evaluation Kit

For evaluating purposes a LUPA-1300 evaluation kit is available.

The LUPA-1300 evaluation kit consists of a multifunctional digital board (memory, sequencer and IEEE 1394 Fire Wire interface), an

ADC-board and an analog image sensor board.

Visual Basic software (under Win 2000 or XP) allows the grabbing and display of images and movies from the sensor. All acquired

images and movies can be stored in different file formats (8- or 16-bit). All setting can be adjusted on the fly to evaluate the sensors

specifications. Default register values can be loaded to start the software in a desired state.

Contact FillFactory (info@Fillfactory.com) for more information on the evaluation kit.

Document Number: 38-05711 Rev. *D

Page 28 of 29

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Document History Page

Document Title: CYIL1SM1300AA LUPA-1300 1.3 MPxl High Speed CMOS Image Sensor

Document Number: 38-05711

Orig. of

Change

Rev.

ECN

Issue Date

Description of Change

**

310396

370756

See ECN

SIL

Initial Cypress release.

*A

FPW

Additional timing specifications and removal of inconsistencies throughout the data

sheet.

*B

*C

*D

497127

649105

See ECN

QGS

FPW

Converted to Frame file.

Updated Ordering Information.

2766920 09/21/2009

NVEA

Update Ordering Information and template. Add part number to title.

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 38-05711 Rev. *D

Revised September 21, 2009

Page 29 of 29

Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided

that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.

All products and company names mentioned in this document may be the trademarks of their respective holders.

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