C9530
Table 6. Suggested Oscillator Crystal Parameters
Parameter Description
Fo
Conditions
Min
33.0
–
Typ.
33.33
–
Max.
33.5
±100
±100
5
Unit
MHz
PPM
PPM
PPM
Frequency
Tolerance
TC
TS
TA
See Note 5
Stability (TA –10 to +60C) Note 5
Aging (first year @ 25C) Note 5
Parallel Resonant, Note 5
The crystal’s rated load. Note 5
Note 6
–
–
–
–
Operating Mode
–
–
–
CXTAL
RESR
Load Capacitance
–
20
40
–
pF
Effective Series Resistance (ESR)
–
–
Ohms
Internal Crystal Oscillator
Output Clock Frequency Control
This device will operate in two input reference clock configu-
rations. In its simplest mode a 33.33-MHz fundamental cut
parallel resonant crystal is attached to the XIN and XOUT pins.
All of the output clocks have their frequency selected by the
logic state of the S0 and S1 control bits. The source of these
control signals is determined by the SMBus register Byte 0 bit
0. At initial power-up this bit is set of a logic 1 state and thus
the frequency selections are controlled by the logic levels
present on the device’s S(0,1) pins. If the application does not
use an SMBus interface then hardware frequency selection
S(0,1) must be used. If it is desired to control the output clocks
using an SMBus interface, then this bit (B0b0) must first be set
to a low state. After this is done the device will use the contents
of the internal SMBus register Bytes 0 Bits 3 and 4 to control
the output clock’s frequency.
In the second mode a 33.33-MHz input reference clock is
driven in on the IN clock from an external source. In this appli-
cation the XOUT pin must be left disconnected.
Output Clock Three-state Control
All of the clocks in Bank A (CLKA) and Bank B (CLKB) may be
placed in a three-state condition by bringing their relevant OE
pins (OEA and OEB) to a logic LOW state. This transition to
and from a state and active condition is a totally asynchronous
event and clock glitching may occur during the transitioning
states. This function is intended as a board level testing
feature. When the output clocks are being enabled and
disabled in active environments the SMBus control register
bits are the preferred mechanism to control these signals in an
orderly and predictable manner.
The following formula and schematic may be used to under-
stand and calculate either the loading specification of a crystal
for a design or the additional discrete load capacitance that
must be used to provide the correct load to a known load rated
crystal
(CXINPCB + CXINFTG + CXINDISC) x (CXOUTPCB) + CXOUTFTG) + CXOUTDISC
)
C =
L
(CXINPCB + CXINFTG + CXINDISC) + (CXOUTPCB) + CXOUTFTG) + CXOUTDISC
)
where:
CXTAL
= The load rating of the crystal.
CXINFTG
= The clock generators XIN pin effective device internal capacitance to ground.
CXOUTFTG = The clock generators XOUT pin effective device internal capacitance to ground.
CXINPCB = The effective capacitance to ground of the crystal to device PCB trace.
CXOUTPCB = The effective capacitance to ground of the crystal to device PCB trace.
CXINDISC = Any discrete capacitance that is placed between the XIn pin and ground.
CXOUTDISC = Any discrete capacitance that is placed between the XIn pin and ground.
Notes:
5. For best performance and accurate frequencies from this device, it is recommended but not mandatory that the chosen crystal meets or exceeds these specifi-
cations.
6. Larger values may cause this device to exhibit oscillator startup problems.
Document #: 38-07033 Rev. *C
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