请登录

免费注册
全部商品
电子元器件
方案中心
工业品
PDF资料
购物车 0
上传BOM

产品分类

找货询价

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

QQ咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

会员中心
购物车
技术支持

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

售后咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

AZP92_09

型号：

AZP92_09

描述：

ECL / PECL ÷ 1 ， ÷ 2时钟发生器芯片，可选择启用[ ECL/PECL ÷1, ÷2 Clock Generation Chip with Selectable Enable ]

品牌：

AZM[ ARIZONA MICROTEK, INC ]

页数：

9 页

PDF大小：

166 K

下载PDF手册
ARIZONA MICROTEK, INC.  
AZP92  
ECL/PECL ÷1, ÷2 Clock Generation Chip with Selectable Enable  
FEATURES  
PACKAGE AVAILABILITY  
•
Green and RoHS Compliant / Lead (Pb)  
Free Package Available  
3.0V to 5.5V Operation  
PACKAGE  
PART NO.  
MARKING  
NOTES  
MLP 8 (2x2) Green  
/ RoHS Compliant  
/ Lead (Pb) Free  
P1G  
<Date Code>  
•
•
•
AZP92NAG  
1,2  
Selectable Divide Ratio  
Selectable Enable Polarity and  
Threshold (CMOS/TTL or PECL)  
Selectable Input Biasing  
High Bandwidth for ≥1GHz  
-147 dBc/Hz (÷1), -150 dBc/Hz (÷2)  
Typical Noise Floor  
1
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)  
Tape & Reel.  
2
Date code format: “Y” for year followed by “WW” for week.  
•
•
•
•
•
Available in a MLP 8 (2x2) Package  
S Parameter and IBIS Model Files  
Available on Arizona Microtek Website  
DESCRIPTION  
The AZP92 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is  
selected with the DIV-SEL pin/pad. When DIV-SEL is open (NC), the AZP92 functions as a standard receiver. If  
DIV-SEL is connected to VEE, it functions as a ÷2 divider.  
A selectable enable is provided which also functions as a reset when the ÷2 mode is selected. Enable (EN)  
functionality is selected with the EN-SEL pin/pad which has three valid states: open (NC), VEE, or connected to VEE  
via a 20kΩ resistor. Leaving EN-SEL open or connecting it to VEE will select the EN pin/pad to function as an active  
high CMOS/TTL enable. When EN-SEL is open, an internal 75kΩ pull-up resistor is selected which enables the  
outputs whenever EN is left open. When EN-SEL is connected to VEE, an internal 75kΩ pull-down resistor is  
selected which disables the outputs whenever EN is left open.  
Connecting the EN-SEL to VEE with a 20kΩ resistor will select the EN pin/pad to function as an active low  
PECL/ECL enable with an internal 75kΩ pull-down resistor. In this mode, outputs are enabled when EN is left open  
(NC). This default logic condition can be overridden by connecting the EN to VCC with an external resistor of  
≤20kΩ. Refer to the enable truth table on the next page for detailed operation.  
MLP 8, 2x2 mm Package (AZP92NA)  
The AZP92NA provides a VBB with an 1880Ω internal bias resistor from D to VBB. This feature allows AC  
coupling with minimal external components. The VBB pin supports 1.5mA sink/source current and should be  
bypassed to ground or VCC with a 0.01 μF capacitor.  
NOTE: The specifications in the ECL/PECL tables are valid when thermal equilibrium has been established.  
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (623) 505-2414  
www.azmicrotek.com  
AZP92  
SIGNAL DESCRIPTION  
PIN/PAD FUNCTION  
D
Data Input  
Q/Q¯  
Data Outputs  
VBB/D¯  
EN  
EN-SEL  
DIV-SEL  
VEE  
Reference Voltage Output  
Enable/Reset Input  
Enable Logic Select  
Divide Ratio Select  
Negative Supply  
VCC  
Positive Supply  
ENABLE TRUTH TABLE  
EN  
CMOS Low or VEE  
CMOS High, VCC or NC Data  
CMOS Low, VEE or NC  
CMOS High or VCC  
PECL Low, VEE or NC  
PECL High or VCC  
DIVIDE TRUTH TABLE  
EN-SEL  
NC  
NC  
VEE  
VEE  
20kΩ to VEE  
20kΩ to VEE  
Q
Low  
Q¯  
DIV-SEL  
DIVIDE  
RATIO  
÷1  
High  
Data  
High  
Data  
Data  
High  
NC  
Low  
1
VEE  
÷2  
Data  
Data  
Low  
1
DIV-SEL connection must  
be ≤1Ω.  
D
EN (EN-SEL CONNECTED TO  
(PECL)  
V
EE VIA 20k RESISTOR)  
EN (EN-SEL OPEN OR  
(CMOS)  
CONNECTED TO VEE  
)
(DIV-SEL  
OPEN)  
Q
(DIV-SEL  
CONNECTED  
Q
TO VEE  
)
TIMING DIAGRAM  
June 2009 REV - 9  
www.azmicrotek.com  
2
AZP92  
AZP92NA  
MLP 8, 2x2 mm  
TOP VIEW  
June 2009 REV - 9  
www.azmicrotek.com  
3
AZP92  
Absolute Maximum Ratings are those values beyond which device life may be impaired.  
Symbol  
Characteristic  
Rating  
Unit  
VCC  
VI  
VEE  
VI  
PECL Power Supply  
(VEE = 0V)  
(VEE = 0V)  
(VCC = 0V)  
(VCC = 0V)  
— Continuous  
— Surge  
0 to +6.0  
0 to +6.0  
-6.0 to 0  
-6.0 to 0  
50  
Vdc  
Vdc  
Vdc  
Vdc  
PECL Input Voltage  
ECL Power Supply  
ECL Input Voltage  
Output Current  
IHGOUT  
mA  
100  
TA  
TSTG  
Operating Temperature Range  
Storage Temperature Range  
-40 to +85  
-65 to +150  
°C  
°C  
100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND)  
-40°C  
0°C  
25°C  
85°C  
Symbol  
Characteristic  
Unit  
Min  
-1085  
-1900  
Max  
-880  
-1555  
Min  
-1025  
-1900  
Max  
-880  
-1620  
Min  
-1025  
-1900  
Max  
-880  
-1620  
Min  
-1025  
-1900  
Max  
-880  
-1620  
VOH  
VOL  
Output HIGH Voltage1  
Output LOW Voltage1  
Input HIGH Voltage  
D/D¯, EN (ECL)2  
mV  
mV  
VIH  
VIL  
-1165  
-390  
VCC  
-1165  
-390  
VCC  
-1165  
-390  
VCC  
-1165  
-390  
VCC  
mV  
mV  
EN (CMOS)3 VEE+2000  
VEE+2000  
VEE+2000  
VEE+2000  
Input LOW Voltage  
D/D¯, EN (ECL)2  
EN (CMOS)3  
Reference Voltage  
-2250  
VEE  
-1390  
-1475  
VEE + 800  
-1250  
-2250  
VEE  
-1390  
-1475  
VEE + 800  
-1250  
-2250  
VEE  
-1390  
-1475  
VEE + 800  
-1250  
-2250  
VEE  
-1390  
-1475  
VEE + 800  
-1250  
VBB  
IIH  
mV  
μA  
Input HIGH Current EN  
150  
150  
150  
150  
Input LOW Current  
EN (ECL)2  
IIL  
0.5  
-150  
0.5  
-150  
0.5  
-150  
0.5  
-150  
μA  
EN (CMOS)3  
IEE  
Power Supply Current4  
31  
31  
31  
34  
mA  
1.  
2.  
3.  
4.  
Specified with outputs terminated through 50Ω resistors to VCC - 2V.  
EN-SEL connected to VEE through a 20kΩ resistor.  
EN-SEL connected VEE or left open (NC).  
DIV-SEL left open (NC).  
100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V)  
-40°C  
0°C  
25°C  
85°C  
Symbol  
Characteristic  
Unit  
Min  
2215  
1400  
Max  
2420  
1745  
Min  
2275  
1400  
Max  
2420  
1680  
Min  
2275  
1400  
Max  
2420  
1680  
Min  
2275  
1400  
Max  
2420  
1680  
VOH  
VOL  
Output HIGH Voltage1,2  
Output LOW Voltage1,2  
Input HIGH Voltage1  
D/D¯, EN (PECL)3  
EN (CMOS)4  
mV  
mV  
VIH  
VIL  
2135  
2000  
2910  
VCC  
2135  
2000  
2910  
VCC  
2135  
2000  
2910  
VCC  
2135  
2000  
2910  
VCC  
mV  
mV  
Input LOW Voltage1  
D/D¯, EN (PECL)3  
EN (CMOS)4  
1050  
GND  
1910  
1825  
800  
2050  
150  
1050  
GND  
1910  
1825  
800  
2050  
150  
1050  
GND  
1910  
1825  
800  
2050  
150  
1050  
GND  
1910  
1825  
800  
2050  
150  
VBB  
IIH  
Reference Voltage1  
Input HIGH Current EN  
mV  
μA  
Input LOW Current  
EN (PECL)3  
IIL  
0.5  
-150  
0.5  
-150  
0.5  
-150  
0.5  
-150  
μA  
EN (CMOS)4  
IEE  
Power Supply Current5  
31  
31  
31  
34  
mA  
1.  
2.  
3.  
4.  
5.  
For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value.  
Specified with outputs terminated through 50Ω resistors to VCC - 2V.  
EN-SEL connected to VEE through a 20kΩ resistor.  
EN-SEL connected VEE or left open (NC).  
DIV-SEL left open (NC).  
June 2009 REV - 9  
www.azmicrotek.com  
4
AZP92  
100K PECL DC Characteristics (VEE = GND, VCC = +5.0V)  
-40°C  
0°C  
25°C  
85°C  
Symbol  
Characteristic  
Unit  
Min  
3915  
3100  
Max  
4120  
3445  
Min  
3975  
3100  
Max  
4120  
3380  
Min  
3975  
3100  
Max  
4120  
3380  
Min  
3975  
3100  
Max  
4120  
3380  
VOH  
VOL  
Output HIGH Voltage1,2  
Output LOW Voltage1,2  
Input HIGH Voltage1  
D/D¯, EN (PECL)3  
EN (CMOS)4  
mV  
mV  
VIH  
VIL  
3835  
2000  
4610  
VCC  
3835  
2000  
4610  
VCC  
3835  
2000  
4610  
VCC  
3835  
2000  
4610  
VCC  
mV  
mV  
Input LOW Voltage1  
D/D¯, EN (PECL)3  
EN (CMOS)4  
2750  
GND  
3610  
3525  
800  
3750  
150  
2750  
GND  
3610  
3525  
800  
3750  
150  
2750  
GND  
3610  
3525  
800  
3750  
150  
2750  
GND  
3610  
3525  
800  
3750  
150  
VBB  
IIH  
Reference Voltage1  
Input HIGH Current EN  
mV  
μA  
Input LOW Current  
EN (PECL)3  
IIL  
0.5  
-150  
0.5  
-150  
0.5  
-150  
0.5  
-150  
μA  
EN (CMOS)4  
IEE  
Power Supply Current5  
31  
31  
31  
34  
mA  
1.  
2.  
3.  
4.  
5.  
For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.  
Specified with outputs terminated through 50Ω resistors to VCC - 2V.  
EN-SEL connected to VEE through a 20kΩ resistor.  
EN-SEL connected VEE or left open (NC).  
DIV-SEL left open (NC).  
AC Characteristics (VEE = -3.0V to -5.5V; VCC = GND or VEE = GND; VCC = +3.0V to +5.5V)  
-40°C  
Typ  
0°C  
Typ  
25°C  
Typ  
85°C  
Typ  
Symbol  
Characteristic  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Propagation Delay  
D to Q/Q¯ Outputs1  
EN to Q/Q¯ Outputs1  
Duty Cycle Skew2  
Input Swing3  
tPLH / tPHL  
tSKEW  
(SE)  
(SE)  
450  
600  
20  
450  
600  
20  
450  
600  
20  
450  
600  
20  
ps  
ps  
5
5
5
5
VPP (AC)  
Differential (D/D¯)  
Single Ended (D)4  
Output Rise/Fall1  
(20% - 80%)  
150  
300  
1000  
2000  
150  
300  
1000  
2000  
150  
300  
1000  
2000  
150  
300  
1000  
2000  
mV  
tr / tf  
80  
200  
80  
200  
80  
200  
80  
200  
ps  
1.  
2.  
3.  
4.  
Specified with outputs terminated through 50Ω resistors to VCC - 2V.  
Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.  
The peak-to-peak input swing is the range for which AC parameters are guaranteed.  
Range valid for AC coupled signals only.  
AC PP INPUT (Differential)  
D
D
VPP (AC)  
June 2009 REV - 9  
www.azmicrotek.com  
5
AZP92  
Typical Large Signal Outputs, Q/Q¯  
1000  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
0
500  
1000  
1500  
2000  
2500  
3000  
3500  
4000  
FREQUENCY (MHz)  
Measured with 750mv D input, Q/Q¯ each terminated to VCC-2V via 50 Ω resistors.  
June 2009 REV - 9  
www.azmicrotek.com  
6
AZP92  
PACKAGE DIAGRAM  
MLP 8 2x2mm  
Pin 1 Dot  
By Marking  
2.000±0.050  
MLP 8  
(2x2mm)  
2.000±0.050  
TOP VIEW  
Pin 1 Identification  
R0.100 TYP  
0.350±0.050  
0.250±0.050  
8
7
6
5
1
2
3
4
1.200±0.050 1.750  
exp. pad Ref.  
0.500 bsc  
0.600±0.050  
exp. pad  
BOTTOM VIEW  
1
2
3
4
0.750±0.050  
0.000-0.050  
0.203±0.025  
SIDE VIEW  
Note: All dimensions are in mm  
June 2009 REV - 9  
www.azmicrotek.com  
7
AZP92  
TAPE & REEL PACKAGING  
MLP 8 2x2mm  
Direction of Travel  
Carrier Tape Width  
Package  
Suffix Reel Diameter Quantity  
Carrier Tape Pitch  
MLP 8 (2x2mm)  
R1  
R2  
7”  
13”  
1000  
2500  
8mm  
8mm  
4mm  
4mm  
June 2009 REV - 9  
www.azmicrotek.com  
8
AZP92  
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc.  
makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona  
Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all  
liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license  
rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems  
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a  
situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such  
unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries,  
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly  
or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that  
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.  
June 2009 REV - 9  
www.azmicrotek.com  
9
厂商 型号 描述 页数 下载

AZM

 		AZP51 低相位噪声的正弦波LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave to LVPECL Buffer/Divider ] 9 页

AZM

 		AZP51SG 低相位噪声的正弦波LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave to LVPECL Buffer/Divider ] 9 页

AZM

 		AZP51_12 低相位噪声正弦波/ CMOS到LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider ] 9 页

AZM

 		AZP52 低相位噪声的正弦波LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave to LVPECL Buffer/Divider ] 9 页

AZM

 		AZP52SG 低相位噪声的正弦波LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave to LVPECL Buffer/Divider ] 9 页

AZM

 		AZP52_13 低相位噪声正弦波/ CMOS到LVPECL缓冲器/转换器[ Low Phase Noise Sine Wave / CMOS to LVPECL Buffer / Translator ] 9 页

AZM

 		AZP53 低相位噪声的正弦波LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave to LVPECL Buffer/Divider ] 9 页

AZM

 		AZP53PG 低相位噪声的正弦波LVPECL缓冲器/分频器[ Low Phase Noise Sine Wave to LVPECL Buffer/Divider ] 9 页

AZM

 		AZP53QG 低相位噪声正弦波/ CMOS[ Low Phase Noise Sine Wave/CMOS ] 13 页

AZM

 		AZP53_13 低相位噪声正弦波/ CMOS到LVPECL缓冲器/转换器[ Low Phase Noise Sine Wave / CMOS to LVPECL Buffer / Translator ] 13 页

购物指南

支付方式

配送服务

售后服务

发票须知

优惠券使用规则

特色服务

PCBA制造

国产品牌推荐

国产料号替代

质量保证

技术资料

行业资讯

关于我们

关于达普

联系我们

联系我们

服务热线：400-618-9990

企业邮箱：smail@ic72.com

服务时间：周一至周六 8:30-17:30

达普官方微信号

PDF索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

IC型号索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

Copyright 2024 gkzhan.com Al Rights Reserved 京ICP备06008810号-21 京

深圳网络警察报警平台
公共信息安全网络监察
经营性网站备案信息
不良信息举报中心
工商网监电子标识
全国公安机关备案
0.201208s