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IZ4053B

型号：

IZ4053B

描述：

模拟多路复用器多路解复用器[ Analog Multiplexer Demultiplexer ]

品牌：

ETC[ ETC ]

页数：

8 页

PDF大小：

72 K

下载PDF手册
TECHNICAL DATA  
IW4053B  
Analog Multiplexer Demultiplexer  
High-Performance Silicon-Gate CMOS  
The IW4053B analog multiplexer/demultiplexer is digitally  
controlled analog switches having low ON impedance and very low  
OFF leakage current. Control of analog signals up to 20V peak-to-peak  
can be achieved by digital signal amplitudes of 4.5 to 20V (if VCC - GND  
= 3V, a V - VEE of up to 13 V can be controlled; for VCC - VEE level  
CC  
differences above 13V a VCC - GND of at least 4.5V is required).  
These multiplexer circuits dissipate extremely low quiescent power  
over the full VCC -GND and VCC - VEE supply-voltage ranges,  
independent of the logic state of the control signals. When a logic  
“1”is present at the ENABLE input terminal all channels are off.  
The IW4053B is a triple 2-channel multiplexer having three separate  
digital control inputs, A, B, and C, and an enable input. Each control  
input selects one of a pair of channels which are connected in a single-  
pole double-throw configuration.  
ORDERING INFORMATION  
IW4053BN  
IW4053BD  
IZ4053B  
Plastic DIP  
SOIC  
chip  
TA = -55° to 125° C for all packages  
·
·
Operating Voltage Range: 3.0 to 18 V  
Maximum input current of 1 mA at 18 V over full package-temperature  
range; 100 nA at 18 V and 25°C  
PIN ASSIGNMENT  
·
Noise margin (over full package temperature range):  
1.0 V min @ 5.0 V supply  
2.0 V min @ 10.0 V supply  
2.5 V min @ 15.0 V supply  
LOGIC DIAGRAM  
Triple Single-Pole, Double-Position  
Plus Common Off  
FUNCTION TABLE  
Control Inputs  
ON  
Enable  
Select  
B
Channels  
C
L
A
L
L
L
L
L
L
L
L
L
H
L
Z0  
Z0  
Z0  
Z0  
Z1  
Z1  
Z1  
Z1  
Y0  
Y0  
X0  
X1  
X0  
X1  
X0  
X1  
X0  
X1  
L
L
H
L
L
H
Y1  
L
H
H
L
Y1  
H
H
H
H
X
L
Y0  
L
H
L
Y0  
H
Y1  
H
H
X
Y1  
PIN 16 =VCC  
PIN 7 = VEE  
PIN 8 = GND  
X
None  
H = high level  
L = low level  
X = don’t care  
INTEGRAL  
1
IW4053B  
MAXIMUM RATINGS*  
Symbol  
Parameter  
Value  
-0.5 to +20  
-0.5 to VCC +0.5  
±10  
Unit  
V
VCC  
DC Supply Voltage (Referenced to GND)  
DC Input Voltage (Referenced to GND)  
DC Input Current, per Pin  
V
IN  
V
IIN  
PD  
mA  
mW  
mW  
°C  
Power Dissipation in Still Air  
500*1  
Ptot  
Power Dissipation per Output Transistor  
Storage Temperature  
100  
Tstg  
TL  
-65 to +150  
260  
Lead Temperature, 1 mm from Case for 10 Seconds  
(Plastic DIP or SO Package)  
°C  
*Maximum Ratings are those values beyond which damage to the device may occur.  
Functional operation should be restricted to the Recommended Operating Conditions.  
*1 - for Plastic DIP from -55° to +100°C, for SO Package from -55° to +65°C.  
+Derating - Plastic DIP: - 12 mW/°C from 100° to 125°C  
SO Package: - 7 mW/°C from 65° to 125°C  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
DC Supply Voltage (Referenced to GND)  
DC Input Voltage (Referenced to GND)  
Operating Temperature, All Package Types  
Min  
3.0  
0
Max  
18  
Unit  
V
VCC  
V
IN  
VCC  
V
TA  
-55  
+125  
°C  
This device contains protection circuitry to guard against damage due to high static voltages or electric  
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages  
to this high-impedance circuit. For proper operation, V and VOUT should be constrained to the range GND£(V or  
IN  
IN  
VOUT)£VCC.  
Unused digital pins must be tied to an appropriate logic voltage level (e.g., either GND or V ). Unused  
CC  
Analog I/O pins may be left open or terminated.  
INTEGRAL  
2
IW4053B  
DC ELECTRICAL CHARACTERISTICS Digital Section  
VCC  
V
Guaranteed Limit  
Symbol  
Parameter  
Test Conditions  
V =VCC thru 1kW  
-55  
°C  
£ 25  
°C  
£ 125 Unit  
°C  
V
IH  
Minimum High-Level  
Input Voltage, Channel- VEE=GND=0  
Select or Enable Inputs  
5
10  
15  
3.5  
7
3.5  
7
3.5  
7
V
IS  
IIS<2mA on all OFF Chanels  
11  
11  
11  
RL=1kW to GND  
V
IL  
Maximum Low -Level  
V =VCC thru 1kW  
5
10  
15  
1.5  
3
4
1.5  
3
4
1.5  
3
4
V
IS  
Input Voltage, Channel- VEE=GND=0  
Select or Enable Inputs IIS<2mA on all OFF Chanels  
RL=1kW to GND  
IIN  
Maximum Input  
Leakage Current,  
Channel-Select or  
Enable Inputs  
V =VCC or GND  
VEE=GND=0  
18  
±0.1  
±0.1  
±1.0  
mA  
mA  
IN  
ICC  
Maximum Quiescent  
Supply Current (per  
Package)  
Channel Select = VCC or GND  
VEE=GND=0  
5
5
10  
20  
100  
5
10  
20  
100  
150  
300  
600  
10  
15  
20  
3000  
DC ELECTRICAL CHARACTERISTICS Analog Section  
VCC  
Guaranteed Limit  
Symbol  
Parameter  
Test Conditions  
V
-55  
°C  
£ 25  
°C  
£ 125 Unit  
°C  
RON  
Maximum “ON” Resistance  
VEE=GND=0  
V = GND to VCC  
IS  
5
10  
15  
800  
310  
200  
1050  
400  
240  
1150  
550  
320  
W
DRON  
Maximum Difference in “ON” VEE=GND=0  
Resistance Between Any  
Two Channels in the Same  
Package  
5
10  
15  
-
-
-
10*  
15*  
5*  
-
-
-
W
IOFF  
Maximum Off- Channel  
Leakage Current, Any One  
Channel  
VEE=GND=0  
18  
18  
±100  
±100  
±100  
±100  
±1000  
±1000  
nA  
Maximum Off- Channel  
Leakage Current, Common  
Channel  
VEE=GND=0  
* - Typical Value  
INTEGRAL  
3
IW4053B  
INTEGRAL  
4
IW4053B  
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=20.0 ns)  
VCC  
V
Guaranteed Limit  
Symbol  
Parameter  
-55  
°C  
£ 25  
°C  
£ 125  
°C  
Unit  
tPHL(tPLH)  
Maximum Propagation Delay , Analog Input to  
Analog Output (Figure 1)  
RL=200kW, VEE=GND=0  
5
10  
15  
60  
30  
20  
60  
30  
20  
70  
40  
30  
ns  
tPHL1( PLH1)  
t
Maximum Propagation Delay , Channel-Select  
Input to Analog Output (Figure 1)  
RL=200 kW, VEE=GND=0  
5
10  
15  
350  
200  
160  
350  
200  
160  
400  
250  
200  
ns  
ns  
tPZL1(tPZH1) Maximum Propagation Delay , Channel-Select  
Input to Analog Output  
5
10  
15  
720  
320  
240  
720  
320  
240  
720  
320  
240  
(Figure 2) RL=10 kW  
VEE=GND=0  
VEE=-5Â, GND=0  
5
450  
450  
450  
tPZL2( PZH2)  
t
Maximum Propagation Delay , Enable to Analog  
Output  
(Figure 2) RL=10 kW  
VEE=GND=0  
5
10  
15  
720  
320  
240  
720  
320  
240  
720  
320  
240  
ns  
ns  
ns  
VEE=-10Â, GND=0  
5
400  
400  
400  
tPLZ1( PHZ1)  
t
Maximum Propagation Delay , Channel-Select  
Input to Analog Output  
(Figure 2) RL=10 kW  
5
10  
15  
720  
320  
240  
720  
320  
240  
720  
320  
240  
VEE=GND=0  
VEE=-5Â, GND=0  
5
450  
450  
450  
tPLZ2( PHZ2)  
t
Maximum Propagation Delay , Enable to Analog  
Output  
(Figure 2) RL=1,0 kW  
VEE=GND=0  
5
10  
15  
450  
210  
160  
450  
210  
160  
450  
210  
160  
VEE=-10Â, GND=0  
5
-
300  
-
300  
7.5  
600  
-
CIN  
Maximum Input Capacitance, Channel-Select or  
Enable Inputs  
pF  
pF  
CI/O  
Maximum Capacitance  
VEE=GND=-5V  
5
-
5*  
-
CIS  
COS  
5
5
-
-
9*  
-
-
Feedthrough CIOS  
0.2*  
INTEGRAL  
5
IW4053B  
ADDITIONAL APPLICATION CHARACTERISTICS  
**  
VCC  
V
VIS  
Limits  
Symbol  
Parameter  
Test Conditions  
Unit  
Typical Value  
V
25 °C  
BW  
Maximum On-  
Channel  
VEE=GND=0  
RL=1kW  
Bandwidth or  
Minimum  
Frequency  
20 log(VOS/V )=-3db  
IS  
VOS at Common OUT/IN  
10  
10  
2,5  
2,5  
30  
60  
MHz  
Response (-3db)  
VOS at Any Channel  
f1  
(-40db)  
VEE=GND=0  
RL=1kW  
20 log(VOS/V )=-40db  
Feedthrough  
Frequency (All  
Channels OFF)  
IS  
VOS at Common OUT/IN  
10  
10  
2,5  
2,5  
8
8
MHz  
VOS at Any Channel  
f2  
(-40db)  
VEE=GND=0  
Signal Crosstalk RL=1kW  
Frequency  
20 log(VOS/V )=-40db  
IS  
Between any 2 Sections :  
In Pin 2, Out Pin 14  
10  
10  
2,5  
2,5  
2.5  
6
MHz  
%
In Pin 15, Out Pin 14  
THD  
VAO/I  
Total Harmonic  
Distortion  
VEE=GND=0  
fIS=1kHz sine wave  
5
10  
15  
1
1,5  
2,5  
0.3  
0.2  
0.12  
Address-or  
VEE=GND=0, RL=10kW***  
10  
-
65  
mV  
Enable to Signal tr,tf=20ns  
Crosstalk Square Wave  
(Peak)  
** Peak-to-peak voltage symmetrical about (VCC-VEE)/2.  
*** Both ends of channel.  
INTEGRAL  
6
IW4053B  
VCC  
50%  
INPUT  
GND  
tPLH  
tPHL  
VCC  
90%  
50%  
10%  
ANALOG OUT  
GND  
tTLH  
tTHL  
Figure 1. Switching Waveforms  
tr  
tf  
VCC  
ENABLE  
90%  
50%  
50%  
CHANNEL-SELECT  
INPUT  
10%  
GND  
tPLZ  
tPZL  
VCC  
VOL  
90%  
10%  
10%  
ANALOG  
OUT  
VOH  
90%  
GND  
tPHZ  
tPZH  
Figure 2. Switching Waveforms  
EXPANDED LOGIC DIAGRAM  
IN / OUT  
Ucc  
16  
3
5
1
2
13 12  
TG  
TG  
TG  
BINARY 1 OF 2  
DECODERS  
WITH ENABLE  
14  
LOGIC LEVEL  
CONVERSION  
11  
A
OUT/IN  
15  
10  
9
B
TG  
TG  
TG  
OUT/IN  
C
4
OUT/IN  
6
ENABLE  
8
7
GND  
VEE  
INTEGRAL  
7
IW4053B  
CHIP PAD DIAGRAM  
Chip marking  
204053  
1.95 + 0.03  
12  
11  
10  
14  
13  
15  
16  
09  
08  
01  
03  
07  
06  
05  
04  
02  
(0,0)  
Location of marking (mm): left lower corner x=1.361, y=1.592; right higher corner x=1.423, y=1.652.  
Chip thickness: 0.46±0.02mm  
PAD LOCATION  
Location (left lower corner), mm  
Pad No  
Pin No  
Pad size, mm  
X
Y
0.116  
0.116  
0.362  
0.669  
1.074  
1.287  
1.699  
1.699  
1.699  
1.700  
1.640  
1.063  
0.756  
0.429  
0.116  
0.116  
0.453  
0.175  
0.116  
0.116  
0.116  
0.115  
0.290  
0.620  
0.973  
1.268  
1.583  
1.583  
1.583  
1.583  
1.445  
0.942  
0.100 x 0.100  
0.100 x 0.100  
0.100 x 0.100  
0.100 x 0.100  
0.100 x 0.100  
0.100 x 0.100  
0.100 x 0.100  
0.100 x 0.100  
0.100 x 0.100  
0.100 x 0.100  
0.100 x 0.100  
0.100 x 0.100  
0.100 x 0.100  
0.100 x 0.100  
0.100 x 0.100  
0.100 x 0.100  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
16  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
16  
Note: Pad location is given as per passivation layer  
INTEGRAL  
8
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