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LUPA-4000

4M Pixel CMOS Image Sensor

(SPI) interface. It is housed in a 127-pin ceramic PGA

package.

This data sheet allows the user to develop a camera-system

based on the described timing and interfacing.

Main features

The main features of the image sensor are identified as:

• 2048 x 2048 active pixels (4M pixel resolution)

• 12 µm²square pixels (based on the high-fill factor active

pixel sensor technology of FillFactory (US patent No.

6,225,670 and others))

• Peak QE x FF of 37.50%

• Optical format: 24,6 mm x 24,6 mm

• Pixel rate of 66 MHz using a 33 MHz system clock

• Optical dynamic range: 66 dB (2000:1) in single slope

operation and up to 90 dB in multiple slope operation

• 2 On-chip 10 bit, 33 MSamples/s ADC

• Full snapshot shutter

• Random programmable windowing and sub-sampling

modes

• 127-pin PGA package

• Binning (Voltage averaging in X-direction)

• Programmable read out direction (X and Y)

Preamble

Overview

Part Number and ordering information

This document describes the interfacing and the driving of the

LUPA-4000 image sensor. This 4 mega-pixel CMOS active

pixel sensor features synchronous shutter and a maximal

frame-rate of 15 fps in full resolution. The readout speed can

be boosted by means of sub sampling and windowed Region

Of Interest (ROI) readout. High dynamic range scenes can be

captured using the double and multiple slope functionality.

Mono-

Name

Package

chrome/color

CYIL1SM4000AA-GDC 127 pinceramic Monochrome

PGA

The LUPA-4000 is also available in color or monochrome

without the cover glass. Please contact Cypress for more

information.

The sensor can be used with one or two outputs. Two on chip

10-bit ADC's can be used to convert the analog data to a 10-bit

digital word stream. The sensor uses a 3-wire Serial-Parallel

Cypress Semiconductor Corporation

Document Number: 38-05712 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised Januari 4, 2007

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TABLE OF CONTENTS

Preamble ........................................................................................................................................................... 1

Overview ...................................................................................................................................................... 1

Main features ............................................................................................................................................... 1

Part Number and ordering information.......................................................................................................... 1

Specifications ................................................................................................................................................... 4

General specifications .................................................................................................................................. 4

Electro-optical specifications ........................................................................................................................ 4

Features and general specifications ............................................................................................................ 6

Electrical specifications ................................................................................................................................ 7

Sensor architecture .......................................................................................................................................... 8

The 6-T pixel ................................................................................................................................................ 8

Frame rate and windowing ........................................................................................................................... 9

Output amplifier ............................................................................................................................................ 9

Pixel array drivers ........................................................................................................................................ 10

Column amplifiers ........................................................................................................................................ 10

Analog to Digital Converter .......................................................................................................................... 10

Synchronous shutter .................................................................................................................................... 11

Non-destructive readout (NDR) ................................................................................................................... 12

Operation and signalling .............................................................................................................................. 12

Pixel array signals ........................................................................................................................................ 14

Timing and read out of the image sensor ...................................................................................................... 16

Timing of the pixel array ............................................................................................................................... 16

Read out of the image sensor ...................................................................................................................... 18

Serial-Parallel-Interface (SPI) ...................................................................................................................... 24

Pin list ................................................................................................................................................................ 25

Geometry and mechanical specifications ...................................................................................................... 29

Bare die ........................................................................................................................................................ 29

Package drawing ......................................................................................................................................... 30

Bonding pads ............................................................................................................................................... 32

Bonding diagram .......................................................................................................................................... 33

Glass transmittance ..................................................................................................................................... 34

Handling and soldering precautions .............................................................................................................. 35

Ordering Information .................................................................................................................................... 35

Disclaimer .................................................................................................................................................... 35

APPENDIX A: LUPA-4000 evaluation system ................................................................................................ 36

APPENDIX B: Frequently Asked Questions ................................................................................................... 37

Document History Page ................................................................................................................................... 38

LIST OF FIGURES

Spectral response curve ..................................................................................................................................... 5

Photo-voltaic response curve ............................................................................................................................. 6

Block diagram of the image sensor .................................................................................................................... 8

6T-pixel architecture ........................................................................................................................................... 8

Output stage architecture ................................................................................................................................... 9

ADC timing ......................................................................................................................................................... 10

In- and external ADC connections ...................................................................................................................... 11

Document Number: 38-05712 Rev. *B

Page 2 of 38

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Synchronous shutter operation ........................................................................................................................... 11

Principle of non-destructive readout. .................................................................................................................. 12

Internal timing of the pixel................................................................................................................................... 14

Integration and read out in parallel ..................................................................................................................... 16

Integration and readout sequentially .................................................................................................................. 16

Timing of the pixel array ...................................................................................................................................... 17

Readout of the image sensor. F.O.T ................................................................................................................... 18

X- and Y-addressing ........................................................................................................................................... 19

X-addressing. From bottom to top....................................................................................................................... 20

Output signal related to Clock_x signal ............................................................................................................... 21

Standard timing for the R.O.T. Only pre_col and Norowsel control signals are required.................................... 22

Reduced standard ROT by means of Sh_col signal............................................................................................ 22

X- and Y-addressing with precharging of the buses ........................................................................................... 23

SPI block diagram and timing ............................................................................................................................. 24

Die figure of the LUPA-4000 ............................................................................................................................... 29

Package drawing of the LUPA-4000 package .................................................................................................... 30

LUPA-4000 package specifications with die ....................................................................................................... 31

Placing of the bonding pads on the LUPA-4000 package .................................................................................. 32

Bonding pads diagram of the LUPA-4000 package ........................................................................................... 33

Transmission characteristics of the D263 glass used as protective cover for the LUPA-4000 sensors. ............ 34

Content of the LUPA-4000 evaluation kit ........................................................................................................... 36

Dual slope diagram ............................................................................................................................................. 37

LIST OF TABLES

General specifications ........................................................................................................................................ 4

Electro-optical specifications .............................................................................................................................. 4

Features and general specifications ................................................................................................................... 6

Recommended operation conditions .................................................................................................................. 7

Frame rate as function of ROI read out and/or sub sampling ............................................................................. 9

ADC specifications ............................................................................................................................................. 10

Advantages and disadvantages of non-destructive readout. .............................................................................. 12

Power supplies ................................................................................................................................................... 12

Overview of the power supplies related to the pixel signals ............................................................................... 13

Overview of bias signals ..................................................................................................................................... 13

Overview of the in- and external pixel array signals ........................................................................................... 15

Timing specifications .......................................................................................................................................... 17

Read-out timing specifications ............................................................................................................................ 19

Read-out timing specifications with precharching of the buses .......................................................................... 23

SPI parameters ................................................................................................................................................... 24

Document Number: 38-05712 Rev. *B

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Specifications

General specifications

Table 1. General specifications

Parameter

Pixel architecture

Pixel size

Specification

Remarks

6T-pixel

Based on the high fill-factor active pixel sensor technology of FillFactory

12 µm x 12 µm

2048 x 2048

The resolution and pixel size results in a 24,6 mm x 24,6 mm optical

active area.

Resolution

Pixel rate

66 MHz

Using a 33 MHz system clock and 1 or 2 parallel outputs.

Full snapshot shutter (integration during read out is possible).

Frame rate increase possible with ROI read out and/or sub sampling.

Shutter type

Full frame rate

Pipelined snapshot shutter

15 frames/second

Electro-optical specifications

Overview

Table 2. Electro-optical specifications

Parameter

Specification

Remarks

of max. output swing

FPN

<1.25% RMS

<2.5% RMS

PRNU

at 25% and 75% (% of the signal)

@ output (measured).

Conversion gain

Output signal amplitude

13.5 uV/electron

1V

Converted by 2 on-chip 10-bit ADC's in 2x10 parallel digital

outputs. Or to be used with external ADC's

Saturation charge

Sensitivity

80.000 e-

2090 V.m2/W.s

11.61 V/lux.s

Average white light.

Visible band only (180 lx = 1 W/m2).

Peak QE * FF

Peak SR * FF

37.5%

0.19 A/W

Average QE*FF = 35%.

Average SR*FF = 0.15 A/W.

See spectral response curve.

Dark current (@ 21 °C)

<140 mV/s

or 10000 e-/s

Noise electrons

S/N ratio

< 40 e-

2000:1

66 dB.

Spectral sensitivity range

Parasitic sensitivity

400 - 1000 nm

< 1/5000

I.e. sensitivity of the storage node during read out (after

integration).

MTF

64%

Power dissipation

<200 mWatt

Typical (without ADC's).

Document Number: 38-05712 Rev. *B

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Spectral response curve

Figure 1. Spectral response curve

QE 40%

QE 30%

QE 25%

0.20

0.18

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

QE 20%

QE 10%

0.00

400

500

600

700

800

900

1000

Wavelength [nm]

Figure 1 shows the spectral response characteristic. The

curve is measured directly on the pixels. It includes effects of

non-sensitive areas in the pixel, e.g. interconnection lines. The

sensor is light sensitive between 400 and 1000 nm. The peak

QE * FF is 37.5% approximately between 500 and 700 nm. In

view of a fill factor of 60%, the QE is thus larger than 60%

between 500 and 700 nm.

Document Number: 38-05712 Rev. *B

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Photo-voltaic response curve

Figure 2. Photo-voltaic response curve

1.2

1

0.8

0.6

0.4

0.2

0

20000

40000

60000

80000

# electrons

100000

120000

140000

Figure 2 shows the pixel response curve in linear response

mode. This curve is the relation between the electrons

detected in the pixel and the output signal. The resulting

voltage-electron curve is independent of any parameters. The

voltage to electrons conversion gain is 13.5 µV/electron.

Note that the upper part of the curve (near saturation) is

actually a logarithmic response.

Features and general specifications

Table 3. Features and general specifications

Feature

Specification/Description

Electronic shutter type

Windowing (ROI)

Sub-sampling and binning modes

Read out direction

Extended dynamic range

Analog output

Full snapshot shutter (integration during read out is possible).

Randomly programmable ROI read out.

2:1 subsampling and voltage averaging is possible (only in the X-direction).

Read out direction can be reversed in X and Y.

Multiple slope (up to 90 dB optical dynamic range).

The output rate of 66 Mpixels/s can be achieved with either 1 or 2 analog outputs.

2 on-chip 10-bit ADC's @ 33 Msamples/s.

Nominal 2.5V (some supplies require 3.3V).

3.3V.

Digital output

Supply voltage VDD

Logic levels

Operational temperature range

Interface

0°C to 60°C; with degradation of dark current.

Serial-to Parallel Interface (SPI).

Package

127 pin PGA package

Power dissipation

Mass

<200 mW

<100g

Document Number: 38-05712 Rev. *B

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Table 3. Features and general specifications (continued)

Feature

Specification/Description

Output amplifiers

Differential

External output load

R > 10 kΩ

C < 20 pF (<10 pF is advised)

Number of outputs

1 at 66 Mpixels/sec

2 at 33 Mpixels/sec

Electrical specifications

or output. ± 50 mA

T_LLead temperature (5 seconds soldering). 350 °C

Absolute maximum ratings

• Absolute Ratings are those values beyond which damage

to the device may occur.

VDD DC supply voltage -0.5 to 4.5 V

V_INDC input voltage -0.5 to 3.8 V

• VDD = VDDD = VDDA (VDDD is supply to digital circuit,

VDDA to analog circuit).

V_OUTDC output voltage -0.5 to 3.8 V

I_IODC current drain per pin; any single input

Recommended operating conditions

Table 4. Recommended operation conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V

Vaa

Va3

Vdd

Voo

Vres

Power supply column read out module

Power supply digital modules

2.5

3.3

2.5

3.5

2.5

3.3

2.6

0

3.3

V

Power supply output stages

V

Power supply reset drivers

2.5

2.0

2.5

2.0

3.8

3.3

3.5

3.0

3.3

0

V

Vres_ds

Vmem_h

Vmem_l

Vpix

Power supply multiple slope reset driver

Power supply memory element (high level)

Power supply memory element (low level)

Power supply pixel array

V

Vpre_l

T_A

Power supply for Precharge off-state

Commercial operating temperature.

–0.4

0

V

30

60

°C

Notes

1. All parameters are characterized for DC conditions after thermal equilibrium has been established.

2. Unused inputs must always be tied to an appropriate logic level, e.g. either VDD or GND.

3. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however it is recommended that normal precautions

be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit.

Document Number: 38-05712 Rev. *B

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Sensor architecture

A schematic drawing of the architecture is given in the block

diagram below. The image core consists of a pixel array, one

X- and two Y-addressing registers (only one drawn), pixel

array drivers and column amplifiers. The image sensor of 2048

* 2048 pixels is read out in progressive scan. One or two output

amplifiers read out the image sensor. The output amplifiers are

working at 66 MHz pixel rate nominal speed or each at 33 MHz

pixel rate in case the 2 output amplifiers are used to read out

the imager. The complete image sensor has been designed for

operation up to 66 MHz.

The structure allows having a programmable addressing in the

x-direction in steps of 2 and in the y-direction in steps of 2 (only

even start addresses in X- and Y-direction are possible). The

starting point of the address is uploadable by means of the

Serial-Parallel Interface (SPI)

Figure 3. Block diagram of the image sensor

eos_y

On chip drivers

Reset, mem_hl,

precharge, sample

pixel array

2048 * 2048

Column ampliﬁers

X shift register

sync_y

Clk_y

eos_x

Clk_x

sync_x

2 differential

outputs

DAC

SPI

Logic blocks

The 6-T pixel

To obtain the global shutter feature combined with a high

sensitivity and good Parasitic Light Sensitivity (PLS), the pixel

architecture given in the figure below is implemented.

Figure 4. 6T-pixel architecture

Vpix

Vmem

Row-Select

Sample

Reset

Document Number: 38-05712 Rev. *B

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This pixel architecture is designed in a 12 * 12 µm²pixel pitch.

The pixel is designed to meet the specifications as described

in Table 1, Table 2, and Table 3.

Frame rate and windowing

Frame rate

To obtain a frame rate a 15 frames/sec, one needs 1 output amplifier, working at 66 MHz pixel rate or 2 output amplifiers working

at 33 MHz each (assuming a Row Overhead Time (ROT) of 200 nsec).

The frame period of the LUPA-4000 sensor can be calculated as follows:

Frame period = FOT + (Nr. Lines * (ROT + pixel period * Nr. Pixels)

with: FOT: Frame Overhead Time = 5 µs.

Nr. Lines: Number of Lines read out each frame (Y).

Nr. Pixels: Number of pixels read out each line (X).

ROT: Row Overhead Time = 200 ns (nominal; can be further reduced).

Pixel period: 1/66 MHz = 15.15 ns.

Example read out of the full resolution at nominal speed (66 MHz pixel rate):

Frame period = 5 us + (2048 * (200 ns + 15.15 ns * 2048) = 64 ms => 15 fps.

ROI read out (windowing)

x-address and the y-address is 2 (only even start addresses

can be chosen). The size of both address registers is 10 bits.

When for instance the addresses 0000000001 and

0000000001 are uploaded, the readout will start at line 2 and

column 2.

Windowing can easily be achieved by a serial-parallel

uploadable interface in which the starting point of the x- and

y-address is uploaded. This downloaded starting point initiates

the shift register in the x- and y- direction triggered by the

Sync_x and Sync_y pulse. The minimum step size for the

Table 5. Frame rate as function of ROI read out and/or sub sampling

Image Resolution (X*Y)

2048 x 2048

Frame rate [frames/s]

Frame readout time [ms]

67

Comment

Full resolution.

15

31

62

1024 x 2048

32

16

4.7

Subsample in X-direction.

ROI read out.

1024 x 1024

640 x 480

210

ROI read out.

Output amplifier

between the 2 internal buses. When using 2 output-stages,

both outputs will be in phase.

1 output amplifier working at 66 Mpixels/sec is required to

bring the whole pixel array of 2048 by 2048 pixels at the

required frame rate to the outside world. A second output

stage is also foreseen to convert the analog data on-chip by 2

10-bit ADC's each working at 33 MHz. By having a second

output stage working in parallel, the pixel rate can be more

relaxed to 33 MHz for both output amplifiers. Using only one

output-stage, the output signal will be the result of multiplexing

Each output-stage has 2 outputs. One output is the pixel

signal; the second output is a DC signal which offset can be

programmed using a 7-bit word. The DC signal can be used

for common mode rejection between the 2 signals. The

disadvantage is an increase in power dissipation however this

can be reduced by setting the highest DAC voltage by means

of the SPI

Figure 5. Output stage architecture.

Image sensor

7bits

Out1: Pixel signal

Out2: dc signal

Page 9 of 38

DAC

SPI

Document Number: 38-05712 Rev. *B

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The output voltage of Out1 will be between 1.3V (dark level)

and 0.3V (white level) and depends on process variations and

voltage supply settings. The output voltage of Out2 is

determined by the DAC.

ADC should be tied externally to the outputs of the output

amplifiers.

One ADC will sample the even columns and the other one will

sample the odd columns. Although the input range of the ADC

is between 1V and 2V and the output range of the analog

signal is only between 0.3V and 1.3V, the analog output and

digital input may be tied to each other directly. This is possible

because there is an on chip level-shifter located in front of the

ADC to lift up the analog signal to the ADC range.

Pixel array drivers

We have foreseen on this image sensor on chip drivers for the

pixel array signals. Not only the driving on system level is easy

and flexible, also the maximum currents applied to the sensor

are controlled on chip. This means that the charging on sensor

level is fixed and that the sensor cannot be overdriven from

externally. In the paragraph on the timing, the operation of the

on-chip drivers is explained more in detail.

Table 6. ADC specifications

Parameter

Input range

Specification

1 - 2V (*)

Column amplifiers

Quantization

10 Bits

The column amplifiers are designed for minimum power dissi-

pation and minimum loss of signal for this reason multiple

biasing signals are needed.

Nominal data rate

33 Msamples/s

DNL (linear conversion mode) Typ. < 0.4 LSB RMS

The column amplifiers also have the "voltage-averaging"

feature integrated. In case of voltage averaging mode, the

voltage average between 2 columns is taken and read out. In

this mode only 2:1 pixels have to be read out.

INL (linear conversion mode)

Input capacitance

Typ. < 3.5 LSB

< 2 pF

Power dissipation @ 33 MHz

Conversion law

50 mW

To achieve the voltage-averaging mode, an additional external

digital signal called "voltage-averaging" is required in

combination with a bit from the SPI.

Linear/Gamma-corrected

ADC timing

Analog to Digital Converter

The ADC converts the pixel data on the falling edge of the

ADC_CLOCK but it takes 2 clock cycles before this pixel data

is at the output of the ADC. This pipeline delay is shown in

Figure .

The LUPA4000 has a two 10 bit flash analog digital converters

running nominally at 33 Msamples/s. The ADC's are

electrically separated from the image sensor. The inputs of the

Figure 6. ADC timing

Note

4. The internal ADC range will be typ. 50 mV lower then the external applied ADC_VHIGH and ADC_VLOW voltages due to voltage drops over parasitic internal

resistors in the ADC.

Document Number: 38-05712 Rev. *B

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Setting of the ADC reference voltages

Figure 7. In- and external ADC connections

2.5V

RHIGH_ADC

REF_HIGH ~ 2 V

external

internal

R_ADC

external

REF_LOW ~ 1 V

RLOW_ADC

The internal resistor R_ADChas a value of approximately 300Ω.

Resistor

R_{ADC_VLOW}

Value (Ω)

This results in the values for the external resistors:

220

Resistor

R_{ADC_VHIGH}

Value (Ω)

The values of the resistors depend on the value of R_ADC. The

voltage difference between ADC_VLOW and ADC_VHIGH

should be at least 1.0V to assure proper working of the ADC.

75

R_ADC

300

Synchronous shutter

In a synchronous (snapshot) shutter light integration takes

place on all pixels in parallel, although subsequent readout is

sequential.

Figure 8. Synchronous shutter operation

Line number

Time axis

Integration time

Burst Readout time

Document Number: 38-05712 Rev. *B

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Figure 8 shows the integration and read out sequence for the

synchronous shutter. All pixels are light sensitive at the same

period of time. The whole pixel core is reset simultaneously

and after the integration time all pixel values are sampled

together on the storage node inside each pixel. The pixel core

is read out line by line after integration. Note that the

integration and read out cycle can occur in parallel or in

sequential mode. (ref. 4. Timing and read out of the image

sensor)

Non-destructive readout (NDR)

The sensor can also be read out in a non-destructive way. After

a pixel is initially reset, it can be read multiple times, without

resetting. The initial reset level and all intermediate signals can

be recorded. High light levels will saturate the pixels quickly,

but a useful signal is obtained from the early samples. For low

light levels, one has to use the later or latest samples.

Figure 9. Principle of non-destructive readout

time

Essentially an active pixel array is read multiple times, and

reset only once. The external system intelligence takes care

of the interpretation of the data. Table 7 summarizes the

advantages and disadvantages of non-destructive readout.

• Power supplies and grounds

• Biasing and Analog signals

• Pixel array signals

• Digital signals

Table 7. Advantages and disadvantages of non-destruc-

tive readout.

• Test signals

Power supplies and ground

Advantages

Disadvantages

Every module on chip, as there are: column amplifiers, output

stages, digital modules, drivers has its own power supply and

ground. Off chip the grounds can be combined, but not all

power supplies may be combined. This results in several

different power supplies, but this is required to reduce

electrical cross-talk and to improve shielding, dynamic range

and output swing.

Low noise - as it is true CDS.

System memory required

torecordtheresetleveland

the intermediate samples.

High sensitivity - as the

conversion capacitance is kept readings of each pixel, thus

rather low.

Requires multiples

higher data throughput.

On chip we have the ground lines of every module which are

kept separately to improve shielding and electrical cross talk

between them.

High dynamic range - as the

results includes signal for short digital calculations.

and long integrations times.

Requires system level

An overview of the supplies is given in Table 8 and Table 9.

Table 9 summarizes the supplies related to the pixel array

signals, where Table 8 summarizes the supplies related with

all other modules

Operation and signalling

One can distinguish the different signals into different groups:

Table 8. Power supplies

Name

DC Current

7 mA

Max.current

50 mA

Typ.

2.5V

Max.

3.3V

Description

Vaa

Va3

Power supply column readout module.

10 mA

50 mA

3.3V

Power supply column readout module.

Should be tuneable to 3.3V max.

Vdd

1 mA

20 mA

1 mA

200 mA

20 mA

2.5V

Power supply digital modules

Power supply output stages

Analog supply of ADC circuitry

Digital supply of ADC circuitry

Voo

Vdda

Vddd

200 mA

Document Number: 38-05712 Rev. *B

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Table 9. Overview of the power supplies related to the pixel signals

Name DC current Max. current Min. Typ.

Vres 2.5V 3.5V

Max.

3.8V

Description

1 mA

200 mA

Power supply reset drivers.

Vres_ds

2.0V

2.5V

3.3V

3.5V

Power supply dual slope reset drivers.

Vmem_h

Power supply memory elements in pixel for

high voltage level

Vmem_l

1 mA

200 mA

2.0V

2.5 V

3.0V

Power supply memory elements in pixel for

low voltage level. Should be tuneable

Vdd

Vpix

1 mA

200 mA

500 mA

2.0V

2.5V

3.0V

3.3V

Power supply for Sample

12 mA

Power supply pixel array. Should be

tuneable to 3.3V

Vpre_l

1 mA

200 mA

–400 mV 0V

0V

Power supply for Precharge in off-stat. May

be connected to ground.

The maximum currents mentioned in Table 8 and Table 9 are

peak currents which occur once per frame (except for Vres_ds

in multiple slope mode). All power supplies should be able to

deliver these currents except for Vmem_l and Vpre_l, which

must be able to sink this current.

• Apply Vdd

• Apply clocks and digital pulses to the sensor to count 2048

clocks and 2048 clock_y pulses to empty the shift registers

• Apply other supplies

The maximum peak current for Vpix should not be higher than

500 mA. It is important to notice that no power supply filtering

on chip is implemented and that noise on these power supplies

can contribute immediately to the noise on the signal.

Especially the voltage supplies Vpix and Vaa are important to

be well noise free.

Biasing and analog signals

The analog output levels that may be expected are between

0.3V for a white, saturated, pixel and 1.3V for a black pixel.

2 Output stages are foreseen, each consisting of 2 output

amplifiers, resulting in 4 outputs. 1 Output amplifier is used for

the analog signal resulting from the pixels. The second

amplifier is used for a dc reference signal. The dc-level from

the buffer is defined by a DAC, which is controlled by a 7-bit

word downloaded in the SPI. Additionally, an extra bit in the

SPI defines if 1 output or the 2 output stages are used.

Start-up sequence

The LUPA-4000 will go in latch up (draw high current) as soon

as all power supplies are turned on at the same time. The

sensor will come out of latch-up and start working normally as

soon as it is being clocked. A power supply with a 400 mA limit

is recommended to avoid damage to the sensor. It is

recommended to avoid the time that the device is in the

latch-up state, so clocking of the sensor should start as soon

as possible (i.e. as soon as the system is turned on).

Table 10 summarizes the biasing signals required to drive this

image sensor. For optimisation reasons of the biasing of the

column amplifiers with respect to power dissipation, we need

several biasing resistors. This optimisation results in an

increase of signal swing and dynamic range.

In order to completely avoid latch-up of the image sensor, the

next sequence should be taken into account:

Table 10. Overview of bias signals

Signal

Out_load

Comment

Connect with 60 KΩ to Voo and capacitor of 100 nF to Gnd Output stage

Connect with 2 MΩ to Vdd and capacitor of 100 nF to Gnd X-addressing

Connect with 25 KΩ to Vaa and capacitor of 100 nF to Gnd Multiplex bus

Related module

DC-level

0.7 V

dec_x_load

muxbus_load

nsf_load

0.4 V

0.8 V

1.2 V

0.5 V

1.4 V

0.5 V

0.4 V

0.5 V

Connect with 5 KΩ to Vaa and capacitor of 100 nF to Gnd

Column amplifiers

uni_load_fast

uni_load

Connect with 10 KΩ to Vaa and capacitor of 100 nF to Gnd Column amplifiers

Connect with 1 MΩ to Vaa and capacitor of 100 nF to Gnd

Connect with 3 KΩ to Vaa and capacitor of 100 nF to Gnd

Connect with 1 MΩ to Vaa and capacitor of 100 nF to Gnd

Connect with 2 MΩ to Vdd and capacitor of 100 nF to Gnd

Connect with 1 MΩ to Vaa and capacitor of 100 nF to Gnd

Column amplifiers

Y-addressing

pre_load

col_load

dec_y_load

psf_load

Column amplifiers

Document Number: 38-05712 Rev. *B

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LUPA-4000

Table 10. Overview of bias signals (continued)

Signal

Comment

Connect with 1kΩ to Vdd and capacitor of at least 200 nF to Pixel drivers

Gnd.

Related module

DC-level

precharge_bias

1.4V

Each biasing signal determines the operation of a corre-

sponding module in the sense that it controls speed and dissi-

pation. Some modules have 2 biasing resistors: one to achieve

the high speed and another to minimize power dissipation.

no sense increasing Vpix without increasing the reset level.

The opposite does make sense. Additionally, it is this reset

pulse that also controls the dual or multiple slope feature

inside the pixel. By giving a reset pulse during integration, but

not at full reset level, the photodiode is reset to a new value,

only if his value is sufficient decreased due to light illumination.

Pixel array signals

The Pixel array of the image sensor requires digital control

signals and several different power supplies. This paragraph

explains the relation between the control signals and the

applied supplies and the internal generated pixel array signals.

The low level of reset is 0V, but the high level is 2.5V or higher

(3.3V) for the normal reset and a lower (<2.5V) level for the

multiple slope reset.

Precharge: Precharge serves as a load for the first source

follower in the pixel and is activated to overwrite the current

information on the storage node by the new information on the

photodiode. Precharge is controlled by an external digital

signal between 0 and 2.5V.

From Figure 9 one can see that the internal generated pixel

array signals are Reset, Sample, Precharge, Vmem and

Row_select. These are internal generated signals derived by

on chip drivers from external applied signals. Row_select is

generated by the y addressing and will not be discussed in this

paragraph.

Sample: Samples the photodiode information onto the

memory element. This signal is also a standard digital level

between 0 and 2.5V.

The function of each of the signals is:

Reset: Resets the pixel and initiates the integration time. If

reset is high than the photodiode is forced to a certain voltage,

depending on Vpix, which is the pixel supply; and depending

on the high level of reset signal. The higher these signals or

supplies are, the higher the voltage-swing. The limitation on

the high level of Reset and Vpix is 3.3V. Nevertheless, it has

Vmem: this signal increases the information on the memory

element with a certain offset. This way one can increase the

output voltage variation. Vmem changes between Vmem_l

(2.5V) and Vmem_h (3.3V).

Figure 10. Internal timing of the pixel. Levels are defined by the pixel array voltage supplies (For the correct polarities

of the signals refer to Table 11)

The signals in Figure 10 are generated from the on chip

drivers. These on chip drivers need 2 types of signals to

generate the exact type of signal. It needs digital control

signals between 0 and 3.3V (internally converted to 2.5V) with

normal driving capability and power supplies. The control

signals are required to indicate the moment they need to occur

and the power supplies indicate the level.

than the internal signal Vmem is low, if Mem_hl is logic "1" the

internal signal Vmem is high.

Reset is made by means of 2 control signals: Reset and

Reset_ds and 2 supplies: Vres and Vres_ds. Depending on

the signal that becomes active, the corresponding supply level

is applied to the pixel.

Table 11 summarizes the relation between the internal and

external pixel array signals.

Vmem is made of a control signal Mem_hl and 2 supplies

Vmem_h and Vmem_l. If the signal Mem_hl is the logic "0"

Document Number: 38-05712 Rev. *B

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LUPA-4000

Table 11. Overview of the in- and external pixel array signals

Internal Signal

Precharge

Sample

Vlow

Vhigh

0.45V

External control signal

Precharge (AL)

Low DC-level

Vpre_l

High DC-level

Controlled by bias-resistor

Vdd

0

2.5V

Sample (AL)

Gnd

Reset

2.5 - 3.3V

Reset (AH) & Reset_ds

(AH)

Gnd

Vres & Vres_ds

Vmem

2.0- 2.5V

2.5-3.3V

Mem_hl (AL)

Vmem_l

Vmem_h

In case the dual slope operation is desired, one needs to give

a second reset pulse to a lower reset level during integration.

This can be done by the control signal Reset_ds and by the

power supply Vres_ds that defines the level to which the pixel

has to be reset.

• Clock_x (AH): Determines the pixel rate. A clock of 33 MHz

is required to achieve a pixel rate of 66MHz.

• Spi_data (AH): the data for the SPI

• Spi_clock (AH): clock of the serial parallel interface. This

clock downloads the data into the SPI register.

Note that Reset is dominant over Reset_ds, which means that

the high voltage level will be applied for reset, if both pulses

occur at the same time.

• Spi_load (AH): when the SPI register is uploaded, then the

data will be internally available on the rising edge of

SPI_load.

Note that multiple slopes are possible having multiple

Reset_ds pulses with a lower Vres_ds level for each pulse

given within the same integration time

• Sh_kol (AL): control signal of the column readout. Is used

in sample & hold mode and in binning mode.

• Norowsel (AH): Control signal of the column readout. (See

timing).

The rise and fall times of the internal generated signals are not

very fast (200 nsec). In fact they are made rather slow to limit

the maximum current through the power supply lines

(Vmem_h, Vmem_l, Vres, Vres_ds, Vdd). Current limitation of

those power supplies is not required. Nevertheless, it is

advisable to limit the currents not higher than 400 mA.

• Pre_col (AL): Control signal of the column readout to reduce

row blanking time.

• Voltage averaging (AH): Signal required obtaining voltage

averaging of 2 pixels.

The power supply Vmem_l must be able to sink this current

because it must be able to discharge the internal capacitance

from the level Vmem_h to the level Vmem_l. The external

control signals should be capable of driving input capacitance

of about 10 pF.

Test signals

The test structures implemented in this image sensor are:

• Array of pixels (6*12) which outputs are tied together: used

for spectral response measurement.

• Temperature diode (2): Apply a forward current of 10-100

µA and measure the voltage V_Tof the diode. V_Tvaries linear

with the temperature (V_Tdecreases with approximately 1,6

mV/°C).

Digital signals

The digital signals control the readout of the image sensor.

These signals are:

• Sync_y (AH): Starts the readout of the frame. This pulse

synchronises the y-address register: active high. This signal

is at the same time the end of the frame or window and

determines the window width.

• End of scan pulses (do not use to trigger other signals):

• Eos_x: end of scan signal: is an output signal, indicating

when the end of the line is reached. Is not generated when

doing windowing.

• Clock_y (AH): Clock of the y-register. On the rising edge of

this clock, the next line is selected.

• Eos_y: end of scan signal: is an output signal, indicating

when the end of the frame is reached. Is not generated

when doing windowing.

• Eos_spi: output signal of the SPI to check if the data is

transferred correctly through the SPI.

• Sync_x (AH): Starts the readout of the selected line at the

address defined by the x-address register. This pulse

synchronises the x-address register: active high. This signal

is at the same time the end of the line and determines the

window length.

Notes

5. AH: Active High

6. AL: Active Low

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LUPA-4000

Timing and read out of the image sensor

The timing of the LUPA-4000 sensor consists of 2 parts. The

first part is related with the control of the pixels, the integration

time and the signal level. The second part is related with the

readout of the image sensor. As this image sensor is able for

full synchronous shutter, integration time and readout can be

in parallel or sequential.

In the parallel mode the integration time of the frame I is

ongoing during readout of frame I-1. Figure 11 shows this

parallel timing structure

Figure 11. Integration and read out in parallel

Read frame I

Read frame I + 1

Integration I + 2

Integration I + 1

The control of the readout of the frame and of the integration

time are independent of each other with the only exception that

the end of the integration time from frame I+1 is the beginning

of the readout of frame I+1.

The LUPA-4000 sensor also can be used in sequential mode

(triggered snapshot mode) where readout and integration will

be sequentially. Figure 12 shows this sequential timing

sequence.

Figure 12. Integration and readout sequentially

Read frame I

Integration I + 1

Integration I

Read frame I + 1

Timing of the pixel array

Figure shows the external applied signals required to control

the pixel array. At the end of the integration time from frame

I+1, the signals Mem_hl, Precharge and Sample have to be

given. The reset signal controls the integration time, which is

defined as the time between the falling edge of reset and the

rising edge of sample.

The first part of the timing is related with the timing of the pixel

array. This implies the control of the integration time, the

synchronous shutter operation and the sampling of the pixel

information onto the memory element inside each pixel. The

signals needed for this control are described in the previous

paragraph 3.9 and in Figure 10.

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Figure 13. Timing of the pixel array: The integration time is determined by the falling edge of the reset pulse. The longer

the pulse is high, the shorter the integration time. At the end of the integration time, the information has to be stored

onto the memory element for readout.

Timing specifications for each signal are:

Table 12. Timing specifications

Symbol

Name

Mem_HL

Value

5 - 8,2 µsec

3 - 6 µsec

5 - 8 µsec

> 2 µsec

a

b

c

d

e

Precharge

Sample

Precharge-Sample

Integration time

> 1 µsec

• Falling edge of Precharge is equal or later than falling edge

of Vmem.

source follower in the pixel. Sample stores the photodiode

information onto the memory element. Mem_hl pumps up this

value to reduce the loss of signal in the pixel and this signal

must be the envelop of Precharge and Sample. After Mem_hl

is high again, the readout of the pixel array can start. The

frame blanking time or frame overhead time is thus the time

that Mem_hl is low, which is about 5 µsec. Once the readout

starts, the photodiodes can all be initialised by reset for the

next integration time. The minimal integration time is the

minimal time between the falling edge of reset and the rising

edge of sample. Keeping the slow fall times of the corre-

sponding internal generated signals in mind, the minimal

integration time is about 2 µsec.

• Sample is overlapping with precharge.

• Rising edge of Vmem is more than 200 nsec after rising

edge of Sample.

• Rising edge of reset is equal or later than rising edge of

Vmem

The timing of the pixel array is straightforward. Before the

frame is read, the information on the photodiode needs to be

stored onto the memory element inside the pixels. This is done

by means of the signals Mem_hl, Precharge and Sample.

When precharge is activated it serves as a load for the first

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An additional reset pulse of minimum 2 µsec can be given

during integration by asserting Reset_ds to implement the

double slope integration mode.

sequentially. As seen in the previous section, integration and

readout can also be done in parallel.

The readout timing is straightforward and is basically

controlled by means of sync and clock pulses.

Read out of the image sensor

Figure 14 shows the top level concept of this timing. The

readout of a frame consists of the frame overhead time, the

selection of the lines sequentially and the readout of the pixels

of the selected line

As soon as the information of the pixels is stored in to the

memory element of each pixel, this information can be readout

Figure 14. Readout of the image sensor. F.O.T: Frame overhead time. R.O.T: Row overhead time. L: selection of line, C:

Selection of column

Read frame I

Integration I + 2

Readout Lines

F.O.T

L1

L2

L3

L2048

Readout pixels

R.O.T

C1

C2

C2048

The readout of an image consists of the FOT (Frame overhead

time) and the sequential selection of all pixels. The FOT is the

overhead time between 2 frames to transfer the information on

the photodiode to the memory elements. From Figure 13 it

should be clear that this time is the time that Mem_hl is low

(typically 5 µs). After the FOT the information is stored into the

memory elements and a sequential selection of rows and

columns makes sure the frame is read.

is done by means of a Clock_y and a Sync_y signal. The

Sync_y signals synchronises the y-addressing and initialises

the y-address selection registers. The start address is the

address downloaded in the SPI multiplied by 2.

On the rising edge of Clock_y the next line is selected. The

Sync_y signal is dominant and from the moment it occurs the

y-address registers are initialised. If a Sync_y pulse is given

before the end of the frame is reached, only a part of the frame

will be read. To obtain a correct initialisation Sync_y must

contain at least 1 rising edge of Clock_y when it is active.

X- and Y- addressing

To readout a frame the lines are selected sequentially.

Figure 15 gives the timing to select the lines sequentially. This

Document Number: 38-05712 Rev. *B

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LUPA-4000

Figure 15. X- and Y-addressing

Table 13. Read-out timing specifications

Symbol Name

Value

a

b

c

d

e

f

Sync_Y

>20 ns

>0 ns

Sync_Y-Clock_Y

Clock_Y-Sync_Y

NoRowSel

>0 ns

>50 ns

Pre_col

Sh_col

200 ns (more information on this timing

can be found in section 4.2.2.a)

g

h

Voltage averaging

Sync_X-Clock_X

>20 ns

>0 ns

As soon as a new line is selected, it has to be read out by the

output amplifiers. Before the pixels of the selected line can be

multiplexed onto the output amplifiers, one has to wait a

certain time, indicated as the ROT or Row overhead time

shown in Figure 15. This is the time to get the data stable from

the pixels to the output bus before the output stages. This ROT

is in fact lost time and rather critical in a high-speed sensor.

Different timings to reduce this ROT are explained in next

paragraph.

Please note that the pixel rate is the double frequency of the

Clock_x frequency. To obtain a pixel rate of 66 MHz, one needs

to apply a pixel clock Clock_x of 33MHz. When only 1 analog

output is used 2 pixels are output every Clock_x period. When

Clock_x is high, the first pixel is selected, when Clock_x is low,

the next pixel is selected. Consequently, during 1 complete

period of Clock_x 2 pixels are readout by the output amplifier.

If 2 analog outputs are used each Clock-X period 1 pixel is

presented at each output.

During the selection of 1 line, 2048 pixels are selected. These

2048 pixels have to be readout by 1 (or 2) output amplifier.

Document Number: 38-05712 Rev. *B

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Figure 16. X-addressing. From bottom to top: Clock_x, Sync_x, internal selection pixel 1&2, internal selection pixel 3&4,

internal selection pixel 5 & 6

The first pixel that is selected is the x-address downloaded in

the SPI. The starting address is the number downloaded into

the SPI, multiplied with 2.

quently, the best way to obtain a certain window is by using an

internal counter in the controller.

Figure 16 is the simulation result after extraction of the layout

module from a different sensor to show the principle. In this

figure the pixel clock has a frequency of 50 MHz, which would

result in a pixel rate of 100 Msamples/sec.

Windowing is achieved by a starting address downloaded in

the SPI and the size of the window. In the x-direction, the size

is determined by the moment a new Clock_y is given. In the

y-direction, the sync_y pulse determines the size. Conse-

Figure shows the relation between the applied Clock_x and

the output signal.

Document Number: 38-05712 Rev. *B

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Figure 17. Output signal related to Clock_x signal. From bottom to top: Clock_x, Sync_x and output. The output level

before the first pixel is the level of the last pixel of previous line

Pixel 1

Pixel2….: Pixel period : 20nsec

Output 1

saturated

dark

Sync_x

Clock_x:

25MHz

As soon as Sync_x is high and 1 rising edge of Clock_x occurs,

the pixels are brought to the analog outputs. This is again the

simulation result of a comparable sensor to show the principle.

Reduced Row Overhead Time timing

The row overhead time is the time between the selection of

lines that one has to wait to get the data stable at the column

amplifiers.

Please note there is a time difference between the clock edge

and the moment the data is seen at the output. As this time

difference is very difficult to predict in advance, it is advisable

to have the ADC sampling clock flexible to set an optimal Add

sampling point. The time differences can easily vary between

5 - 15 nsec and have to be tested on the real devices.

This row overhead time is a loss in time, which should be

reduced as much as possible.

Document Number: 38-05712 Rev. *B

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Standard timing (200 ns)

Figure 18. Standard timing for the R.O.T. Only pre_col and Norowsel control signals are required

In this case the control signals Norowsel and pre_col are made

active for about 20 nsec from the moment the next line is

selected. The time these pulses have to be active is related

with the biasing resistance Pre_load. The lower this

resistance, the shorter the pulse duration of Norowsel and

pre_col may be. After these pulses are given, one has to wait

for at least 180 nsec before the first pixels can be sampled. For

this mode Sh_col must be made active (low) all the time.

nsec, the analog data is stored. The ROT is in this case

reduced to 100 nsec, but as the internal data was not stable

yet dynamic range is lost because not the complete analog

levels are reached yet after 100 ns.

Figure 18 shows this principle. Sh_col is now a pulse of 100

ns-200 ns starting at the same moment as pre_col and

Norowsel. The duration of Sh_col is equal to the ROT. The

shorter this time the shorter the ROT will be however this

lowers also the dynamic range.

Back-up timing (ROT =100-200 ns)

A straightforward way of reducing the R.O.T is by using a

sample and hold function.

In case "voltage averaging" is required, the sensor must work

in this mode with Sh_col signal and a "voltage averaging"

signal must be generated after Sh_col drops and before the

readout starts (see Figure 15)

By means of Sh_col the analog data is tracked during the first

100 nsec during the selection of a new set of lines. After 100

Figure 19. Reduced standard ROT by means of Sh_col signal. pre_col (short pulse), Norowsel (short pulse) and Sh_col

(large pulse)

Precharging of the buses

above. The idea is to have a short pulse of about 5 ns to

precharge the output buses to a well-known level. This mode

makes the ghosting of bad columns impossible.

This timing mode is exactly the same as the mode without

sample and hold, except that the prebus1 and prebus2 signals

are activated. It should be noticed that the precharging of the

buses can be combined with all of the timing modes discussed

In this mode, Nsf_load must be made much larger (at least 1

Mohms).

Document Number: 38-05712 Rev. *B

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Figure 20. X- and Y-addressing with precharging of the buses

Table 14. Read-out timing specifications with precharching of the buses

Symbol

Name

Sync_Y

Value

a

b

c

d

e

f

>20 ns

>0 ns

Sync_Y-Clock_Y

Clock_Y-Sync_Y

NoRowSel

Pre_col

>0 ns

>50 ns

Sh_col

200 ns (or cst low, depending

on timing mode)

g

h

i

Voltage averaging

Sync_X-Clock_X

Prebus pulse

>20 ns

>0 ns

As short as possible

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LUPA-4000

Serial-Parallel-Interface (SPI)

The SPI is required to upload the different modes. Table 15

shows the parameters and there bit position

Table 15. SPI parameters

Parameter

Bit nr.

Remarks

1: from bottom to top

Y-direction

Y-address

0

1-10

11

Bit 1 is LSB

X-voltage averaging enable

X-subsampling

X-direction

1: Enabled

12

1: Subsampling

0: From left to right

Bit 14 is LSB

0: 1 Output

13

X-address

14-23

24

Nr output amplifiers

DAC

25-31

Bit 25 is LSB

When all zeros are loaded into the SPI, the sensor will start at

pixel 0,0. The scanning will be from left to right and from top to

bottom. There will be no sub-sampling or voltage averaging

and only one output is used. The DAC will have the lowest

level at its output.

When using sub sampling, only even X-addresses may be

applied.

Figure 21. SPI block diagram and timing

32 outputs to sensor

To sensor

Bit 31

Bit 0

spi_in

D

Q

Clock_spi

Load_addr

Spi_in

C

Entire uploadable block

Load_addr

D

Q

Clock_spi

C

spi_in

B0

B1

B2

B31

Unity Cell

command

applied to

sensor

Load_addr

Document Number: 38-05712 Rev. *B

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LUPA-4000

Pin list

Table 16 is a list of all the pins and their functionalities.

Pad

E1

Pin Name

sync_x

Pin Type

Input

Description

Digital input. Synchronises the X-address register.

Indicates when the end of the line is reached.

Power supply digital modules.

1

2

3

4

5

6

7

8

9

F1

D2

G2

G1

F2

H1

H2

J2

eos_x

vdd

Testpin

Supply

Input

clock_x

eos_spi

spi_data

spi_load

spi_clock

gndo

Digital input. Determines the pixel rate.

Testpin

Input

Checks if the data is transferred correctly through the SPI.

Digital input. Data for the SPI.

Digital input. Loads data into the SPI.

Digital input. Clock for the SPI.

Ground output stages

Input

Ground

Output

Supply

Output

Ground

Supply

Ground

Supply

Input

10

11

12

13

14

15

16

17

18

19

20

J1

out2

Analog output 2.

K1

M2

L1

out2DC

voo

Reference output 2.

Power supply output stages

Reference output 1.

out1DC

out1

M1

N2

P1

P2

N1

P3

Q1

Analog output 1.

gndo

Ground output stages.

vaa

Power supply analog modules.

Ground analog modules.

gnda

va3

Power supply column modules.

Power supply pixel array.

vpix

psf_load

Analog reference input. Biasing for column modules. Connect with R=1MΩ

to Vaa and decouple with C=100nF to gnda.

21

22

23

24

25

26

27

28

29

Q2

R1

R2

Q3

Q4

N3

Q5

Q6

Q7

nsf_load

Input

Analog reference input. Biasing for column modules. Connect with R=5kΩ to

Vaa and decouple with C=100nF to gnda.

muxbus_load

uni_load_fast

pre_load

Analog reference input. Biasing for multiplex bus. Connect with R=25kΩ to

Vaa and decouple with C=100nF to gnda.

Analog reference input. Biasing for column modules. Connect with R=10kΩ

to Vaa and decouple with C=100nF to gnda.

Analog reference input. Biasing for column modules. Connect with R=3kΩ to

Vaa and decouple with C=100nF to gnda.

out_load

Analog reference input. Biasing for output stage. Connect with R=60kΩ to

Vaa and decouple with C=100nF to gnda.

dec_x_load

uni_load

Analog reference input. Biasing for X-addressing. Connect with R=2MΩ to

Vdd and decouple with C=100nF to gndd.

Analog reference input. Biasing for column modules. Connect with R=1MΩ

to Vaa and decouple with C=100nF to gnda.

col_load

Analog reference input. Biasing for column modules. Connect with R=1MΩ

to Vaa and decouple with C=100nF to gnda.

dec_y_load

Analog reference input. Biasing for Y-addressing. Connect with R=2MΩ to

Vdd and decouple with C=100nF to gndd.

30

31

32

33

R3

M3

L2

L3

vdd

Supply

Ground

Input

Power supply digital modules.

gndd

Ground digital modules.

prebus1

prebus2

Digital input. Control signal to reduce readout time.

Input

Document Number: 38-05712 Rev. *B

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Pad

34

Q8

Pin Name

sh_col

Pin Type

Input

Description

Digital input. Control signal of the column readout.

35

R4

pre_col

Input

Digital input. Control signal of the column readout to reduce row-blanking

time.

36

37

38

39

R5

R6

R7

K2

norowsel

clock_y

sync_y

Input

Digital input. Control signal of the column readout.

Digital input. Clock of the Y-addressing.

Input

Digital input. Synchronises the Y-address register.

eos_y_r

Testpin

Indicates when the end of frame is reached when scanning in the 'right'

direction.

40

41

42

43

44

45

46

47

Q9

temp_diode_p

temp_diode_n

vpix

Testpin

Supply

Input

Anode of temperature diode.

Cathode of temperature diode.

Power supply pixel array.

Q10

R8

R9

vmem_l

vmem_h

vres

Power supply Vmem drivers.

Power supply reset drivers.

R10

R11

Q11

R12

vres_ds

ref_low

Analog reference input. Low reference voltage of ADC. (see Figure 7 for

exact resistor value)

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

Q12

P15

Q14

Q15

R13

R14

R15

P14

Q13

R16

Q16

P16

N14

N15

L16

L15

N16

M16

linear_conv

bit_9

Input

Digital input. 0= linear conversion; 1= gamma correction.

Digital output 1 <9> (MSB).

Digital output 1 <8>.

Output

Input

bit_8

bit_7

Digital output 1 <7>.

bit_6

Digital output 1 <6>.

bit_5

Digital output 1 <5>.

bit_4

Digital output 1 <4>.

bit_3

Digital output 1 <3>.

bit_2

Digital output 1 <2>.

bit_1

Digital output 1 <1>.

bit_0

Digital output 1 <0> (LSB).

clock

gndd

ADC clock input.

Supply

Input

Digital GND of ADC circuitry.

Digital supply of ADC circuitry (nominal 2.5V).

Analog GND of ADC circuitry.

Analog supply of ADC circuitry (nominal 2.5V).

Digital input. 0=no inversion of output bits; 1 = inversion of output bits.

vddd

gnda

vdda

bit_inv

CMD_SS

Input

Analog reference input. Biasing of second stage of ADC. Connect to VDDA

with R=50 kΩ and decouple with C=100 nF to GNDa.

66

67

L14

analog_in

CMD_FS

Input

Analog input of 1^stADC.

M15

Analog reference input. Biasing of first stage of ADC. Connect to VDDA with

R=50 kΩand decouple with C=100 nF to GNDa.

68

M14

ref_high

Input

Analog reference input. High reference voltage of ADC.

(see Figure 7 for exact resistor value)

69

70

71

K14

J14

J15

vres_ds

vres

Supply

Power supply reset drivers.

vpre_l

Power supply precharge drivers. Must be able to sink current. Can also be

connected to ground.

72

J16

vdd

Supply

Power supply digital modules.

Document Number: 38-05712 Rev. *B

Page 26 of 38

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LUPA-4000

Pad

73

74

75

K15

Pin Name

vmem_h

Pin Type

Supply

Input

Description

Power supply Vmem drivers.

K16

H15

vmem_l

ref_low

Analog reference input. Low reference voltage of ADC.

(see Figure 7 for exact resistor value)

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

H16

G16

F16

E16

G15

G14

F14

E14

D16

E15

F15

D15

C15

D14

B16

B14

C16

A16

linear_conv

bit_9

Input

Digital input. 0= linear conversion; 1= gamma correction.

Digital output 2 <9> (MSB).

Digital output 2 <8>.

Output

Input

bit_8

bit_7

Digital output 2 <7>.

bit_6

Digital output 2 <6>.

bit_5

Digital output 2 <5>.

bit_4

Digital output 2 <4>.

bit_3

Digital output 2 <3>.

bit_2

Digital output 2 <2>.

bit_1

Digital output 2 <1>.

bit_0

Digital output 2 <0> (LSB).

ADC clock input.

clock

gndd

Supply

Input

Digital GND of ADC circuitry.

Digital supply of ADC circuitry (nominal 2.5V).

Analog GND of ADC circuitry.

Analog supply of ADC circuitry (nominal 2.5V).

vddd

gnda

vdda

bit_inv

CMD_SS

Digital input. 0=no inversion of output bits; 1 = inversion of output bits.

Input

Biasing of second stage of ADC. Connect to VDDA with R=50 kΩ and

decouple with C=100 nF to GNDa.

94

95

B15

A15

analog_in

CMD_FS

Input

Analog input 2^ndADC.

Analog reference input. Biasing of first stage of ADC. Connect to VDDA with

R=50 kΩ and decouple with C=100 nF to GNDa.

96

A14

ref_high

Input

Analog reference input. High reference voltage of ADC.

(see Figure 7 for exact resistor value)

97

C14

B13

A13

A9

vres_ds

vres

Supply

Input

Power supply reset drivers.

98

Power supply reset drivers.

99

vmem_h

vmem_l

vpix

Power supply Vmem drivers.

100

101

102

103

104

105

106

107

108

109

Power supply Vmem drivers.

A10

A11

A12

B7

Power supply pixel array.

reset

Digital input. Control of reset signal in the pixel.

Digital input. Control of double slope reset in the pixel.

Digital input. Control of Vmem signal in pixel.

Digital input. Control of Vprecharge signal in pixel.

Digital input. Control of Vsample signal in pixel.

Cathode of temperature diode.

reset_ds

mem_hl

precharge

sample

Input

B8

Input

B9

Input

B10

B11

B6

temp_diode_n

temp_diode_p

Testpin

Anode of temperature diode.

precharge_bias Input

Analog reference input. Biasing for pixel array. (seeTable 10 for exact resistor

and capacitor value)

110

111

112

A8

photodiode

gndd

Testpin

Output photodiode.

A7

Ground

Supply

Ground digital modules.

Power supply digital modules.

B12

vdd

Document Number: 38-05712 Rev. *B

Page 27 of 38

[+] Feedback

LUPA-4000

Pad

113

A6

Pin Name

eos_y_l

Pin Type

Description

Testpin

Indicates when the end of frame is reached when scanning in the 'left'

direction.

114

115

116

117

118

A1

A5

A2

A3

B5

sync_y

Input

Digital input. Synchronises the Y-address register.

Digital input. Clock of the Y-addressing.

clock_y

norowsel

Digital input. Control signal of the column readout.

Digital input. Control signal of the voltage averaging in the column readout.

volt. averaging Input

pre_col

Input

Digital input. Control signal of the column readout to reduce row-blanking

time.

119

120

121

122

123

124

125

126

A4

B1

B2

C1

D1

B4

B3

C2

sh_col

prebus2

prebus1

dec_y_load

vpix

Input

Digital input. Control signal of the column readout.

Digital input. Control signal to reduce readout time.

Analog reference input. Biasing for Y-addressing.

Power supply pixel array.

Input

Supply

Ground

Supply

Ground

va3

Power supply column modules.

gnda

Ground analog modules.

vaa

Power supply analog modules.

127E2 E2

gndd

Ground digital modules.

REMARKS:

3. All unused inputs should be tied to a non-active level (e.g.

VDD or GND).

1. All pins with the same name can be connected together.

2. All digital input are active high (unless mentioned

otherwise).

Document Number: 38-05712 Rev. *B

Page 28 of 38

[+] Feedback

LUPA-4000

Geometry and Mechanical specifications

Bare die

Figure 22. Die figure of the LUPA-4000

m

27200 M

Pixel array of 2048 x 2048 pixels

Pixel 0,0

25610 Mm

Pixel 0,0 is located at 478 µm from the left side of the die and

1366 µm from the bottom side of the die.

Document Number: 38-05712 Rev. *B

Page 29 of 38

[+] Feedback

LUPA-4000

Package drawing

The LUPA-4000 is packaged in a 127-pin PGA package.

Figure 23. Package drawing of the LUPA-4000 package

Document Number: 38-05712 Rev. *B

Page 30 of 38

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LUPA-4000

Figure 24. LUPA-4000 package specifications with die

Document Number: 38-05712 Rev. *B

Page 31 of 38

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LUPA-4000

Bonding pads

The bonding pads are located as indicated below.

Figure 25. Placing of the bonding pads on the LUPA-4000 package

Document Number: 38-05712 Rev. *B

Page 32 of 38

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LUPA-4000

Bonding diagram

The die is bonded to the bonding pads of the package as

indicated below

Figure 26. Bonding pads diagram of the LUPA-4000 package.

The die will be placed in the package in a way that the center

of the light sensitive area will match the center of the package.

Document Number: 38-05712 Rev. *B

Page 33 of 38

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LUPA-4000

Glass transmittance

A D263 glass will be used as protection glass lid on top of the

LUPA-4000 monochrome sensors. Figure 24 shows the trans-

mission characteristics of the D263 glass

Figure 27. Transmission characteristics of the D263 glass used as protective cover for the LUPA-4000 sensors

100

90

80

70

60

50

40

30

20

10

0

400

500

600

700

800

900

Wavelength [nm]

Document Number: 38-05712 Rev. *B

Page 34 of 38

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LUPA-4000

Handling and soldering precautions

Special care should be given when soldering image sensors

with color filter arrays (RGB color filters), onto a circuit board,

since color filters are sensitive to high temperatures.

Prolonged heating at elevated temperatures may result in

deterioration of the performance of the sensor. The following

recommendations are made to ensure that sensor perfor-

mance is not compromised during end-users' assembly

processes.

Precautions and cleaning:

Avoid spilling solder flux on the cover glass; bare glass and

particularly glass with antireflection filters may be adversely

affected by the flux. Avoid mechanical or particulate damage

to the cover glass.

It is recommended that isopropyl alcohol (IPA) is used as a

solvent for cleaning the image sensor glass lid. When using

other solvents, it should be confirmed beforehand whether the

solvent will dissolve the package and/or the glass lid or not.

Board Assembly:

Device placement onto boards should be done in accordance

with strict ESD controls for Class 0, JESD22 Human Body

Model, and Class A, JESD22 Machine Model devices.

Assembly operators should always wear all designated and

approved grounding equipment; grounded wrist straps at ESD

protected workstations are recommended including the use of

ionized blowers. All tools should be ESD protected.

Ordering Information

Cypress Semiconductor

FillFactory Part Number

Part Number

LUPA-4000-M

CYIL1SM4000AA-GBC

Disclaimer

Manual Soldering:

The LUPA-4000 is only to be used for non-military

applications. A strict exclusivity agreement prevents us to sell

the LUPA-4000 to customers who intend to use it for military

applications.

When a soldering iron is used the following conditions should

be observed:

• Use a soldering iron with temperature control at the tip.

FillFactory image sensors are only warranted to meet the

specifications as described in the production data sheet.

Specifications are subject to change without notice.

• The soldering iron tip temperature should not exceed

350°C.

• The soldering period for each pin should be less than 5

seconds.

Please contact info@FillFactory.com for more information.

Document Number: 38-05712 Rev. *B

Page 35 of 38

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LUPA-4000

APPENDIX A: LUPA-4000 evaluation system

For evaluating purposes an LUPA-4000 evaluation kit is

available.

Visual Basic software (under Win 2000 or XP) allows the

grabbing and display of images and movies from the sensor.

All acquired images and movies can be stored in different file

formats (8 or 16-bit). All setting can be adjusted on the fly to

evaluate the sensors specs. Default register values can be

loaded to start the software in a desired state

The LUPA-4000 evaluation kit consists of a multifunctional

digital board (memory, sequencer and IEEE 1394 Fire Wire

interface) and an analog image sensor board.

Figure 28. Content of the LUPA-4000 evaluation kit

Please contact Fillfactory (info@Fillfactory.com) if you want

any more information on the evaluation kit.

Document Number: 38-05712 Rev. *B

Page 36 of 38

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LUPA-4000

APPENDIX B: Frequently Asked Questions

Q: How does the dual (multiple) slope extended dynamic range mode works?

A:

Figure 29. Dual slope diagram

Reset pulse

Read out

Double slope reset pulse

Reset level 1

Reset level 2

p1

p2

p3

p4

Saturation level

Double slope reset time (usually 5-

10% of the total integration time)

Total integration time

The green lines are the analog signal on the photodiode, which decrease as a result of exposure. The slope is determined by the

amount of light at each pixel (the more light the steeper the slope). When the pixels reach the saturation level the analog signal

will not change despite further exposure. As you can see without any double slope pulse pixels p3 and p4 will reach saturation

before the sample moment of the analog values, no signal will be acquired without double slope. When double slope is enabled

a second reset pulse will be given (blue line) at a certain time before the end of the integration time. This double slope reset pulse

resets the analog signal of the pixels BELOW this level to the reset level. After the reset the analog signal starts to decrease with

the same slope as before the double slope reset pulse. If the double slope reset pulse is placed at the end of the integration time

(90% for instance) the analog signal that would have reach the saturation levels aren't saturated anymore (this increases the

optical dynamic range) at read out. It's important to notice that pixel signals above the double slope reset level will not be

influenced by this double slope reset pulse (p1 and p2).

All products and company names mentioned in this document may be the trademarks of their respective holders.

Document Number: 38-05712 Rev. *B

Page 37 of 38

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

[+] Feedback

LUPA-4000

Document History Page

Document Title: LUPA-4000 4M PIXEL CMOS Image Sensor

Document Number: 38-05712

Orig. of

Change

REV.

ECN.

Issue Date

Description of Change

**

310396

497132

649219

See ECN

FPW

Initial Cypress Release

Converted to Frame file

*A

*B

QGS

FPW

Ordering information update+ title update + package spec label

Document Number: 38-05712 Rev. *B

Page 38 of 38

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