请登录

免费注册
全部商品
电子元器件
方案中心
工业品
PDF资料
购物车 0
上传BOM

产品分类

找货询价

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

QQ咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

会员中心
购物车
技术支持

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

售后咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

CYIS1SM0250-EVAL

型号：

CYIS1SM0250-EVAL

描述：

250K像素辐射硬CMOS图像传感器[ 250K Pixel Radiation Hard CMOS Image Sensor ]

品牌：

CYPRESS[ CYPRESS ]

页数：

24 页

PDF大小：

466 K

下载PDF手册
CYIS1SM0250-AA  
CYIS1SM0250-AA STAR250 250K Pixel  
Radiation Hard CMOS Image Sensor  
Key Features (continued)  
Features  
Parameter  
Typical Value  
The STAR250 sensor is a CMOS Active Pixel Sensor,  
designed for application in Optical Inter-Satellite Link beam  
trackers. The STAR250 is part of broader range of applications  
such as space-borne systems like sun sensing and star  
tracking. It features 512 by 512 pixels on a 25 µm pitch, on chip  
Fixed Pattern Noise (FPN) correction, a programmable gain  
amplifier, and a 10bit ADC. Flexible operating (multiple  
windowing, subsampling) is possible by direct addressable X-  
and Y- register.  
Proton Radiation  
Tolerance  
1% of pixels has an increase in  
dark current > 1 nA/cm2 after  
3*10^10 protons at 11.7 MeV  
SEL Threshold  
Color Filter Array  
Packaging  
> 80 MeV cm3 mg-1  
Mono  
84 pin JLCC  
< 350 mW  
The sensor has an outstanding radiation tolerance that is  
observed by using proprietary technology modifications and  
design techniques. Two versions of sensors are available,  
STAR250 and STAR250BK7. STAR250 has a quartz glass lid  
and air in the cavity. The STAR250BK7 has a BK7G18 glass  
lid with anti reflective coating. The cavity is filled with N2  
increasing the temperature operating range.  
Power Consumption  
Applications  
• Satellites  
• Spacecraft monitoring  
• Nuclear inspection  
Key Features  
Parameter  
Optical Format  
Active Pixels  
Pixel Size  
Typical Value  
1 Inch  
512 x 512  
25 µm  
Shutter Type  
Electronic  
8 MHz  
Maximum Data Rate /  
Master Clock  
Frame Rate  
Up to 30 full frames/s  
10 bit  
ADC Resolution  
Sensitivity  
3340 V.m2/W.s  
74dB (5000:1)  
76 e-  
Dynamic Range  
kTC Noise  
Dark Current  
4750 e-/s at RT  
Supply Voltage  
Operating Temperature  
5V  
0°C - +65°C (STAR250)  
-40°C - +85°C (STAR250BK7)  
Gamma Total Dose  
Radiation tolerance  
Increase in average dark current  
< 1 nA/cm2 after 3 MRad  
Image operation with dark signal  
< 1V/s after 10 Mrad  
demonstrated (Co60)  
Cypress Semiconductor Corporation  
Document Number: 38-05713 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised December 12, 2006  
[+] Feedback  
CYIS1SM0250-AA  
Specifications  
General Specifications  
Table 1. General Specifications  
Parameter  
Specification  
Remarks  
Pixel Architecture  
3-transistor active pixel  
4 diodes per pixel  
Radiation-tolerant pixel design  
4 photodiodes for improved MTF  
Pixel Size  
25 x 25 µm2  
512 by 512 pixels  
8 Mps  
Resolution  
Pixel Rate  
Shutter Type  
Electronic  
Integration time is variable in time, steps equal to the row  
readout time  
Frame Rate  
29 full frames/second  
Double slope  
Extended dynamic range  
Programmable gain  
Supply voltage VDD  
Programmable between x1, x2, x4, x8 Selectable through pins G0 and G1  
5V  
Operational temperature  
range  
0°C - +65°C  
-40°C - +85°C  
84 pins JLCC  
STAR250 (Quartz glass lid, air in cavity)  
STAR250BK7 (BK7G18 glass lid, N2 in cavity)  
Package  
Electro-optical Specifications  
Overview  
Table 2. Electro-optical Specifications  
Parameter  
Detector Technology  
Pixel Structure  
Specification (all typical)  
Comment  
CMOS Active Pixel Sensor  
3-transistor active pixel  
4 diodes per pixel  
Radiation-tolerant pixel design  
4 Photodiodes for improved MTF  
Photodiode  
High fill factor photodiode  
512 by 512 pixels  
25 x 25 µm2  
Sensitive Area Format  
Pixel Size  
Spectral Range  
200 - 1000 nm  
Max. 35%  
See curves  
Quantum Efficiency x Fill  
Factor  
Above 20% between 450 and 750 nm  
(Note: Metal FillFactor (MFF) is 63%)  
Full Well Capacity  
Linear Range within + 1%  
Output Signal Swing  
Conversion Gain  
311K electrons  
128K electrons  
1.68 V  
When output amplifier gain = 1  
When output amplifier gain = 1  
When output amplifier gain = 1  
When output amplifier gain = 1 near dark  
Dominated by kTC  
5.7 µV/e-  
Temporal Noise  
76 e-  
Dynamic Range  
74 dB (5000:1)  
At the analog output  
Document Number: 38-05713 Rev. *B  
Page 2 of 24  
[+] Feedback  
CYIS1SM0250-AA  
Table 2. Electro-optical Specifications (continued)  
Parameter  
Specification (all typical)  
Comment  
FPN (Fixed Pattern Noise)  
1 < 0.1% of full well  
(typical)  
Measured local, on central image area 50% of pixels, in  
the dark  
PRNU (Photo Response  
Non-uniformity)  
Local: 1 = 0.39% of response  
Global: 1 = 1.3% of response  
Measured in central image area 50% of pixels, at Qsat/2  
Average Dark Current  
Signal  
4750 e-/s  
At RT  
DSNU (Dark Signal Non  
Uniformity)  
3805 e-/s RMS  
At RT, scale linearly with integration time  
at 600 nm.  
MTF  
Horizontal: 0.36  
Vertical: 0.39  
Optical Cross Talk  
5% (TBC) to nearest neighbor if central  
pixel is homogeneously illuminated  
Anti-blooming Capacity  
Output Amplifier Gain  
Windowing  
x 1000 to x 100 000  
1, 2, 4 or 8  
Controlled by 2 bits  
X and Y 9-bit programmable shift  
registers  
Indicate upper left pixel of each window  
Electronic Shutter Range  
1: 512  
Integration time is variable in time steps equal to the row  
readout time  
ADC  
10 bit  
± 3.5 counts  
none  
ADC Linearity  
Missing Codes  
ADC Setup Time  
ADC Delay Time  
Power Dissipation  
INL  
310 ns  
To reach 99% of final value  
Average at 8 MHz pixel rate  
125 ns  
< 350 mW  
Document Number: 38-05713 Rev. *B  
Page 3 of 24  
[+] Feedback  
CYIS1SM0250-AA  
Spectral Response Curve  
Figure 1. Spectral Response Curve  
0.2  
QE 0.4  
QE 0.3  
QE 0.2  
0.15  
0.1  
QE 0.1  
QE 0.05  
QE 0.01  
0.05  
0
400  
500  
600  
700  
800  
900  
1000  
1100  
Wavelength [nm]  
Figure 2. UV Region Spectral Response Curve  
STAR250  
UV-measurement  
1,00E+00  
200  
250  
300  
350  
400  
450  
QE 100%  
500  
1,00E-01  
1,00E-02  
1,00E-03  
1,00E-04  
QE 10%  
QE 1%  
WaveLength [nm]  
Document Number: 38-05713 Rev. *B  
Page 4 of 24  
[+] Feedback  
CYIS1SM0250-AA  
Pixel Profile  
Figure 3. Pixel Profile  
horizontal pixel profile  
Vertica pixel profile  
Imaginary pixel boundaries  
0
5
10  
15  
20  
25  
30  
35  
40  
45  
50  
55  
60  
65  
70  
75  
80  
85  
90  
95 100 105 110  
Scan distance [mm]  
The pixel profile is measured using the 'knife edge' method:  
the image of a target containing a black to white transition is  
scanned over a certain pixel with subpixel resolution steps.  
The image sensors settings and the illumination conditions are  
adjusted such that the transition covers 50% of the output  
range. The scan is performed both horizontal and vertical.  
Document Number: 38-05713 Rev. *B  
Page 5 of 24  
[+] Feedback  
CYIS1SM0250-AA  
Electrical Specifications  
Absolute Maximum Ratings  
Table 3. Absolute Maximum Ratings STAR250  
Characteristics  
Limits  
Units  
Remarks  
Min  
-0.5  
-0.5  
0
Max  
+7  
Any Supply Voltage  
V
V
Voltage on any Input Terminal  
Operating Temperature  
Vdd + 0.5  
+60  
°C  
°C  
°C  
Storage Temperature  
-10  
NA  
+60  
Sensor soldering Temperature  
125  
Hand soldering only. The  
sensor’s temperature  
during soldering should not  
exceed this limit.  
Table 4. Absolute Maximum Ratings STAR250BK7  
Characteristics Limits  
Units  
Remarks  
Min  
-0.5  
-0.5  
-40  
-40  
-40  
NA  
Max  
+7  
Any Supply Voltage  
V
Voltage on any Input Terminal  
Operating Temperature  
Storage Temperature  
Vdd + 0.5  
+85  
V
°C  
°C  
°C  
°C  
+85  
+120  
125  
Maximum 1 hour  
Sensor soldering Temperature  
Hand soldering only. The  
sensor’s temperature  
during soldering should not  
exceed this limit.  
Radiation Tolerance  
Table 5. Radiation Tolerance  
Parameter  
Criterion  
Qualification level  
Gamma Total Dose Radiation  
tolerance  
Increaseinaveragedarkcurrent See graph  
< 1 nA/cm2 after 3 MRad  
Imageoperationwithdarksignal 10 Mrad demonstrated (Co60)  
< 1V/s  
Single (test) pixel operation with 24 Mrad demonstrated (Co60)  
dark signal < 1V/s  
Proton Radiation Tolerance  
SEL Threshold  
1% of pixels has an increase in see graph  
dark current > 1 nA/cm2 after  
3*10^10 protons at 11.7 MeV  
> 80 MeV cm3 mg-1  
To be confirmed  
Figure 4. shows the increase in dark current under total dose  
irradiation. This curve is measured when the radiation is at  
high dose rate. Annealing results in a significant dark current  
decrease.  
Document Number: 38-05713 Rev. *B  
Page 6 of 24  
[+] Feedback  
CYIS1SM0250-AA  
Figure 4. Dark Current Increase  
1,4  
1,2  
1
0,8  
0,6  
0,4  
0,2  
0
0
2
4
6
8
10  
12  
Total Ionizing Dose [Mrad(Si)]  
Figure 5. shows the percentage of pixels with a dark current  
increase under 11.7 Mev radiation with protons.  
Absolute Ratings are those values beyond that damage to the  
device may occur.  
Figure 5. Percentage of Pixels with Dark Current Increase  
Notes  
1. All parameters are characterized for DC conditions after establishing thermal equilibrium.  
2. Unused inputs must always be tied to an appropriate logic level, e.g. either VDD or GND.  
3. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. Take, normal precautions to avoid applying any  
voltages higher than the maximum rated voltages to this high-impedance circuit.  
Document Number: 38-05713 Rev. *B  
Page 7 of 24  
[+] Feedback  
CYIS1SM0250-AA  
DC Operating Conditions  
Table 6. DC operating conditions  
Symbol  
Parameter  
Min  
Typ  
Max  
Units  
V
VDD_ANA  
VDD_DIG  
VDD_ADC_ANA  
VDD_ADC_DIG  
VDD_ADC_DIG_3.3/5  
VIH  
Analogue supply voltage to imager part  
Digital supply voltage to imager part  
Analogue supply voltage to ADC  
Digital supply voltage to ADC  
Supply voltage of ADC output stage  
Logical '1' input voltage  
5
5
V
5
5
V
V
3.3 to 5  
V
2.3  
0
Vdd  
1
V
VIL  
Logical '0' input voltage  
V
VOH  
Logical '1' output voltage  
4.25  
4.5  
0.1  
5
V
VOL  
Logical '0' output voltage  
1
V
VDD_PIX  
Pixel array power supply (default 5V, the device is  
then in "soft reset". In order to avoid the image lag  
associated with soft reset, reduce this voltage to  
3…3.5V "hard reset")  
V
VDD_RESL  
Reset power supply  
5
V
Document Number: 38-05713 Rev. *B  
Page 8 of 24  
[+] Feedback  
CYIS1SM0250-AA  
Sensor Architecture  
Figure 6. STAR250 Schematic  
Clk_YR  
SyncYR  
Sync_YL  
Clk_YL  
9
10  
512  
512  
Pixel Array  
512 by 512 Pixels  
D9...D0  
Ld_Y  
Col  
Sel  
Rst  
9
9
Clk_ADC  
Ain  
A8...A0  
512  
S
R
Column Amplifiers  
Rst  
1024  
1024  
Progr. Gain  
Amplifier  
512  
Aout  
Sig  
9
X Address  
Decoder / Shift Register  
Ld_X  
The base line of the STAR250 sensor design consists of an  
imager with a 512 by 512 array of active pixels at 25 µm pitch.  
The detector contains on-chip correction for Fixed Pattern  
Noise (FPN) in the column amplifiers, a programmable gain  
output amplifier and a 10-bit Analog-to-Digital Converter  
(ADC). Through additional preset registers the start position of  
a window can be programmed to enable fast read out of only  
part of the detector array.  
the column bus by T3. The Reset and the Read entrance of  
the pixel are connected to one of the Y shift registers.  
Figure 7. STAR250 Pixel Structure  
T1  
Read  
Reset  
T2  
Pixel Structure  
The image sensor consists of several building blocks as  
outlined in Figure 6. The central element is a 512 by 512 pixel  
array with square pixels at 25 µm pitch. Unlike classical  
designs, the pixels of this sensor contain four photodiodes.  
This configuration enhances the MTF and reduces the PRNU.  
Figure 7. shows an electrical diagram of the pixel structure.  
The four photodiodes are connected in parallel to the reset  
transistor (T1). Transistor T2 converts the charge, collected on  
the photo diode node, to a voltage signal that is connected to  
T3  
Document Number: 38-05713 Rev. *B  
Page 9 of 24  
[+] Feedback  
CYIS1SM0250-AA  
Shift Registers  
The first process resets lines in a progressive scan. At line  
reset, all the pixels in a line are drained from any photo  
charges collected since their last reset or readout. After reset,  
a new exposure cycle starts for that particular line.  
The shift registers are located next to the pixel array and  
contain as many outputs as the number of rows in the pixel  
array. They are designed as "1-hot" registers, (YL and YR shift  
register) each allowing selection of one row of pixels at a time.  
A clock pulse moves the pointer one position down the register  
resulting in the selection of every individual row for either reset  
or for readout. The spatial offset between the two selected  
rows determines the integration time. A synchronization pulse  
to the shift registers loads the value from a preset register into  
the shift register forcing the pointer to a predetermined  
position. Windowing in the vertical (Y) direction is achieved by  
presetting the registers to a row that is not the first row and by  
clocking out only the required number of rows.  
The second process is the actual readout, which also happens  
in an equally fast linewise progressive scan.  
During readout, the photo charges collected since the  
previous reset are converted into an output voltage. This is  
then passed on pixel by pixel to the imager's pixel serial output  
and ADC. Readout is destructive, meaning the accumulation  
of charges from successive exposure phases is not possible  
in the present architecture.  
The STAR250 has two Y- shift registers; YL and YR. One is  
used for readout of a line (YL) and the other is used to reset a  
line (YR). The integration time is equal to the time between the  
last reset and the readout of that line, see Figure 8. The  
integration time is thus equal to:  
Column Amplifiers  
All outputs from the pixels in a column are connected in parallel  
to a column amplifier. This amplifier samples the output  
voltage and the reset level of the pixel whose row is selected  
at that moment and presents these voltage levels to the output  
amplifier. As a result, the pixels are always reset immediately  
after readout as part of the sample procedure and the  
maximum integration time of a pixel is the time between two  
read cycles.  
Integration time = (Nr. Lines * (RBT + pixel period * Nr. Pixels))  
with:  
• Nr. Lines: Number of Lines between readout and reset (Y).  
• Nr. Pixels: Number of pixels read out each line (X).  
• RBT: Row Blanking Time = 3.2 µs (typical).  
• Pixel period: 1/8 MHz = 125 ns (typical).  
Electronic Shutter  
In a linescan integrating imager with electronic shutter, there  
are two continuous processes of image gathering.  
Figure 8. Electronic Shutter  
x
Reset line  
Read line  
y
x
y
Reset sequence  
Line number  
Time axis  
Integration time  
Frame time  
Document Number: 38-05713 Rev. *B  
Page 10 of 24  
[+] Feedback  
CYIS1SM0250-AA  
Programmable Gain Amplifier  
Image Readout  
The signal from the column amplifiers is fed to an output  
amplifier with four presettable gains (adjustable with pins G0  
and G1). The offset correction of this amplifier is done through  
a black reference procedure. The signal from the output  
amplifier is externally available on the analog output  
terminator of the device.  
In an infinite uninterrupted loop, follow these steps line-by-line:  
1. Synchronize the read (YL) and/or reset (YR) registers, in  
this cases:  
• SYNC_YL - to reinitiate the readout sequence to row  
position Y1  
• SYNC_YR - to reinitiate the reset pointer to row position  
Y1  
Analog-to-Digital Converter  
For all other lines do not pulse one of these SYNC_Y signals.  
The on-chip 10-bit ADC is electrically separated from the other  
circuits of the device. The ADC conversion range is set by the  
voltages on VLOW_ADC (pin 47) and VHIGH_ADC (pin 70).  
Make voltages on these pins equal to about 2V on  
VLOW_ADC and 4V on VHIGH_ADC. The voltages are set by  
connecting VLOW with 1.2kΩ to GND and VHIGH_ADC with  
560Ω to VDD. This way, a resistor ladder is created as shown  
in Figure 9.  
2. Operate the double sampling column amplifiers with two  
RESETs. Apply one to reset the line that is currently  
selected to produce the reset reference level for the double  
sampling column amplifiers. Apply the other reset to  
another line depending on the required integration time  
reduction.  
3. Perform a Line Readout:  
Figure 9. ADC Resistor Ladder  
Reset the X read address shift register to the value in its  
shadow register (X1).  
Perform a pixel readout operation, operating the track/hold  
and the ADC.  
RADC_VHIGH  
Shift the X read address shift register one position further.  
Shift the Y read and reset address shift registers one position  
further. If either of Y read or reset address shift register comes  
to the end of the pixel array (or the ROI), wrap it around to the  
start position by pulsing SYNC_YL.  
Pin 70: VHIGH_ADC  
External  
Internal  
RADC  
Readout Timing  
The actual line readout process starts with addressing the line  
to read. This is done either by initializing the YL pointer with a  
new value, or by shifting it one position beyond its previous  
value. (Addressing the line has reset, YR is done in an  
analogous fashion). During the "blanking time", after the new  
line is addressed on the sensor, the built-in column-parallel  
double sampling amplifiers are operated. This renders  
offset-corrected values of the line under readout.  
External  
Pin 47: VLOW_ADC  
RADC_VLOW  
After the blanking time the pixels of the row addressed by YL  
are read by multiplexing all the pixels one by one to the serial  
output chain. The pixel is selected by the X pointer, and that  
pointer is either initialized with a new value or an increment of  
the previous position.  
The internal ADC resistance varies according to temperature.  
The resistance value increases approximately 4.4 Ω/°C with  
increasing temperature. If the ADC range is set externally with  
resistors, the conversion range may vary with temperature.  
This effect is cancelled out by not making use of resistors but  
directly applying voltages on VLOW_ADC and VHIGH_ADC.  
The time between row resets and their corresponding row  
readouts is the effective exposure time (or integration time).  
This time is proportional to the number of lines (DelayLines)  
between the line currently under reset and the line currently  
under readout: DelayLines = (YR - YL+1). This time is also  
equal to the delay between the SYNC_YR pulse and the  
subsequent SYNC_YR.  
Timing and Readout of the Image Sensor  
Image Readout Procedure  
The effective integration time tint is calculated as delaylines *  
line time. The line time itself is a function of four terms: the time  
to output the desired number of pixels in the line (Wframe), and  
the overhead ("blanking") time that is needed to select an new  
line and perform the double sampling and reset operations.  
A preamble or initialization phase is irrelevant. The sensor is  
read out continuously. The first frame is generally saturated  
and useless because there is no preceding reset of each pixel.  
Document Number: 38-05713 Rev. *B  
Page 11 of 24  
[+] Feedback  
CYIS1SM0250-AA  
Figure 10. Basic Readout Timing  
SYNC_YL  
SYNC_YR  
T13  
T10  
CAL  
T2  
T9  
T16  
Row Start  
Address  
T15  
T17  
LD_Y  
CLK_YL  
CLK_YR  
T14  
T12  
T1  
S
T3  
T7  
RESET  
T4  
T4  
T6  
R
T11  
T5  
L/R  
T8  
Time Available for Read Out of Row Y  
Row  
Y-1  
Row Blanking Time  
SYNC_YR is not identical to as SYNC_YL. SYNC_YR is used  
in case of electronic shutter operation. The CLK_YR is driven  
identically as CLK_YL, but the SYNC_YR pulse leads the  
SYNC_YL pulse by a certain number of rows. This lead time  
is the effective integration (electronic shutter ~) time. Relative  
to the row timing, both SYNC pulses are given at the same  
time position, once for each frame, but during different rows.  
first row. CAL is pulsed on the first row too, 2 µs later than  
SYNC_YL.  
The minimal idle time is 1.4 µs (before starting reading pixels).  
However, do not read out pixels during the complete row initial-  
ization process (in between the rising edge on S and the falling  
edge on L/R). In this case, the total idle time is minimal. This  
timing assumes that the Y start register was loaded in  
advance, which can occur at any time but before the pulse on  
SYNC_YL or SYNC_YR.  
SYNC_YL is pulsed when the first row is read out and  
SYNC_YR is pulsed for the electronic shutter to start for this  
Table 7. Readout Timing Specifications  
Symbol  
Min  
Typ  
Description  
T1  
1.8 µs  
Delay between selection of new row by falling edge on CLK_YL and falling edge on S.  
Minimal value. Normally, CLK_YR is low already at the end of the previous sequence.  
T2  
T3  
T4  
T5  
1.8 µs  
0.4 µs  
Delay between selection of new a row by SYNC_YL and falling edge on S.  
Duration of S and R pulse.  
0.1 µs  
Duration of RESET pulse.  
T4 + 40 ns  
0.3 µs  
L/R pulse must overlap second RESET pulse at both sides.  
Document Number: 38-05713 Rev. *B  
Page 12 of 24  
[+] Feedback  
CYIS1SM0250-AA  
Table 7. Readout Timing Specifications (continued)  
Symbol  
T6  
Min  
0.8 µs  
20 ns  
0
Typ  
Description  
Delay between falling edge on RESET and falling edge on R.  
Delay between falling edge on S and rising edge on RESET.  
Delay between falling edge on L/R and falling edge on CLK_Y.  
Duration of cal pulse. The CAL pulse is given once each frame.  
Delay between falling edge of SYNC_YL and rising edge of CAL pulse.  
Delay between falling edge on R and rising edge on L/R.  
Delay between rising edge of CLK_Y and falling edge on S.  
Pulse width SYNC_YL / YR  
T7  
0.1 µs  
1 µs  
T8  
T9  
100 ns  
0
1 µs  
T10  
T11  
T12  
T13  
T14  
T15  
T16  
T17  
T18  
T19  
T20  
T21  
T22  
2 µs  
40 ns  
0.1 µs  
0.1 µs  
1 µs  
0.5 µs  
0.5 µs  
Pulse width CLK_YL / YR  
10 ns  
20 ns  
10 ns  
10 ns  
20 ns  
10 ns  
Address set-up time  
Load X / Y start register value  
Address stable after load  
SYNC_X pulse width. SYNC_X while CLK_X is high.  
40 ns  
40 ns  
Analogue output is stable during CLK_X low.  
CLK_X pulse width: During this clock phase the analogue output ramps to the next  
pixel level.  
T23  
125 ns  
ADC digital output stable after falling edge of CLK_ADC  
Loading the X- and Y- Start Positions  
The following timing constraints apply:  
The start positions (start addresses) for "ROI" (Region Of  
Interest) are preloaded in the X or Y start register. They  
become effective by the application of the SYNC_X,  
SYNC_YL and/or SYNC_YR. The start X- or Y address must  
be applied to their common address bus, and the  
corresponding LD_X or LD_Y pin must be pulsed.  
Load the X or Y start addresses in advance, before the X or Y  
shift registers are preset by a SYNC pulse. However, if  
necessary, they can be load just before the SYNC_X or  
SYNC_Y pulse as shown in the Figure 11.  
E.g. the X start register can be loaded during the row idle time.  
The Y start register can be loaded during readout of the last  
row of the previous frame.  
On each falling edge of CLK_X, a new pixel of the same row  
(line) is accessed. The output stage is in hold when CLK_X is  
low and starts generating a new output after a rising edge on  
CLK_X.  
If the X or Y start address does not change for later frames, it  
does not need to be reloaded in the register.  
Document Number: 38-05713 Rev. *B  
Page 13 of 24  
[+] Feedback  
CYIS1SM0250-AA  
Figure 11. Timing for Loading the X- and Y- Register  
Row Blanking Time  
Time Available for Read Out of Row Y  
Column Start  
Address  
T15  
T17  
LD_X  
T16  
T19  
SYNC_X  
CLK_X  
T18  
T20  
T21  
T22  
Analog  
Output  
Pixel 3  
Pixel 1  
Pixel 2  
CLK ADC  
ADC Out  
T23  
Pixel 1  
Pixel 2  
Other Signals  
used mainly during testing to verify proper operation of the shift  
registers.  
Tie SELECT signal to VDD for normal operation. This signal  
was added for diagnostic reasons and inhibits the pixel array  
operation when held low.  
TEST DIODE and TESTPIXEL ARRAY are connections to  
optical test structures that are used for electro optical  
evaluation. TESTDIODE is a plain photodiode with an area of  
14x5 pixels. TESTPIXEL_ARRAY is an array (14x5) of pixels  
where the photodiodes are connected in parallel. These  
structures measure the photocurrent of the diodes directly.  
The CAL signal sets the output amplifier DC offset level. When  
this signal is active (high) the pixel array is internally  
disconnected from the output amplifier, its gain is set to unity  
and its input signal is connected to the BLACK_REF input.  
Perform this action at least once for each frame.  
TESTPIXEL_RESET and TESTPIXEL-OUT are connections  
to a single pixel that are used for testing.  
EOS_X, EOS_YL and EOS_YR produce a pulse when the  
respective shift register comes at its end. These outputs are  
Document Number: 38-05713 Rev. *B  
Page 14 of 24  
[+] Feedback  
CYIS1SM0250-AA  
Pinlist  
Table 8. Power Supply Connections  
Pin  
10  
11  
Pin Name  
VDD_ANA  
Pin Description  
Analog power supply 5V.  
Digital power supply 5V.  
VDD_DIG  
31  
33  
34  
49  
50  
53  
66  
67  
69  
VDD_AMP  
Power supply of output amplifier 5V.  
Digital power supply 5V.  
VDD_DIG  
VDD_ANA  
Analogue power supply 5V.  
Reset power supply 5V.  
VDD_RESR  
VDD_DIG  
Digital power supply 5V.  
VDD_ADC_ANA  
VDD_ADC_ANA  
VDD_ADC_DIG  
ADC analogue power supply 5V.  
ADC analogue power supply 5V.  
ADC digital power supply 5V.  
VDD_ADC_DIG_3.3/5 ADC 3.3V power supply for digital output of ADC.  
For interface with 5V external system: connect to VDD_ADC_DIG.  
For interface with 3.3 V external system: connect to 3.3V power supply.  
52  
76  
VDD_PIX  
Pixel array power supply [default: 5V, the device is then in "soft reset". In order to avoid  
the image lag associated with soft reset, reduce this voltage to 3…3.5 V "hard reset"].  
78  
79  
VDD_DIG  
Digital power supply 5V.  
Reset power supply 5V.  
VDD_RESL  
Table 9. Ground Connections  
Pin  
9
Pin Name  
GND_ANA  
Pin Description  
Analog ground.  
12  
30  
32  
35  
51  
54  
65  
68  
77  
GND_DIG  
Digital ground.  
GND_AMP  
Ground of output amplifier.  
Digital ground.  
GND_DIG  
GND_ANA  
Analog ground.  
GND_DIG  
Digital ground.  
GND_ADC_ANA  
GND_ADC_ANA  
GND_ADC_DIG  
GND_DIG  
ADC analog ground.  
ADC analog ground.  
ADC digital ground.  
Digital ground.  
Table 10. Digital Input Signals  
Pin  
Pin Name  
Pin Description  
1
S
Control signal for column amplifier.  
Apply pulse pattern - see sensor timing diagram.  
2
R
Control signal for column amplifier.  
Apply pulse pattern - see sensor timing diagram.  
Document Number: 38-05713 Rev. *B  
Page 15 of 24  
[+] Feedback  
CYIS1SM0250-AA  
Table 10. Digital Input Signals (continued)  
Pin  
Pin Name  
Pin Description  
Resets row indicated by left/right shift register.  
3
RESET  
high active (1= reset row).  
Apply pulse pattern - see sensor timing diagram.  
4
5
SELECT  
L/R  
Selects row indicated by left/right shift register.  
high active (1=select row).  
Apply 5 V DC for normal operation.  
Use left or right shift register for SELECT and RESET.  
1 = left / 0 = right - see sensor timing diagram.  
6
A0  
A1  
Start address for X- and Y- pointers (LSB).  
Start address for X- and Y- pointers.  
Start address for X- and Y- pointers.  
Start address for X- and Y- pointers.  
Start address for X- and Y- pointers.  
Start address for X- and Y- pointers.  
Start address for X- and Y- pointers.  
Start address for X- and Y- pointers.  
Start address for X- and Y- pointers (MSB).  
7
8
A2  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
A3  
A4  
A5  
A6  
A7  
A8  
LD_Y  
LD_X  
CLK_YL  
SYNC_YL  
Latch address (A0…A8) to Y start register (0 = track, 1 = hold).  
Latch address (A0…A8) to X start register(0 = track, 1 = hold).  
Clock YL shift register (shifts on falling edge).  
Sets YL shift register to location preloaded in Y start register.  
Low active (0=sync).  
Apply SYNC_YL when CLK_YL is high.  
24  
25  
CLK_X  
Clock X shift register (output valid & s when CLK_X is low).  
SYNC_X  
Sets X shift register to location preloaded in X start register.  
Low active (0=sync).  
Apply SYNC_X when CLK_X is high.  
After SYNC_X, apply falling edge on CLK_X, and rising edge on CLK_X.  
27  
28  
CLK_YR  
Clock YR shift register (shifts on falling edge).  
SYNC_YR  
Sets YR shift register to location preloaded in Y start register.  
Low active (0=sync).  
Apply SYNC_YR when CLK_YR is high.  
36  
37  
CAL  
G0  
Initialize output amplifier.  
Output amplifier will output BLACKREF in unity gain mode when CAL is high (1).  
Apply pulse pattern (one pulse per frame) - see sensor timing diagram.  
Select output amplifier gain value: G0 = LSB; G1 = MSB.  
00 = unity gain; 01 = x2; 10= x4; 11=x8.  
38  
71  
G1  
idem.  
CLK_ADC  
ADC clock.  
ADC converts on falling edge.  
75  
BITINVERT  
1 = invert output bits.  
0 = no inversion of output bits.  
Document Number: 38-05713 Rev. *B  
Page 16 of 24  
[+] Feedback  
CYIS1SM0250-AA  
Table 10. Digital Input Signals (continued)  
Pin  
Pin Name  
Pin Description  
Tri-state control of digital ADC outputs  
80  
TRI_ADC  
1 = tri-state; 0 = output  
Table 11. Digital Output Signals  
Pin  
Pin Name  
Pin Description  
23  
EOS_YL  
End-of-scan of YL shift register.  
Low first clock period after last row (low active).  
26  
29  
EOS_X  
End-of-scan of X shift register.  
Low first clock period after last active column (low active).  
EOS_YR  
End-of-scan of YR shift register.  
Low first clock period after last row (low active).  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
ADC output bit (LSB).  
ADC output bit.  
ADC output bit.  
ADC output bit.  
ADC output bit.  
ADC output bit.  
ADC output bit.  
ADC output bit.  
ADC output bit.  
ADC output bit (MSB).  
Table 12. Analog Input Signals  
Pin  
39  
Pin Name  
NBIASARR  
PBIAS  
Pin Description  
Connect with 470 k to Vdd and decouple to ground with a 100 nF capacitor.  
40  
Connect with 39 k to ground and decouple to Vdd with a 100 nF capacitor for 8 MHz  
pixel rate. (Lower resistor values yield higher maximal pixel rates at the cost of extra  
power dissipation).  
41  
NBIAS_AMP  
Output amplifier speed/power control.  
Connect with 51kΩ to VDD and decouple with 100 nF to GND for 8 MHz output rate  
(Lower resistor values yield higher maximal pixel rates at the cost of extra power  
dissipation).  
42  
44  
BLACKREF  
IN_ADC  
Control voltage for output signal offset level.  
Buffered on-chip, the reference level can be generated by a 100kΩ resistive divider.  
Connect to +/- 2 V DC for use with on-chip ADC.  
Input, connect to sensor's output.  
Input range is between 2 & 4 V (VLOW_ADC & VHIGH_ADC).  
45  
46  
NBIASANA2  
NBIASANA  
Connect with 100 k to VDD and decouple to GND.  
Connect with 100 k to VDD and decouple to GND.  
47  
70  
VLOW_ADC  
VHIGH_ADC  
Low reference and high reference voltages of ADC should be about 2 and 4V.  
The required voltage settings on VLOW_ADC and VHIGH_ADC can be approximated  
by tying VLOW_ADC with 1.2kΩ to GND and VHIGH_ADC with 560Ω to VDD.  
Document Number: 38-05713 Rev. *B  
Page 17 of 24  
[+] Feedback  
CYIS1SM0250-AA  
Table 12. Analog Input Signals (continued)  
Pin  
Pin Name  
Pin Description  
Anti-blooming drain control voltage:  
48  
G_AB  
Default: connect to ground. The anti-blooming is operational but not maximal.  
Apply 1V DC for improved anti-blooming.  
72  
73  
74  
PBIASDIG2  
PBIASENCLOAD  
PBIASDIG1  
Connect with 100K to GND and decouple to VDD.  
Connect with 100K to GND and decouple to VDD.  
Connect with 47K to GND and decouple to VDD.  
Table 13. Analog Output Signals  
Pin  
Pin Name  
Pin Description  
43  
OUT  
Analogue output signal are connected to the analogue input of the ADC.  
Table 14. Test Structures  
Pin  
Pin Name  
Pin Description  
81  
TESTDIODE  
Plain photo diode, size: 14 x 25 pixels.  
Must be left open for normal operation.  
82  
83  
84  
TESTPIX  
ARRAY  
Array of test pixels, connected in parallel (14 x 25 pixels).  
Must be left open for normal operation.  
TESTPIXEL_RESET  
Reset input of single test pixel.  
Must be tied to GND for normal operation.  
TESTPIXEL_OUT  
Output of single test pixel.  
Must be left open for normal operation.  
Document Number: 38-05713 Rev. *B  
Page 18 of 24  
[+] Feedback  
CYIS1SM0250-AA  
Package  
Package with Glass  
Note: All dimension in Figure 12. are measured in inches.  
Figure 12. STAR250 Package Dimensions  
Table 15. Package Specifications:  
Type  
Material  
JLCC-84  
Black Alumina BA-914  
7.6 x 10-6 /K  
Thermal expansion coefficient  
Document Number: 38-05713 Rev. *B  
Page 19 of 24  
[+] Feedback  
CYIS1SM0250-AA  
Die Alignment  
Figure 13. Die Alignment  
Parallelism in  
X and Y within  
+ 50 Pm  
68 P  
Pin 1  
Center of Cavity  
and of FPA  
Center of  
Silicium  
Offset Between Center of  
Silicium and Center of  
Cavity:  
A
A
X: 0  
Y: 68 Pm  
Die:  
0.508+0.01  
Bonding Cavity:  
0.508+0.051  
Glass Window:  
1.0+/-0.05  
Window Adhesive:  
0.08+0.02  
Die Cavity:  
0.508+0.051  
A -  
Die Adhesive:  
0.08+0.02  
Section A  
Drawing Not to Scale  
The die is aligned manually in the package to a tolerance of ±50 µm and the alignment is verified after hardening the die adhesive.  
All dimensions in figure 13 are in mm.  
Document Number: 38-05713 Rev. *B  
Page 20 of 24  
[+] Feedback  
CYIS1SM0250-AA  
Window Specifications  
STAR250  
Table 16. STAR250 Glass Cover Specifications:  
Material  
Dimensions  
Fused Silica  
25 x 25 mm +- 0.2 mm  
Thickness  
1 mm +- 0.05 mm  
Anti reflective coating  
Cavity fill  
No  
Air  
STAR250BK7  
Table 17. STAR250BK7 Glass Cover Specifications  
Material  
Dimensions  
BK7G18  
25 x 25 mm +- 0.2 mm  
1 mm +- 0.05 mm  
Yes  
Thickness  
Anti reflective coating  
Cavity fill  
N2  
Document Number: 38-05713 Rev. *B  
Page 21 of 24  
[+] Feedback  
CYIS1SM0250-AA  
Use a soldering iron with temperature control at the tip. The  
soldering iron tip temperature should not exceed 350°C.  
Soldering and Handling  
Soldering and Handling Conditions  
The soldering period for each pin should be less than five  
seconds.  
Take special care when soldering image sensors onto a circuit  
board. Prolonged heating at elevated temperatures may result  
in deterioration of the performance of the sensor. The following  
recommendations are made to ensure that sensor  
performance is not compromised during end users' assembly  
processes.  
Reflow Soldering  
Reflow soldering is not allowed.  
Precautions and Cleaning  
Avoid spilling solder flux on the cover glass; bare glass and  
particularly glass with antireflection filters may be harmed by  
the flux. Avoid mechanical or particulate damage to the cover  
glass.  
Board Assembly  
The STAR250 is very sensitive to ESD. Device placement onto  
boards should be done in accordance with strict ESD controls  
for Class 0, JESD22 Human Body Model, and Class A,  
JESD22 Machine Model devices. Assembly operators need to  
always wear all designated and approved grounding  
equipment; grounded wrist straps at ESD protected  
workstations are recommended including the use of ionized  
blowers. All tools should be ESD protected.  
Use isopropyl alcohol (IPA) as a solvent for cleaning the image  
sensor glass lid. When using other solvents, it should be  
confirm whether the solvent will dissolve the package and/or  
the glass lid.  
RoHS (lead free) Compliance  
Manual Soldering  
This paragraph reports the use of Hazardous chemical  
substances as required by the RoHS Directive (excluding  
packing material).  
When a soldering iron is used the following conditions should  
be observed:  
Table 18. Chemical Substances in STAR250 Sensor  
If there is any intentional content, in which portion  
is it contained?  
Chemical Substance  
Any intentional content  
Lead  
NO  
NO  
NO  
NO  
NO  
NO  
-
-
-
-
-
-
Cadmium  
Mercury  
Hexavalent chromium  
PBB (Polybrominated biphenyls)  
PBDE (Polybrominated diphenyl ethers)  
Information on Lead Free Soldering  
to produce and maintain the required performance and  
function of the intended product  
The product cannot withstand a lead free soldering process.  
Reflow or wave soldering is not allowed. Hand soldering only.  
Solder 1 pin on each side of the sensor and let it cool down for  
at least 1 minute before continuing  
2. A case that the above material, which is used intentionally  
in the manufacturing process, is contained in or adhered to  
the inquired product.  
The following case is not treated as "intentional content":  
Note: "Intentional content" is defined as any material  
demanding special attention is contained into the inquired  
product by these cases:  
A case that the above material is contained as an impurity into  
raw materials or parts of the intended product. The impurity is  
defined as a substance that cannot be removed industrially, or  
it is produced at a process like chemical composing or reaction  
and it cannot be removed technically.  
1. A case that the above material is added as a chemical  
composition into the inquired product intentionally in order  
Document Number: 38-05713 Rev. *B  
Page 22 of 24  
[+] Feedback  
CYIS1SM0250-AA  
Ordering Information  
Part Numbers  
FillFactory part number  
STAR250  
Cypress Part number  
CYIS1SM0250AA-HQC  
CYIS1SM0250AA-HHC  
CYIS1SM0250-EVAL  
Package  
Glass Lid  
Mono/Color  
Mono  
84-pin JLCC  
84-pin JLCC  
84-pin JLCC  
Quartz fused silica  
BK7G18  
STAR250BK7  
Mono  
Evaluation system  
Quartz fused silica  
Mono  
Evaluation kit  
grabbing and display of images from the sensor. All acquired  
images can be stored in different file formats (8 or 16-bit). All  
setting can be adjusted on the fly to evaluate the sensors  
specs. Default register values can be loaded to start the  
software in a desired state. Please contact us for more  
information.  
For evaluating purposes an STAR250 evaluation kit is  
available. The STAR250 evaluation kit consists of  
multifunctional digital board (memory, sequencer and IEEE  
1394 Fire Wire interface) and an analog image sensor board.  
Visual Basic software (under Win 2000 or XP) allows the  
a
All products and company names mentioned in this document  
may be the trademarks of their respective holders  
Document Number: 38-05713 Rev. *B  
Page 23 of 24  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
[+] Feedback  
CYIS1SM0250-AA  
Document History Page  
Document Title: CYIS1SM0250-AA STAR250 250K Pixel Radiation Hard CMOS Image Sensor  
Document Number: 38-05713  
ISSUE  
DATE  
ORIG. OF  
CHANGE  
REV.  
ECN NO.  
DESCRIPTION OF CHANGE  
**  
*A  
*B  
310213  
603159  
649360  
SEE ECN  
SEE ECN  
SEE ECN  
SIL  
Origination  
QGS  
FPW  
Converted to Framemaker Format  
Title update + package spec label  
Document Number: 38-05713 Rev. *B  
Page 24 of 24  
[+] Feedback  
厂商 型号 描述 页数 下载

CYPRESS

 		CYI9530ZXC PCIX I / O系统时钟发生器，带有EMI控制功能[ PCIX I/O System Clock Generator with EMI Control Features ] 11 页

CYPRESS

 		CYI9530ZXCT PCIX I / O系统时钟发生器，带有EMI控制功能[ PCIX I/O System Clock Generator with EMI Control Features ] 11 页

CYPRESS

 		CYI9531OXC PCIX I / O系统时钟发生器，带有EMI控制功能[ PCIX I/O System Clock Generator with EMI Control Features ] 10 页

CYPRESS

 		CYI9531OXCT PCIX I / O系统时钟发生器，带有EMI控制功能[ PCIX I/O System Clock Generator with EMI Control Features ] 10 页

CYPRESS

 		CYI9531ZXC PCIX I / O系统时钟发生器，带有EMI控制功能[ PCIX I/O System Clock Generator with EMI Control Features ] 10 页

CYPRESS

 		CYI9531ZXCT PCIX I / O系统时钟发生器，带有EMI控制功能[ PCIX I/O System Clock Generator with EMI Control Features ] 10 页

CYPRESS

 		CYIA2SC0300AA-BQE 1/3“ VGA格式CMOS图像传感器[ 1/3” VGA-Format CMOS Image Sensor ] 18 页

CYPRESS

 		CYIFS741BSXBT [ Clock Generator, 68MHz, CMOS, PDSO8, SOIC-8 ] 19 页

CYPRESS

 		CYIFS781BSXC 低EMI的扩频时钟[ Low EMI Spectrum Spread Clock ] 12 页

CYPRESS

 		CYIFS781BSXCT 低EMI的扩频时钟[ Low EMI Spectrum Spread Clock ] 12 页

购物指南

支付方式

配送服务

售后服务

发票须知

优惠券使用规则

特色服务

PCBA制造

国产品牌推荐

国产料号替代

质量保证

技术资料

行业资讯

关于我们

关于达普

联系我们

联系我们

服务热线：400-618-9990

企业邮箱：smail@ic72.com

服务时间：周一至周六 8:30-17:30

达普官方微信号

PDF索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

IC型号索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

Copyright 2024 gkzhan.com Al Rights Reserved 京ICP备06008810号-21 京

深圳网络警察报警平台
公共信息安全网络监察
经营性网站备案信息
不良信息举报中心
工商网监电子标识
全国公安机关备案
0.220436s