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CYU01M16ZFCU-70BVXI

型号：

CYU01M16ZFCU-70BVXI

描述：

16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ]

品牌：

CYPRESS[ CYPRESS ]

页数：

14 页

PDF大小：

509 K

下载PDF手册
CYU01M16ZFC  
MoBL3™  
PRELIMINARY  
16-Mbit (1M x 16) Pseudo Static RAM  
can be put into standby mode when deselected (CE HIGH or  
both BHE and BLE are HIGH). The input/output pins (I/O0  
through I/O15) are placed in a high-impedance state when:  
deselected (CE HIGH), outputs are disabled (OE HIGH), both  
Byte High Enable and Byte Low Enable are disabled (BHE,  
BLE HIGH), or during a write operation (CE LOW and WE  
LOW).  
Features  
• Wide voltage range: 1.7V–1.95V  
• Access Time: 70 ns  
• Ultra-low active power  
— Typical active current: 3 mA @ f = 1 MHz  
— Typical active current: 18 mA @ f = fmax  
• Ultra low standby power  
Writing to the device is accomplished by taking Chip Enable  
(CE LOW) and Write Enable (WE) input LOW. If Byte Low  
Enable (BLE) is LOW, then data from I/O pins (I/O0 through  
I/O7), is written into the location specified on the address pins  
(A0 through A19). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A19).  
• 16-word Page Mode  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Deep Sleep Mode  
Reading from the device is accomplished by taking Chip  
Enables (CE LOW) and Output Enable (OE) LOW while  
forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE)  
is LOW, then data from the memory location specified by the  
address pins will appear on I/O0 to I/O7. If Byte High Enable  
(BHE) is LOW, then data from memory will appear on I/O8 to  
I/O15. Refer to the truth table for a complete description of read  
• Offered in a Lead-Free 48-ball BGA Package  
• Operating Temperature: –40°C to +85°C  
Functional Description[1]  
The CYU01M16ZFC is a high-performance CMOS Pseudo  
Static RAM organized as 1M words by 16 bits that supports an  
asynchronous memory interface. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
and write modes.  
Deep Sleep Mode is enabled by driving ZZ LOW. See the Truth  
Table for a complete description of Read, Write, and Deep  
Sleep mode.  
Logic Block Diagram  
DATA IN DRIVERS  
A 8  
A 9  
A10  
A
A
A
11  
12  
13  
1M × 16  
RAM Array  
I/O0–I/O7  
A
A
A
A
A
14  
15  
16  
17  
18  
19  
I/O8–I/O15  
A
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Power-Down  
Circuit  
Refresh/Power-down  
ZZ  
BHE  
BLE  
Circuit  
CE  
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05604 Rev. *F  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised January 16, 2006  
CYU01M16ZFC  
MoBL3™  
PRELIMINARY  
Pin Configuration[2, 3]  
VFBGA  
Top View  
1
2
4
3
5
6
ZZ  
I/O  
A
A
2
A
OE  
BLE  
0
1
A
B
I/O BHE  
A
CE  
I/O  
A
0
8
4
3
I/O  
A
A
6
I/O I/O  
2
C
D
E
F
5
9
10  
1
A
V
VCC  
VSS  
I/O  
I/O  
3
A17  
NC  
SS  
7
11  
A
V
CC  
I/O  
I/O  
16  
12  
4
A
A
15  
I/O  
I/O  
5
I/O  
I/O  
14  
13  
14  
6
A
A
A
G
I/O  
WE  
I/O  
19  
13  
12  
15  
7
A
A
A
A
A
H
18  
10  
9
11  
NC  
8
Product Portfolio[4]  
Power Dissipation  
Operating ICC (mA)  
f = 1MHz f = fmax  
Speed  
(ns)  
Product  
VCC Range (V)  
Typ.[4]  
Standby ISB2 (µA)  
CYU01M16ZFC  
Min.  
Max.  
1.95  
Typ.[4]  
Max.  
Typ.[4]  
Max.  
Typ.[4]  
Max.  
1.7  
1.8  
70  
3
5
18  
25  
55  
70  
tied low) to reduce standby current. In this mode the PSRAM  
will only refresh certain portions of the memory in the Stand-By  
Mode, as configured by the user through the settings in the  
Variable Address Register.  
Low-Power Modes  
At power-up, all four sections of the die are activated and the  
PSRAM enters into its default state of full memory size and  
refresh space. This device provides four different Low-Power  
Modes.  
Once ZZ returns high in this mode, the PSRAM goes back to  
operating in full address refresh. Please refer to “Variable  
Address Space Register (VAR)” on page 4 for the protocol to  
turn off sections of the memory in Stand-By mode. If the VAR  
register is not updated after the power up, the PSRAM will be  
in its default state. In the default state the whole memory array  
will be refreshed in the Stand-By Mode. The 16-Mbit MoBL3 is  
divided into four 4-Mbit sections allowing certain sections to be  
active (i.e., refreshed).  
1. Reduced Memory Size Operation  
2. Partial Array Refresh  
3. Deep Sleep Mode  
4. Temperature Controlled Refresh  
Reduced Memory Size Operation  
In this mode, the 16 Mb PSRAM can be operated as a 12-Mbit,  
8-Mbit or a 4-Mbit memory block. Please refer to “Variable  
Address Space Register (VAR)” on page 4 for the protocol to  
turn on/off sections of the memory. The device remains in RMS  
mode until changes to the Variable Address Space register are  
made to revert back to a complete 16-Mbit PSRAM.  
Deep Sleep Mode  
In this mode, the data integrity in the PSRAM is not  
guaranteed. This mode can be used to lower the power  
consumption of the PSRAM in an application. This mode can  
be enabled and disabled through VAR similar to the RMS and  
PAR mode. Deep Sleep Mode is activated by driving ZZ LOW.  
The device stays in the deep sleep mode until ZZ is driven  
HIGH.  
Partial Array Refresh  
The Partial Array Refresh mode allows customers to turn off  
sections of the memory block in the Stand-by mode (with ZZ  
Notes:  
2. Ball H6, E3 can be used to upgrade to 32M and 64M density respectively.  
3. NC “no connect” - not connected internally to the die.  
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V  
, T = 25°C. Tested initially and  
A
CC  
CC(typ.)  
after any design changes that may affect the parameter.  
Document #: 38-05604 Rev. *F  
Page 2 of 14  
CYU01M16ZFC  
MoBL3™  
PRELIMINARY  
Variable Address Mode Register (VAR) Update[5, 6]  
t
WC  
ADDRESS  
CE  
Lower-order address (A0-A4) Low Power Modes  
t
t
AW  
HA  
t
BW  
BHE / BLE  
t
SA  
t
PWE  
WE  
ZZ  
t
ZZWE  
tZZMIN  
Deep Sleep Mode—Entry/Exit [7]  
tZZMIN  
ZZ  
Deep Sleep Mode  
t
t
R
CDR  
CE  
VAR Update and Deep Sleep Mode Timing[5, 6]  
Parameter  
Description  
Min.  
Max.  
Unit  
µs  
tZZWE  
tCDR  
ZZ LOW to Write Start  
1
Chip deselect to ZZ LOW  
0
200  
8
ns  
[7]  
tR  
Operation Recovery Time (Deep Sleep Mode only)  
Deep Sleep Mode Time  
µs  
tZZMIN  
µs  
Notes:  
5. OE and the data pins are in a don’t care state while the device is in variable address mode.  
6. All other timing parameters are as shown in the data sheets.  
7. t applies only in the deep sleep mode.  
R
Document #: 38-05604 Rev. *F  
Page 3 of 14  
CYU01M16ZFC  
MoBL3™  
PRELIMINARY  
I
Variable Address Space Register (VAR)  
A19–A5  
A4  
A3  
A2  
A1  
A0  
Memory Array Selection  
00 – 16M(Default)  
01 – 12M  
10 – 8M  
11 – 4M  
Top/Bottom Half Selection  
0 – Bottom (Default)  
1 – Top  
Reserved  
Array On/Off on ZZ  
0 – PAR Mode (Default)  
1 – RMS Mode  
ZZ Enable/Disable  
0 – Deep Sleep Enabled  
(Default)  
1 – Deep Sleep Disabled  
Variable Address Space—Address Patterns  
Partial Array Refresh Mode (A3 = 0, A4 = 1)  
Address  
A2 A1, A0  
Refresh Section  
1 1 1/4th of the array  
1 0 1/2th of the array  
Size  
Density  
4M  
0
0
0
1
1
1
00000h - 3FFFFh (A19 = A18 = 0)  
00000h - 7FFFFh (A19 = 0)  
256K x 16  
512K x 16  
768K x 16  
256K x 16  
512K x16  
786K x16  
8M  
0 1 3/4th of the array  
1 1 1/4th of the array  
1 0 1/2th of the array  
0 1 3/4th of the array  
00000h - BFFFFh (A19:A18 not equal to 1 1)  
C0000h - FFFFFh (A19 = A18= 1)  
80000h - FFFFFh (A19 = 1)  
12M  
4M  
8M  
40000h - FFFFFh (A19:A18 not equal to 0 0)  
Reduced Memory Size Mode (A3 = 1, A4 = 1)  
00000h - 3FFFFh (A19 = A18 = 0)  
00000h - 7FFFFh (A19 = 0)  
12M  
0
0
0
0
1
1
1
1
1 1 1/4th of the array  
1 0 1/2th of the array  
0 1 3/4th of the array  
0 0 Full array  
1 1 1/4th of the array  
1 0 1/2th of the array  
0 1 3/4 h of the array  
0 0 Full array  
256K x 16  
512K x 16  
768K x 16  
1M x 16  
4M  
8M  
00000h - BFFFFh (A19:A18 not equal to 1 1)  
00000h - FFFFFh (Default)  
12M  
16M  
4M  
C0000h - FFFFFh (A19 = A18 = 1)  
80000h - FFFFFh (A19 = 1)  
256K x 16  
512K x 16  
768K x 16  
1M x 16  
8M  
40000h - FFFFFh (A19:A18 not equal to 0 0)  
00000h - FFFFFh (Default)  
12M  
16M  
should be fixed. For a sixteen-word page mode all address  
bits, except for A3, A2, A1, and A0, should be fixed.  
Page Mode  
This device can be operated in a page read mode. This is  
accomplished by initiating a normal read of the device.  
The supported page lengths are four, eight, and sixteen words.  
Random page read is supported for all three four, eight, and  
sixteen-word page read options. Therefore, any address can  
be used as the starting address.  
In order to operate the device in page mode, the upper order  
address bits should be fixed for four-word page access  
operation, all address bits except for A1 and A0 should be  
fixed until the page access is completed. For an eight-word  
page access, all address bits, except for A2, A1, and A0,  
Please, refer to the table below for an overview of the page  
read modes.  
Page Mode Feature  
4-Word Mode  
8-Word Mode  
8 words  
16-Word Mode  
16 words  
Page Length  
4 words  
A1, A0  
Page Read Corresponding Addresses  
Page Read Start Address  
Page Direction  
A2, A1, A0  
Don't Care  
Don't Care  
A3, A2, A1, A0  
Don’t Care  
Don't Care  
Don't Care  
Don’t Care  
Document #: 38-05604 Rev. *F  
Page 4 of 14  
CYU01M16ZFC  
MoBL3™  
PRELIMINARY  
Power-up Characteristics  
The initialization sequence is shown in the figure below. Chip  
Select (CE) should be HIGH for at least 200 µs after VCC has  
reached a stable value. No access must be attempted during  
this period of 200 µs.The state of ZZ has to be high (H) for the  
duration of power-up.  
Stable Power  
VCC  
Logic (HIGH)  
ZZ  
First Access  
Tpu  
CE  
Parameter  
Description  
Min.  
Typ.  
Max.  
Unit  
Tpu  
Chip Enable Low After Stable VCC  
200  
µs  
Document #: 38-05604 Rev. *F  
Page 5 of 14  
CYU01M16ZFC  
MoBL3™  
PRELIMINARY  
DC Input Voltage[8, 9, 10] .................. –0.2V to VCCMAX + 0.3V  
Output Current into Outputs (LOW)............................. 20 mA  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature .................................–65°C to +150°C  
Latch-Up Current....................................................> 200 mA  
Ambient Temperature with  
Power Applied.............................................–55°C to +125°C  
Operating  
Temperature  
Supply Voltage to Ground Potential.–0.2V to VCCMAX + 0.3V  
Device  
Range  
(TA)  
VCC  
DC Voltage Applied to Outputs  
in High Z State[8, 9, 10] ......................–0.2V to VCCMAX + 0.3V  
CYU01M16ZFC Industrial –40°Cto+85°C 1.7V to 1.95V  
DC Electrical Characteristics Over the Operating Range [8, 9, 10]  
CYU01M16ZFC-70  
Parameter  
VCC  
Description  
Supply Voltage  
Test Conditions  
Min.  
1.7  
Typ.[4]  
Max.  
Unit  
V
1.8  
1.95  
VOH  
Output HIGH Voltage  
IOH = –0.1 mA  
CC= 1.7V to 1.95V  
VCC – 0.2  
V
V
VOL  
Output LOW Voltage  
IOL = 0.1 mA  
VCC= 1.7V to 1.95V  
0.2  
V
VIH  
VIL  
IIX  
Input HIGH Voltage  
Input LOW Voltage  
1.7V < VCC < 1.95  
VCC= 1.7V to 1.95V  
0.8 * VCC  
–0.2  
–1  
VCC + 0.3  
0.2 * VCC  
+1  
V
V
Input Leakage Current GND < VIN < VCC  
Output Leakage Current GND < VOUT < VCC  
µA  
µA  
mA  
IOZ  
ICC  
–1  
+1  
VCC Operating Supply  
Current  
f = fMAX  
1/tRC  
=
VCC= VCCmax  
IOUT = 0 mA  
CMOS levels  
18  
25  
f = 1 MHz  
3
5
mA  
ISB1  
CE > VCC – 0.2V,  
55  
70  
µA  
Automatic CE  
Power-Down  
Current —  
VI > VCC – 0.2V, VIN < 0.2V  
f = fMAX (Address and Data Only),  
f = 0 (OE, WE, BHE and BLE),  
VCC = 1.95V, ZZ >= VCC – 0.2V  
CMOS Inputs  
ISB2  
Automatic  
Power-Down  
Current —  
55  
70  
10  
µA  
µA  
CE  
CE > VCC – 0.2V, VIN > VCC – 0.2V  
or VIN < 0.2V, f = 0, VCC = VCCMAX  
ZZ>= VCC – 0.2V  
CMOS Inputs  
IZZ  
Deep Sleep Current  
VCC = VCCMAX, ZZ < 0.2V,  
CE = HIGH or BHE and BLE = HIGH  
Capacitance[11]  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
TA = 25°C, f = 1 MHz,  
VCC = VCC(typ)  
Max.  
Unit  
pF  
CIN  
8
8
COUT  
pF  
Notes:  
8. V  
9. V  
= –0.5V for pulse durations less than 20 ns.  
IL(MIN)  
IH(Max)  
= V + 0.5V for pulse durations less than 20 ns.  
CC  
10. Overshoot and undershoot specifications are characterized and are not 100% tested.  
11. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05604 Rev. *F  
Page 6 of 14  
CYU01M16ZFC  
MoBL3™  
PRELIMINARY  
Thermal Resistance[11]  
Parameter  
Description  
Test Conditions  
VFBGA  
Unit  
ΘJA  
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard test methods and  
procedures for measuring thermal impedence, per  
EIA / JESD51.  
56  
°C/W  
ΘJC  
Thermal Resistance  
(Junction to Case)  
11  
°C/W  
AC Test Loads and Waveforms  
R1  
ALL INPUT PULSES  
VCC  
90%  
90%  
VCC  
OUTPUT  
10%  
10%  
Fall Time = 1 V/ns  
GND  
R2  
30 pF  
Rise Time = 1 V/ns  
Equivalent to:  
INCLUDING  
JIG AND  
SCOPE  
THEVENIN EQUIVALENT  
RTH  
OUTPUT  
VTH  
Parameters  
1.8V (VCC  
14000  
14000  
7000  
)
Unit  
Ω
R1  
R2  
Ω
RTH  
VTH  
Ω
0.90  
V
Document #: 38-05604 Rev. *F  
Page 7 of 14  
CYU01M16ZFC  
MoBL3™  
PRELIMINARY  
Switching Characteristics Over the Operating Range[12, 13, 14, 15, 18]  
70 ns  
Parameter  
Read Cycle  
Description  
Min.  
Max.  
Unit  
[17]  
tRC  
tCD  
Read Cycle Time  
70  
15  
40000  
70  
ns  
ns  
Chip Deselect Time  
CE, BLE/BHE High Pulse Time  
tAA  
Address to Data Valid  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tOHA  
Data Hold from Address Change  
CE LOW to Data Valid  
5
tACE  
70  
35  
tDOE  
OE LOW to Data Valid  
tLZOE  
OE LOW to Low Z[13, 14, 16]  
OE HIGH to High Z[13, 14, 16]  
CE LOW to Low Z[13, 14, 16]  
CE HIGH to High Z[13, 14, 16]  
BLE/BHE LOW to Data Valid  
BLE/BHE LOW to Low Z[13, 14, 16]  
BLE/BHE HIGH to High Z[13, 14, 16]  
5
tHZOE  
25  
tLZCE  
10  
tHZCE  
25  
70  
tDBE  
tLZBE  
5
tHZBE  
25  
Page Read Cycle  
tPC  
Page Mode Read Cycle Time  
Page Mode Address Access  
35  
40000  
35  
ns  
ns  
tPA  
Write Cycle[15]  
tWC  
tSCE  
tCD  
Write Cycle Time  
70  
60  
15  
40000  
ns  
ns  
ns  
CE LOW to Write End  
Chip Deselect Time  
CE, BLE/BHE High Pulse Time  
tAW  
tHA  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
60  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSA  
0
tPWE  
tBW  
tSD  
50  
60  
25  
0
BLE/BHE LOW to Write End  
Data Set-Up to Write End  
Data Hold from Write End  
WE LOW to High-Z[13, 14, 16]  
WE HIGH to Low-Z[13, 14, 16]  
tHD  
tHZWE  
25  
tLZWE  
10  
Notes:  
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of V /2, input pulse levels of  
CC  
0V to V , and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.  
CC  
OL OH  
13. At any given temperature and voltage conditions t  
is less than t  
, t  
is less than t  
, t  
is less than t  
, and t  
is less than t  
for any  
LZWE  
HZCE  
LZCE HZBE  
LZBE HZOE  
LZOE  
HZWE  
given device. All low-Z parameters will be measured with a load capacitance of 30 pF (1.8V)  
14. t , t , t , and t transitions are measured when the outputs enter a high-impedance state.  
HZOE HZCE HZBE  
HZWE  
15. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any  
IL  
IL  
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates  
the write.  
16. High-Z and Low-Z parameters are characterized and are not 100% tested.  
17. If invalid address signals shorter than min. t are continuously repeated for 40 µs, the device needs a normal read timing (t ) or needs to enter standby state  
RC  
RC  
at least once in every 40 µs.  
18. In order to achieve 70ns performance, the read access must be CE controlled. That is, the addresses must be stable prior to CE going active.  
Document #: 38-05604 Rev. *F  
Page 8 of 14  
CYU01M16ZFC  
MoBL3™  
PRELIMINARY  
Switching Waveforms  
Read Cycle 1 (Address Transition Controlled)[20, 21]  
tRC  
ADDRESS  
tAA  
tOHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Read Cycle 2 (OE Controlled)[19, 21]  
ADDRESS  
tRC  
CE  
tCD  
tHZCE  
tACE  
BHE/BLE  
tDBE  
tHZBE  
tLZBE  
OE  
tHZOE  
tDOE  
tLZOE  
HIGH IMPEDANCE  
HIGH  
IMPEDANCE  
DATA OUT  
DATA VALID  
tLZCE  
ICC  
ISB  
V
CC  
50%  
50%  
SUPPLY  
CURRENT  
Notes:  
19. Whenever CE, BHE/BLE are taken inactive, they must remain inactive for a minimum of 15 ns  
20. Device is continuously selected. OE, CE = V  
21. WE is HIGH for Read Cycle.  
.
IL  
Document #: 38-05604 Rev. *F  
Page 9 of 14  
CYU01M16ZFC  
MoBL3™  
PRELIMINARY  
Switching Waveforms (continued)  
Page Read Cycle (ZZ = WE = VIH, 16 word access)[17, 21]  
t
RC  
A4-A19  
t
OHA  
t
AA  
A0-A3  
CE  
t
PC  
t
ACE  
t
HZBE  
t
DOE  
OE  
t
HZCE  
BHE/BLE  
t
DBE  
t
PAA  
t
LZCE  
DATA VALID  
DATA VALI
DATA OUT  
DATA VALID  
DATA VALID  
ATA VALID  
DATA VALID  
DATA VALID  
DATA VALID  
High Z  
Write Cycle 1 (WE Controlled)[15, 16, 19, 22, 23]  
tWC  
ADDRESS  
tSCE  
CE  
tCD  
tAW  
tHA  
tSA  
tPWE  
WE  
tBW  
BHE/BLE  
OE  
tSD  
VALID DATA  
tHD  
DATA I/O  
DON’T CARE  
tHZOE  
Notes:  
22. Data I/O is high-impedance if OE > V  
.
IH  
23. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.  
Document #: 38-05604 Rev. *F  
Page 10 of 14  
CYU01M16ZFC  
MoBL3™  
PRELIMINARY  
Switching Waveforms (continued)  
Write Cycle 2 (CE Controlled)[15, 16, 19, 22, 23]  
t WC  
ADDRESS  
CE  
tSCE  
t
SA  
tHA  
tAW  
tPWE  
WE  
tBW  
BHE/BLE  
OE  
tSD  
VALID DATA  
tHZOE  
tHD  
DATA I/O  
DON’T CARE  
Write Cycle 3 (WE Controlled, OE LOW)[ 19, 23]  
tWC  
ADDRESS  
CE  
tSCE  
tBW  
tAW  
BHE/BLE  
tHA  
tSA  
tPWE  
WE  
tSD  
VALID DATA  
tHD  
DON’T CARE  
DATA I/O  
tLZWE  
tHZWE  
Document #: 38-05604 Rev. *F  
Page 11 of 14  
CYU01M16ZFC  
MoBL3™  
PRELIMINARY  
Switching Waveforms (continued)  
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[15, 19, 22, 23]  
tWC  
ADDRESS  
CE  
tSCE  
tAW  
tHA  
tBW  
BHE/BLE  
tSA  
tPWE  
WE  
tSD  
tHD  
DON’T CARE  
VALID DATA  
DATA I/O  
Truth Table[24, 25]  
ZZ  
H
CE  
H
X
WE  
X
OE  
X
BHE BLE  
Inputs/Outputs  
Mode  
Power  
X
H
H
L
X
H
H
L
High Z  
Deselect/Power-down  
Deselect/Power-down  
Deselect/Power-down  
Read  
Standby (ISB  
Standby (ISB  
Standby (ISB  
)
)
)
H
X
X
High Z  
H
L
X
X
High Z  
H
L
H
L
Data Out (I/O0–I/O15  
)
Active (ICC  
)
)
H
L
H
L
H
L
Data Out (I/O0–I/O7);  
I/O8–I/O15 in High Z  
Read  
Active (ICC  
H
L
H
L
L
H
Data Out (I/O8–I/O15);  
I/O0–I/O7 in High Z  
Read  
Active (ICC  
)
H
H
H
H
L
L
L
L
H
H
H
L
H
H
H
X
L
H
L
L
L
High Z  
High Z  
High Z  
Output Disabled  
Output Disabled  
Output Disabled  
Active (ICC  
Active (ICC  
Active (ICC  
)
)
)
)
H
L
L
Data In (I/O0–I/O15  
)
Write (Upper Byte and Lower Active (ICC  
Byte)  
H
H
L
L
L
L
L
X
X
X
X
H
L
L
H
H
X
Data In (I/O0–I/O7);  
I/O8–I/O15 in High Z  
Write (Lower Byte Only)  
Active (ICC  
)
)
)
Data In (I/O8–I/O15);  
I/O0 –I/O7 in High Z  
Write (Upper Byte Only)  
Active (ICC  
H
H
X
X
H
X
Data in (A0–A4)  
Write (Variable Address Mode Active (ICC  
Register)  
L
High Z  
Deep Power-down / PAR  
Deep Sleep (IZZ) /  
Stand by  
Notes:  
24. H = Logic HIGH, L = Logic LOW, X = Don’t Care.  
25. During ZZ = L and CE = H, Mode depends on how the VAR is set up either in PAR or Deep Sleep Modes.  
Document #: 38-05604 Rev. *F  
Page 12 of 14  
CYU01M16ZFC  
MoBL3™  
PRELIMINARY  
Ordering Information  
Speed  
Package  
Name  
Operating  
Range  
(ns)  
Ordering Code  
CYU01M16ZFCU-70BVXI  
Package Type  
70  
BV48  
48-ball Fine Pitch VFBGA (6 mm × 8 mm × 1 mm) Lead-Free Industrial  
Please contact your local Cypress Sales representative for availability of other parts.  
Package Diagram  
48-Lead VFBGA (6 x 8 x 1 mm) BV48  
BOTTOM VIEW  
A1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
A1 CORNER  
Ø0.30 0.05ꢀ(48X  
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475  
A
A
0.75  
B
6.00 0.10  
3.75  
B
6.00 0.10  
0.15ꢀ(8X  
51-85150-*D  
SEATING PLANE  
C
MoBL is a registered trademark and MoBL3 and More Battery Life are trademarks of Cypress Semiconductor Corporation. All  
product and company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-05604 Rev. *F  
Page 13 of 14  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CYU01M16ZFC  
MoBL3™  
PRELIMINARY  
Document History Page  
Document Title: CYU01M16ZFC MoBL3™ 16-Mbit (1M x 16) Pseudo Static RAM  
Document Number: 38-05604  
Issue  
Date  
Orig. of  
Change  
REV.  
**  
ECN NO.  
278869  
280850  
314034  
Description of Change  
See ECN  
See ECN  
See ECN  
SYT  
REF  
PCI  
New Data Sheet  
*A  
Updated Ordering information to incorporate lead-free parts.  
*B  
Corrected Part Number  
Added Operating Range in Features Section  
Moved address lines A8 - A10 from Column decoder to Row decoder in the  
Logic Block Diagram  
Changed Pin Configuration Diagram Name from FBGA to VFBGA  
Added pin E3 in note #2  
Modified description on Deep Sleep Mode  
Changed tZZWE description  
Changed ΘJA and ΘJC from 55 and 17 °C/W to 56 and 11°C/W respectively  
Modified Test Condition for IIX and IOZ  
Changed VCC(typ) to VCC in note # 12  
Changed tOHA from 10 ns to 5 ns  
Changed tSCE, tAW and tBW from 45 to 50 ns  
Changed tRC and tWC from 6000 ns to 40000 ns  
Changed tPC and tPA from 15 ns to 20 ns  
Added Parameter tCD in AC Table and its corresponding footnote in Notes  
Section  
Changed R1 and R2 from 13500 and 10800 Ω to 14000 Ω  
Changed RTH from 6000 to 7000 Ω  
Parameter tCD added in Read Cycle 2 and Write Cycle 1 Timing Diagrams  
Changed from Advance Information to Preliminary  
*C  
351780  
See ECN  
PCI  
Modified Logic Block Diagram  
Modified description on Deep Sleep Mode  
Deleted Page Write in the Page Mode Feature Table  
Added CE, BHE and BLE in test conditions for IZZ in DC Table  
Modified condition in the third row of the Truth Table for ZZ Pin from X to H  
*D  
*E  
386551  
406266  
See ECN  
See ECN  
PCI  
Changed tPC and tPA from 20 to 25 ns  
Replaced TBDs with appropriate values  
NXR  
Changed address of Cypress Semiconductor Corporation on Page# 1 from  
“3901 North First Street” to “198 Champion Court”  
Removed 55 ns Speed Bin.  
Removed Reference to BHE/ BLE from DPD wave form on page # 3.  
Added ZZ in Power Up characteristics on page# 5.  
Added ISB1 specification in the DC characteristics table on page #6.  
Added test condition ZZ>= VCC-0.2V for ISB2  
Updated the Truth Table for DPD / PAR and Write (Variable Address Mode  
Register) Modes.  
*F  
420604  
See ECN  
HRT  
Changed TCD value to 15 ns from 5 ns on Read and Write Cycles  
Changed TPC and TPAA values to 35 ns from 25 ns  
Included “Chip Enable Access” footnote in AC Parameters  
Changed Isb2 value from 60µA to 70µA  
Document #: 38-05604 Rev. *F  
Page 14 of 14  
厂商 型号 描述 页数 下载

CYPRESS

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CYPRESS

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CYPRESS

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CYPRESS

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CYPRESS

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 		CYU01M16SFCU-70BVXI 16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ] 12 页

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