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CYU01M16SCCU-70BVXI

型号：

CYU01M16SCCU-70BVXI

描述：

16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ]

品牌：

CYPRESS[ CYPRESS ]

页数：

12 页

PDF大小：

453 K

下载PDF手册
CYU01M16SCCU  
MoBL3™  
PRELIMINARY  
16-Mbit (1M x 16) Pseudo Static RAM  
portable applications such as cellular telephones. The device  
can be put into standby mode when deselected (CE1 HIGH or  
CE2 LOW or both BHE and BLE are HIGH). The input/output  
pins (I/O0 through I/O15) are placed in a high-impedance state  
when: deselected (CE1 HIGH or CE2 LOW), outputs are  
disabled (OE HIGH), both Byte High Enable and Byte Low  
Enable are disabled (BHE, BLE HIGH), or during a write  
operation (CE1 LOW and CE2 HIGH and WE LOW).  
Features  
• Wide voltage range: 2.2V–3.6V  
• Access Time: 70 ns  
• Ultra-low active power  
— Typical active current: 3 mA @ f = 1 MHz  
— Typical active current: 18 mA @ f = fmax  
• Ultra low standby power  
Writing to the device is accomplished by taking Chip Enable  
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW.  
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0  
through I/O7), is written into the location specified on the  
address pins (A0 through A19). If Byte High Enable (BHE) is  
LOW, then data from I/O pins (I/O8 through I/O15) is written into  
the location specified on the address pins (A0 through A19).  
• 16-word Page Mode  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Offered in a 48-ball BGA Package  
• Operating Temperature: –40°C to +85°C  
Reading from the device is accomplished by taking Chip  
Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE)  
LOW while forcing the Write Enable (WE) HIGH. If Byte Low  
Enable (BLE) is LOW, then data from the memory location  
Functional Description[1]  
The CYU01M16SCCU is a high-performance CMOS Pseudo  
Static RAM organized as 1M words by 16 bits that supports an  
asynchronous memory interface. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
specified by the address pins will appear on I/O0 to I/O7. If Byte  
High Enable (BHE) is LOW, then data from memory will appear  
on I/O8 to I/O15. Refer to the truth table for a complete  
description of read and write modes.  
Logic Block Diagram  
DATA IN DRIVERS  
A
8
9
A
A
A
A
A
10  
11  
12  
13  
14  
1M x 16  
RAM Array  
I/O –I/O  
0
7
A
A
A
A
15  
16  
17  
18  
I/O –I/O  
8
15  
A
A
19  
COLUMN DECODER  
BHE  
WE  
CE  
2
CE  
1
OE  
BLE  
CE  
CE  
2
Power -Down  
Circuit  
1
BHE  
BLE  
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05601 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised January 25, 2006  
CYU01M16SCCU  
MoBL3™  
PRELIMINARY  
Pin Configuration[2, 3]  
48-Ball VFBGA  
Top View  
1
4
2
5
3
6
A
A
A
2
CE2  
OE  
BLE  
0
1
A
B
I/O BHE  
CE1 I/O  
A
A
4
0
8
3
I/O  
A
A
6
I/O  
I/O  
I/O  
2
C
D
E
F
5
9
10  
1
A
V
SS  
VCC  
VSS  
I/O  
I/O  
3
A17  
NC  
7
11  
A
V
CC  
I/O  
I/O  
16  
12  
4
A
A
15  
I/O  
I/O  
I/O  
I/O  
14  
13  
5
14  
6
A
A
A
G
I/O  
WE  
I/O  
19  
13  
12  
15  
7
A
A
A
A
A
H
18  
10  
9
11  
NC  
8
Product Portfolio[4]  
Power Dissipation  
Operating ICC (mA)  
f = 1MHz f = fmax Standby ISB2 (µA)  
Speed  
(ns)  
Product  
VCC Range (V)  
Typ.[4]  
CYU01M16SCCU  
Min.  
2.2  
Max.  
Typ.[4]  
Max.  
Typ.[4]  
Max.  
Typ.[4]  
Max.  
3.0  
3.6  
70  
3
5
18  
25  
55  
70  
Power-up Characteristics  
The initialization sequence is shown in the figure below. Chip  
Select should be CE1 HIGH or CE2 LOW for at least 200 µs  
after VCC has reached a stable value. No access must be  
attempted during this period of 200 µs.  
Stable Power  
VCC  
CE  
First Access  
Tpu  
Parameter  
Description  
Min.  
200  
Typ.  
Max.  
Unit  
µs  
Tpu  
Chip Enable Low After Stable VCC  
Notes:  
2. Ball H6 and E3 can be used to upgrade to a 32-Mbit and a 64-Mbit density, respectively.  
3. NC “no connect” - not connected internally to the die.  
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V (typ) and T = 25°C. Tested initially  
CC  
CC  
A
and after design changes that may affect the parameters.  
Document #: 38-05601 Rev. *B  
Page 2 of 12  
CYU01M16SCCU  
MoBL3™  
PRELIMINARY  
should be fixed. For a sixteen-word page mode all address  
bits, except for A3, A2, A1, and A0, should be fixed.  
Page Mode  
This device can be operated in a page read mode. This is  
accomplished by initiating a normal read of the device.  
The supported page lengths are four, eight, and sixteen words.  
Random page read is supported for all three four, eight, and  
sixteen-word page read options. Therefore, any address can  
be used as the starting address.  
In order to operate the device in page mode, the upper order  
address bits should be fixed for four-word page access  
operation, all address bits except for A1 and A0 should be  
fixed until the page access is completed. For an eight-word  
page access, all address bits, except for A2, A1, and A0,  
Please refer to the table below for an overview of the page  
read modes.  
Page Mode Feature  
4-Word Mode  
8-Word Mode  
8 words  
16-Word Mode  
16 words  
Page Length  
4 words  
A1, A0  
Page Read Corresponding Addresses  
Page Read Start Address  
Page Direction  
A2, A1, A0  
Don't Care  
Don't Care  
A3, A2, A1, A0  
Don’t Care  
Don't Care  
Don't Care  
Don’t Care  
Document #: 38-05601 Rev. *B  
Page 3 of 12  
CYU01M16SCCU  
MoBL3™  
PRELIMINARY  
DC Input Voltage[5, 6, 7].................... –0.3V to VCCMAX + 0.3V  
Output Current into Outputs (LOW)............................. 20 mA  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature .................................–65°C to +150°C  
Latch-Up Current....................................................> 200 mA  
Ambient Temperature with  
Power Applied.............................................–55°C to +125°C  
Operating  
Range Temperature (TA)  
Device  
VCC  
Supply Voltage to  
Ground Potential..............................–0.3V to VCCMAX + 0.3V  
CYU01M16SCCU Industrial –40°C to +85°C  
2.2V to  
3.6V  
DC Voltage Applied to Outputs  
in High Z State[5, 6, 7]........................–0.3V to VCCMAX + 0.3V  
DC Electrical Characteristics (Over the Operating Range)[5, 6, 7]  
CYU01M16SCCU-70 ns  
Parameter  
VCC  
Description  
Test Conditions  
Min.  
Typ.[4]  
Max.  
Unit  
V
Supply Voltage  
2.2  
3.0  
3.6  
VOH  
Output HIGH Voltage IOH = –0.1 mA  
VCC= 2.2V to 3.6V  
VCC – 0.2  
V
VOL  
Output LOW Voltage IOL = 0.1 mA  
0.2  
V
VCC= 2.2V to 3.6V  
VIH  
VIL  
IIX  
Input HIGH Voltage VCC= 2.2V to 3.6V  
Input LOW Voltage VCC= 2.2V to 3.6V  
0.8 * VCC  
–0.3  
VCC + 0.3V  
0.2 * VCC  
+1  
V
V
Input Leakage  
Current  
GND < VIN < VCC  
–1  
µA  
IOZ  
ICC  
Output Leakage  
Current  
GND < VOUT < VCC  
–1  
+1  
25  
µA  
VCC Operating  
Supply  
f = fMAX = 1/tRC VCC= VCCmax  
IOUT = 0 mA  
18  
mA  
Current  
CMOS levels  
f = 1MHz  
3
5
mA  
ISB1  
Automatic CE  
Power-Down  
Current — CMOS  
Inputs  
CE1 > VCC – 0.2V, CE2 < 0.2V, VIN> VCC  
– 0.2V, VIN < 0.2V f = fMAX (Address and  
Data Only), f = 0  
55  
70  
µA  
(OE, WE, BHE and BLE), VCC = 3.60V  
ISB2  
Automatic CE  
Power-Down  
Current — CMOS  
Inputs  
CE1 > VCC – 0.2V, CE2 < 0.2V,  
VIN > VCC – 0.2V or  
55  
70  
µA  
VIN < 0.2V,  
f = 0, VCC=VCCMAX  
Capacitance[8]  
Parameter  
Description  
Test Conditions  
TA = 25°C, f = 1 MHz,  
CC = VCC(typ)  
Max.  
Unit  
CIN  
Input Capacitance  
Output Capacitance  
8
8
pF  
pF  
V
COUT  
Thermal Resistance[8]  
Parameter  
Description  
Test Conditions  
VFBGA  
56  
Unit  
ΘJA  
ΘJC  
Thermal Resistance (Junction to Ambient) Testconditionsfollowstandardtestmethods  
°C/W  
°C/W  
and procedures for measuring thermal  
impedence, per EIA / JESD51.  
Thermal Resistance (Junction to Case)  
11  
Notes:  
5. V  
6. V  
= –0.5V for pulse durations less than 20 ns.  
IL(MIN)  
= V + 0.5V for pulse durations less than 20 ns.  
IH(Max)  
CC  
7. Overshoot and undershoot specifications are characterized and are not 100% tested.  
8. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05601 Rev. *B  
Page 4 of 12  
CYU01M16SCCU  
MoBL3™  
PRELIMINARY  
AC Test Loads and Waveforms  
R1  
ALL INPUT PULSES  
90%  
10%  
VCC  
OUTPUT  
VCC  
GND  
90%  
10%  
Fall Time = 1 V/ns  
R2  
30 pF  
Rise Time = 1 V/ns  
Equivalent to:  
INCLUDING  
JIG AND  
SCOPE  
THEVENIN EQUIVALENT  
RTH  
OUTPUT  
VTH  
Parameters  
3.0V (VCC  
)
Unit  
Ω
R1  
R2  
26000  
26000  
13000  
1.50  
Ω
RTH  
VTH  
Ω
V
Switching Characteristics Over the Operating Range[9, 10, 11, 15,14]  
70 ns  
Parameter  
Description  
Min.  
Max.  
Unit  
Read Cycle  
[13]  
tRC  
Read Cycle Time  
70  
15  
40000  
ns  
ns  
tCD  
Chip Deselect Time CE1 = HIGH or  
CE2 =LOW, BLE/BHE High Pulse Time  
tAA  
Address to Data Valid  
70  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tOHA  
tACE  
Data Hold from Address Change  
CE LOW to Data Valid  
5
70  
35  
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tDBE  
tLZBE  
tHZBE  
OE LOW to Data Valid  
OE LOW to Low Z[10, 11, 12]  
OE HIGH to High Z[10, 11, 12]  
CE LOW to Low Z[10, 11, 12]  
CE HIGH to High Z[10, 11, 12]  
BLE/BHE LOW to Data Valid  
BLE/BHE LOW to Low Z[10, 11, 12]  
BLE/BHE HIGH to High Z[10, 11, 12]  
5
25  
10  
25  
70  
5
25  
Page Read Cycle  
tPC  
Page Mode Read Cycle Time  
Page Mode Address Access  
35  
40000  
35  
ns  
ns  
tPA  
Notes:  
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of V  
/2, input pulse levels  
CC(typ.)  
of 0V to V , and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.  
CC  
OL OH  
10. At any given temperature and voltage conditions t  
is less than t  
, t  
is less than t  
, t  
is less than t  
, and t  
is less than t  
for any  
LZWE  
HZCE  
LZCE HZBE  
LZBE HZOE  
LZOE  
HZWE  
given device. All low-Z parameters will be measured with a load capacitance of 30 pF (3V)  
11. t  
, t  
, t  
, and t  
transitions are measured when the outputs enter a high -impedence state.  
HZOE HZCE HZBE  
HZWE  
12. High-Z and Low-Z parameters are characterized and are not 100% tested.  
13. If invalid address signals shorter than min.tRC are continuously repeated for 40 µs, the device needs a normal read timing (t ) or needs to enter standby state  
RC  
at least once in every 40 µs.  
14. In order to achieve 70-ns performance, the read access must be Chip Enable (CE or CE ) controlled. That is, the addresses must be stable prior to Chip Enable  
1
2
going active.  
Document #: 38-05601 Rev. *B  
Page 5 of 12  
CYU01M16SCCU  
MoBL3™  
PRELIMINARY  
Switching Characteristics Over the Operating Range[9, 10, 11, 15,14] (continued)  
70 ns  
Parameter  
Description  
Min.  
Max.  
Unit  
Write Cycle[15]  
tWC  
tSCE  
tAW  
tCD  
Write Cycle Time  
70  
60  
60  
15  
40000  
ns  
ns  
ns  
ns  
CE LOW to Write End  
Address Set-Up to Write End  
Chip Deselect Time CE1 = HIGH or  
CE2 =LOW, BLE/BHE High Pulse Time  
tHA  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
0
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSA  
tPWE  
tBW  
tSD  
50  
60  
25  
0
BLE/BHE LOW to Write End  
Data Set-Up to Write End  
Data Hold from Write End  
WE LOW to High-Z[10, 11, 12]  
WE HIGH to Low-Z[10, 11, 12]  
tHD  
tHZWE  
25  
tLZWE  
10  
Note:  
15. The internal Write time of the memory is defined by the overlap of WE,CE = V or CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a  
1
IL  
2
IH  
IL  
write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal  
that terminates the write  
Document #: 38-05601 Rev. *B  
Page 6 of 12  
CYU01M16SCCU  
MoBL3™  
PRELIMINARY  
Switching Waveforms  
Read Cycle 1 (Address Transition Controlled)[17, 18]  
tRC  
ADDRESS  
tAA  
tOHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Read Cycle 2 (OE Controlled)[16, 18, 19]  
ADDRESS  
tRC  
CE1  
tCD  
tHZCE  
CE2  
tACE  
BHE/BLE  
tDBE  
IMPEDANCE  
HIGH  
tHZBE  
tLZBE  
OE  
tHZOE  
tDOE  
tLZOE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
tLZCE  
ICC  
ISB  
V
CC  
50%  
50%  
SUPPLY  
CURRENT  
Notes:  
16. Whenever CE = HIGH or CE = LOW, BHE/BLE are taken inactive, they must remain inactive for a minimum of 5 ns.  
1
2
17. Device is continuously selected. OE = CE = V and CE = V .  
1
IL  
2
IH  
18. WE is HIGH for Read Cycle.  
19. CE is the Logical AND of CE and CE .  
1
2
Document #: 38-05601 Rev. *B  
Page 7 of 12  
CYU01M16SCCU  
MoBL3™  
PRELIMINARY  
Switching Waveforms (continued)  
Page Read Cycle (WE = VIH, 16 word access)[13, 18, 19]  
t
RC  
A4-A19  
t
OHA  
t
AA  
A0-A3  
CE  
t
t
1
ACE  
PC  
CE2  
OE  
t
HZBE  
t
DOE  
t
HZCE  
BHE/BLE  
t
DBE  
t
PAA  
t
LZCE  
DATA VALID  
DATA VALID  
DATA VALI
DATA OUT  
DATA VALID  
DATA VALID  
DATA VALID  
DATA VALID  
DATA VALID  
High Z  
Write Cycle 1 (WE Controlled)[15, 12, 16, 19, 20, 21]  
tWC  
ADDRESS  
tSCE  
CE1  
tCD  
CE2  
tAW  
tHA  
tSA  
tPWE  
WE  
tBW  
BHE/BLE  
OE  
tSD  
VALID DATA  
tHD  
DATA I/O  
DON’T CARE  
tHZOE  
Notes:  
20. Data I/O is high-impedance if OE > V  
.
IH  
21. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.  
Document #: 38-05601 Rev. *B  
Page 8 of 12  
CYU01M16SCCU  
MoBL3™  
PRELIMINARY  
Switching Waveforms (continued)  
Write Cycle 2 (CE1 or CE2 Controlled)[15, 12, 16, 20, 21]  
tWC  
ADDRESS  
CE1  
tSCE  
CE2  
tSA  
tAW  
tHA  
tPWE  
WE  
tBW  
BHE/BLE  
OE  
tSD  
VALID DATA  
tHD  
DATA I/O  
DON’T CARE  
tHZOE  
Write Cycle 3 (WE Controlled, OE LOW)[16, 21]  
tWC  
ADDRESS  
CE1  
tSCE  
CE2  
tBW  
BHE/BLE  
tAW  
tHA  
tSA  
tPWE  
WE  
t
HD  
tSD  
VALID DATA  
DON’T CARE  
DATAI/O  
tLZWE  
tHZWE  
Document #: 38-05601 Rev. *B  
Page 9 of 12  
CYU01M16SCCU  
MoBL3™  
PRELIMINARY  
Switching Waveforms (continued)  
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[15, 16, 20, 21]  
tWC  
ADDRESS  
CE1  
CE2  
tSCE  
tAW  
tHA  
tBW  
BHE/BLE  
WE  
tSA  
tPWE  
tSD  
tHD  
DON’T CARE  
DATA I/O  
VALID DATA  
Truth Table[22]  
CE1  
H
CE2  
X
WE  
X
OE  
X
BHE BLE  
Inputs/Outputs  
High Z  
Mode  
Power  
Standby (ISB  
Standby (ISB  
Standby (ISB  
Active (ICC  
Active (ICC  
X
X
H
L
X
X
H
L
Deselect/Power-down  
Deselect/Power-down  
Deselect/Power-down  
Read  
)
X
L
X
X
High Z  
)
X
X
X
X
High Z  
)
L
H
H
L
Data Out (I/O0–I/O15  
)
)
L
H
H
L
H
L
Data Out (I/O0–I/O7);  
I/O8–I/O15 in High Z  
Read  
)
L
H
H
L
L
H
Data Out (I/O8–I/O15);  
I/O0–I/O7 in High Z  
Read  
Active (ICC)  
L
L
L
L
H
H
H
H
H
H
H
L
H
H
H
X
L
H
L
L
L
High Z  
High Z  
High Z  
Output Disabled  
Output Disabled  
Output Disabled  
Active (ICC  
Active (ICC  
Active (ICC  
)
)
H
L
)
L
Data In (I/O0–I/O15  
)
Write (Upper Byte and Lower Active (ICC)  
Byte)  
L
L
H
H
L
L
X
X
H
L
L
Data In (I/O0–I/O7);  
I/O8–I/O15 in High Z  
Write (Lower Byte Only)  
Active (ICC  
)
H
Data In (I/O8–I/O15);  
I/O0 –I/O7 in High Z  
Write (Upper Byte Only)  
Active (ICC)  
Note:  
22. H = Logic HIGH, L = Logic LOW, X = Don’t Care.  
Document #: 38-05601 Rev. *B  
Page 10 of 12  
CYU01M16SCCU  
MoBL3™  
PRELIMINARY  
Ordering Information  
Speed  
Package  
Name  
Operating  
Range  
(ns)  
Ordering Code  
CYU01M16SCCU-70BVXI  
Package Type  
48-ball Fine Pitch VBGA (6 mm × 8 mm × 1 mm) (Pb-Free)  
70  
BV48  
Industrial  
Package Diagram  
48-ball VFBGA (6 x 8 x 1 mm) BV48  
BOTTOM VIEW  
A1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
A1 CORNER  
Ø0.30 0.05ꢀ(48X  
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475  
A
A
0.75  
B
6.00 0.10  
3.75  
B
6.00 0.10  
0.15ꢀ(8X  
51-85150-*D  
SEATING PLANE  
C
MoBL is a registered trademark and MoBL3 and More Battery Life are trademarks of Cypress Semiconductor Corporation. All  
product and company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-05601 Rev. *B  
Page 11 of 12  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CYU01M16SCCU  
MoBL3™  
PRELIMINARY  
Document History Page  
Document Title: CYU01M16SCCU MoBL3™ 16-Mbit (1M x 16) Pseudo Static RAM  
Document Number: 38-05601  
Orig. of  
REV.  
**  
ECN NO. Issue Date Change  
Description of Change  
342199  
386551  
See ECN  
See ECN  
PCI  
PCI  
New Datasheet  
*A  
Changed from Advance to Preliminary  
Replaced TBDs with appropriate values  
Changed tPC and tPA from 20 to 25 ns  
Corrected footnote # 16 as OE = CE1 = VIL and CE2 = VIH  
Added separate waveforms for CE1 and CE2 in Read # 2, Page Read and  
Write # 1 Timing diagram  
*B  
422623  
See ECN  
HRT  
Removed the 55-ns Speed Bin  
Changed Isb2 Max value from 60 µA to 70 µA  
Added Isb1 to DC Parameters  
Added Chip Enable Access Foot Note to AC Parameters  
Changed the tCD Min value from 5 ns to 15 ns  
Changed the Page Mode Values (tPC and tPAA) from 25 ns to 35 ns  
Document #: 38-05601 Rev. *B  
Page 12 of 12  
厂商 型号 描述 页数 下载

CYPRESS

 		CYU001M16OFFA-85BVI [ Pseudo Static RAM, 1MX16, 85ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, BGA-48 ] 14 页

CYPRESS

 		CYU01M16SCCU 16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ] 12 页

CYPRESS

 		CYU01M16SCE 16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ] 11 页

CYPRESS

 		CYU01M16SCEU-70BVXI 16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ] 11 页

CYPRESS

 		CYU01M16SCEU-70BVXIT [ Pseudo Static RAM, 1MX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48 ] 11 页

CYPRESS

 		CYU01M16SCG 16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ] 11 页

CYPRESS

 		CYU01M16SCG-70BVXI 16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ] 11 页

CYPRESS

 		CYU01M16SFCU 16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ] 12 页

CYPRESS

 		CYU01M16SFCU-70BVXI 16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ] 12 页

CYPRESS

 		CYU01M16SFE 16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ] 11 页

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