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CYU001M16OFFA-85BVI

型号：

CYU001M16OFFA-85BVI

品牌：

CYPRESS[ CYPRESS ]

页数：

14 页

PDF大小：

181 K

下载PDF手册
CYU001M16OFFA  
MoBL3™  
16Mb (1Mb x 16) Pseudo Static RAM  
active current. This is ideal for providing More Battery Life  
(MoBL®) in portable applications such as cellular telephones.  
The device can be put into standby mode reducing power  
consumption by more than 99% when deselected CE HIGH or  
both BHE and BLE are HIGH. The input/output pins (I/O0  
through I/O15) are placed in a high-impedance state when:  
deselected CE HIGH, outputs are disabled (OE HIGH), or  
during a write operation (Chip Enable (CE) LOW and Write  
Enable (WE) LOW). The device also has an automatic  
power-down feature that significantly reduces power  
consumption by 99% when addresses are not toggling even  
when the chip is selected (Chip Enable (CE) LOW, both BHE  
and BLE are LOW).  
Features  
• Advanced low-power MoBL3 architecture  
• 1T Cell, PSRAM architecture  
• High speed: 85 ns  
• Wide voltage range:  
— VCC range: 1.70V to 1.95V  
— VCCQ (I/O) range: 1.7V to VCC  
• Low active power  
— Typical active current: 1 mA @ f = 1 MHz  
— Typical active current: 10 mA @ f = fMAX  
• Low standby power  
• Automatic power-down when deselected  
• Partial Array Refresh (PAR) mode  
• Reduced Memory Size (RMS) mode  
• Deep Sleep mode  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the Truth Table at the back of this data sheet for a complete  
description of read and write modes. The CYU001M16OFFA  
has multiple low power modes. Please see the section titled  
“Low Power Modes” for a complete description of the PAR,  
• Automatic Temperature Controlled Self Refresh  
Functional Description[1]  
The CYU001M16OFFA MoBL3 is a high-performance CMOS  
pseudo static RAMs (PSRAM) organized as 1M words by 16  
bits that supports an asynchronous memory interface. This  
device features advanced circuit design to provide ultra-low  
RMS, Deep Sleep Modes. The CYU001M16OFFA is  
configured to have the Deep Sleep Mode disabled in the  
default state.  
Logic Block Diagram  
DATA IN DRIVERS  
A
10  
A
9
8
7
6
5
4
3
2
1
0
A
A
A
A
A
1M x 16  
RAM Array  
I/O –I/O  
0
7
A
A
A
I/O –I/O  
8
15  
A
COLUMN DECODER  
Refresh/  
Power-down  
Circuit  
ZZ  
BHE  
WE  
CE  
OE  
BLE  
CE  
Power -Down  
Circuit  
BHE  
BLE  
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05311 Rev. *A  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised July 8, 2003  
CYU001M16OFFA  
MoBL3™  
Pin Configuration[2, 3, 4, 5]  
FBGA  
Top View  
1
2
4
3
5
6
A
A
A
2
ZZ  
I/O  
OE  
BLE  
0
1
A
B
C
A
A
I/O BHE  
8
CE  
I/O  
4
3
0
A
A
6
I/O I/O  
I/O  
2
5
10  
1
9
V
A
V
I/O  
I/O  
3
A
CCQ  
D
E
F
SS  
7
11  
17  
V
DNU  
A
16  
V
CC  
SSQ  
I/O  
I/O  
12  
4
A
A
15  
I/O  
I/O  
5
I/O  
I/O  
6
14  
13  
14  
A
A
G
H
I/O  
A
WE I/O  
7
13  
12  
15  
19  
A
A
9
A
11  
A
A
NC  
10  
8
18  
Notes:  
2. DNU pins are to be left floating or tied to V.  
3. VSSQ is the ground pin for the I/O drivers. It should be connected to ground of the system.  
4. Pin H6 is the address expansion pin for the 32M density.  
5. ZZ pin is referred to as CE2 on other vendor data sheets.  
Document #: 38-05311 Rev. *A  
Page 2 of 14  
CYU001M16OFFA  
MoBL3™  
Programming the PAR Register  
Partial Array Refresh Register  
The PAR register contains five bits: A4 (most significant bit)  
down to A0 (least significant). To set the PAR register, the ZZ  
pin must be enabled (ZZ LOW). Once this is done, the chip  
enable (CE) is forced LOW, while the address bits, A0 through  
A4, are set to the desired PAR state. Then the control signals,  
WE, BLE, and BHE are all enabled and the state of the  
address bits A0 through A4 is written into the register. Please  
refer to the “PAR Register Update — Timing Waveform” for  
proper programming of the PAR register. The different  
possible configurations of the PAR register is shown in the  
table below. Note that each bit has a default setting upon  
power-up.  
This device has an internal register that controls the operating  
modes. This register is called the Partial Array Refresh  
Register, or PAR Register. Based on the contents of this  
register, the PSRAM can turn on or off various sections of  
memory, or cab be used in a reduced memory size, or  
enable/disable the Deep Sleep Mode.  
PAR Register Description  
Reserved  
ZZ Enable Deep Sleep  
Array On/Off on ZZ  
A3  
PAR Top/Btm Selection PAR Memory Selection  
A21–A5  
A4  
A2  
A1  
A0  
Bit(s)  
Name  
Description  
21–5  
4
Reserved  
Reserved  
0 – Deep Sleep Enabled  
ZZ Enable Deep Sleep  
1 – Deep Sleep Disabled (Default)  
3
2
Array On/Off on ZZ  
0 – PAR Mode (Default)  
1 – RMS Mode  
PAR Top/Bottom Half Selection  
PAR Memory Selection  
0 – Bottom (Default)  
1 – Top  
1–0  
00 – Full Array (16M — Default)  
01 – 3/4 Array (12M)  
10 – 1/2 Array (8M)  
11 – 1/4 Array (4M)  
PAR Register Update — Timing Waveform[10]  
t
WC  
Five Lower-order address bits (A4–A0) Define PAR Register  
ADDRESS  
CE  
t
SCE  
t
ZZCE  
t
t
HA  
AW  
t
t
ZZBE  
BW  
BHE/BLE  
WE  
t
SA  
t
PWE  
t
ZZWE  
ZZ  
t
ZZMIN  
Notes:  
6. IH(MAX) = VCCQ + 0.2V for pulse durations less than 20 ns.  
7. VIL(MIN) = –1V for pulse durations less than 20 ns.  
8. Overshoot and undershoot specifications are characterized and are not 100% tested.  
V
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ) and TA = 25C.  
10. The timing values for the PAR Register Update are shown in the “Partial Array Mode Timing” table and “Switching Characteristics” table.  
Document #: 38-05311 Rev. *A  
Page 3 of 14  
CYU001M16OFFA  
MoBL3™  
low. Once ZZ returns high in this mode, the PSRAM goes back  
to operating in full address refresh. The protocols shown on  
the “PAR Register Description Table” and in the “PAR Register  
Update — Timing Waveform” will have to be followed to turn  
on/off this mode of operation. Once the PAR register is  
updated, all future PAR accesses will use the contents of the  
PAR register when ZZ returns low. If the customer wants to  
change the PAR space, the PAR register must be updated per  
the instruction in the “PAR Register Description Table” section  
of this data sheet.  
Low-Power Modes  
The CYU001M16OFFA provides four distinct operation modes  
for reducing standby power:  
1. reduced memory size operation  
2. partial array refresh  
3. deep sleep mode  
4. temperature controlled self refresh.  
Reduced Memory Size Operation  
If the PAR register is not updated after power-up, the PSRAM  
will be in its default state. In the default state, the whole  
memory array will be refreshed.  
In this mode, the device can be operated as a reduced size  
PSRAM. For example, one could operate the 16M PSRAM as  
a 4M or a 8M memory block. The protocol to turn on/off the  
sections of the memory is described in the PAR register  
description. The RMS mode can be enabled by having the  
appropriate setting in the PAR register. The mode is effective  
once ZZ goes high and remains in the RMS mode until full  
array is restored by accessing the PAR register again.  
Deep Sleep Mode  
In this mode, the data integrity in the PSRAM is not  
guaranteed. This mode can be disabled by writing 1 into bit  
5(A4) of the PAR register. At any point of time, the Deep Sleep  
Mode can be enabled by driving ZZ low and then changing bit  
A4 to 0. Once this is done, the PSRAM enters the deep sleep  
mode. The device stays in the deep sleep mode until ZZ is  
driven High. Once the PSRAM enters the Deep Sleep Mode,  
the content of the PAR register is destroyed and the PAR  
register would go into the default state upon normal operation.  
At power up, all four sections of the die are activated and the  
PSRAM enters into its default state of full memory size and  
refresh space.  
Partial Array Refresh  
The PAR mode allows customers to turn off sections of the die  
in the stand-by mode to save standby current. The 16M  
MoBL3 is divided into four 4M sections allowing certain  
sections to be active (i.e., refreshed). The PAR mode also  
allows a customer to go into a low-power mode with ZZ tied  
low and keeps the data in a certain section of memory.  
Temperature Controlled Refresh  
The device has an automatic temperature controlled refresh  
circuitry. This allows the device to adjust the refresh rate based  
on the junction temperature of the device. The number of  
refreshes are in proportion to the temperature. This allows the  
standby current to decrease at lower temperatures. Please  
see the section on Thermal Characteristics for the junction  
temperature calculation.  
In the PAR, the PSRAM will only refresh certain portions of the  
memory, as configured by the user. This mode is only for  
standby operation, and is applicable as long as ZZ remains  
Partial Array Refresh — Entry/Exit[11]  
Partial Array Mode/  
Deep Sleep Mode  
ZZ  
1us  
suspend  
t
R
t
CDR  
CE or  
BLE / BHE  
Partial Array Mode Timings [12, 13]  
Parameter  
Description  
Min.  
Max.  
Unit  
µs  
tZZWE  
tCDR  
tR  
ZZ LOW to WE LOW  
Chip Deselect to ZZ LOW  
1
0
ns  
Operation Recovery Time (Deep Sleep Mode only)  
Deep Sleep Mode Time  
200  
µs  
tZZMIN  
tZZCE  
10  
0
µs  
ZZ LOW to CE LOW  
1
1
µs  
tZZBE  
ZZ LOW to BHE/BLE LOW  
0
µs  
Notes:  
11. OE and the data pins are in a “don’t care” state while the device is in Partial Array mode.  
12. All other timing parameters are as shown in the switching characteristics section.  
13.  
tR applies only in the Deep Sleep mode.  
Document #: 38-05311 Rev. *A  
Page 4 of 14  
CYU001M16OFFA  
MoBL3™  
Variable Address Space — Address Patterns  
Partial Array Refresh Mode (A3 = 0, A4 = 1)  
A2 A1, A0  
Refresh Section  
One-fourth of the Die  
Half of the Die  
Address  
00000h – 3FFFFh (A19 = A18 = 0)  
00000h – 7FFFFh (A19 = 0)  
Size  
Density  
4M  
0
0
0
1
1
1
11  
10  
01  
11  
10  
01  
256K x 16  
512K x 16  
768K x 16  
256K x 16  
512K x 16  
768K x 16  
8M  
Three-fourths of the Die  
One-fourth of the Die  
Half of the Die  
00000h – BFFFFh (A19: A18 ≠ 11)  
C0000h – FFFFFh (A19 = A18 = 0)  
80000h – FFFFFh (A19 = 1)  
12M  
4M  
8M  
Three-fourths of the Die  
40000h – FFFFFh (A19: A18 ≠ 00)  
Reduced Memory Size Mode (A3 = 1, A4 = 1)  
00000h – 3FFFFh (A19 = A18 = 0)  
00000h – 7FFFFh (A19 = 0)  
12M  
0
0
0
0
1
1
1
1
11  
10  
01  
00  
11  
10  
01  
00  
One-fourth of the Die  
Half of the Die  
256K x 16  
512K x 16  
768K x 16  
1M x 16  
4M  
8M  
Three-fourths of the Die  
Full Die  
00000h – BFFFFh (A19: A18 ≠ 11)  
00000h – FFFFFh  
12M  
16M  
4M  
One-fourth of the Die  
Half of the Die  
C0000h – FFFFFh (A19 = A18 = 1)  
80000h – FFFFFh (A19 = 1)  
256K x 16  
512K x 16  
768K x 16  
1M x 16  
8M  
Three-fourths of the Die  
Full Die  
40000h – FFFFFh (A19: A18 ≠ 00)  
00000h – FFFFFh  
12M  
16M  
Document #: 38-05311 Rev. *A  
Page 5 of 14  
CYU001M16OFFA  
MoBL3™  
Memory Block Split  
Bottom Address Range  
0
1
0
1
1/4 Address Space Refresh  
1/2 Address Space Refresh  
Active Address Space:  
Active Address Space:  
A0 - A18  
A<19> = <0>  
A0 - A17  
A<18, 19> = <0, 0>  
0
1
0
1
3/4 Address Space Refresh  
Active Address Space:  
Full Address Space Refresh  
Active Address Space:  
A0 - A19  
A<18, 19> = <0, 0>, <1, 0>, <0, 1>  
A0 - A19  
A<18, 19> = <X, X>  
Top Address Range  
0
1
0
1
1/4 Address Space Refresh  
Active Address Space:  
A0 - A17  
1/2 Address Space Refresh  
Active Address Space:  
A0 - A18  
A<19> = <1>  
A<18, 19> = <1, 1>  
0
0
1
1
Full Address Space Refresh  
Active Address Space:  
A0 - A19  
A<18, 19> = <X, X>  
3/4 Address Space Refresh  
Active Address Space:  
A0 - A19  
A<18, 19> = <1, 0>, <0, 1>, <1, 1>  
Document #: 38-05311 Rev. *A  
Page 6 of 14  
CYU001M16OFFA  
MoBL3™  
DC Input Voltage[6,7,8] ........................................ −0.3V to 2.25V  
Maximum Ratings  
Output Current into Outputs (LOW)............................. 20 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage...........................................> 2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature .................................–65°C to +150°C  
Latch-up Current.....................................................> 200 mA  
Ambient Temperature with  
Power Applied.............................................–55°C to +125°C  
Operating Range  
Supply Voltage to Ground Potential .................−0.3V to 2.25V  
DC Voltage Applied to Outputs  
in High-Z State[6,7,8] ............................................−0.3V to 2.25V  
Range Ambient Temperature (TA)  
VCC  
1.7V to 1.7V to  
1.95V VCC  
VCCQ  
Industrial  
−25°C to +85°C  
Product Portfolio  
Power Dissipation  
Operating, Icc (mA)  
VCC Range(V)  
f = 1 MHz f = fMAX  
Standby, ISB2 (µA)  
Speed  
Product  
Min.  
1.7  
Typ.  
1.8  
Max.  
1.95  
1.95  
(ns)  
Typ.[9]  
Max.  
Typ.[9]  
Max.  
25  
Typ.[9]  
Max.  
100  
CYU001M16OFFAU  
CYU001M16OFFAS  
85  
1
1
5
5
10  
10  
50  
1.7  
1.8  
85  
25  
50  
125  
DC Electrical Characteristics (Over the Operating Range)  
CYU001M16OFFA  
Parameter  
Description  
Test Conditions  
Min.  
Typ.[9]  
Max.  
Unit  
VOH  
Output HIGH Voltage  
IOH = −0.1 mA  
VCCQ  
0.8  
*
V
VOL  
VIH  
VIL  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
IOL = 0.1 mA  
VCCQ  
*0.2  
V
V
V
VCCQ  
0.8  
*
VCCQ  
0.2  
+
−0.2  
VCCQ  
*0.2  
IIX  
Input Leakage Current  
Output Leakage Current  
GND < VI < VCCQ  
−1  
−1  
+1  
+1  
µA  
µA  
IOZ  
ICC  
GND < VO < VCCQ, Output Disabled  
VCC Operating Supply  
Current  
f = fMAX = 1/tRC  
f = 1 MHz  
Vcc = 1.95V, IOUT  
0mA, CMOS level  
=
10  
1
25  
mA  
5
ISB1  
Automatic CE Power-down CE > VCCQ − 0.2V,  
Current − CMOS Inputs VIN > VCCQ − 0.2V, VIN < 0.2V,  
f = fMAX(Address and Data Only),  
f = 0 (OE, WE, BHE and BLE)  
S
U
50  
50  
125  
100  
µA  
µA  
ISB2  
Automatic CE Power-down CE > VCCQ − 0.2V,  
Current − CMOS Inputs VIN > VCCQ − 0.2V or VIN < 0.2V,  
S
U
50  
50  
125  
100  
f = 0, VCC=1.95V  
Capacitance[14]  
Parameter  
Description  
Test Conditions  
Max.  
Unit  
CIN  
Input Capacitance  
TA = 25°C, f = 1 MHz  
VCC = VCC(typ)  
6
8
pF  
pF  
COUT  
Output Capacitance  
Thermal Resistance[14]  
Parameter  
Description  
Test Conditions  
FBGA  
55  
Unit  
θJA  
Thermal Resistance (Junction to Ambient)  
Thermal Resistance (Junction to Case)  
Still Air, soldered on a 3 x 4.5 inch, two-layer  
printed circuit board  
°C/W  
°C/W  
θJC  
16  
Note:  
14. Tested initially and after design or process changes that may affect these parameters.  
Document #: 38-05311 Rev. *A  
Page 7 of 14  
CYU001M16OFFA  
MoBL3™  
AC Test Loads and Waveforms  
R1  
ALL INPUT PULSES  
90%  
10%  
VCC  
OUTPUT  
VCC  
GND  
90%  
10%  
Rise Time = 1 V/ns  
Fall Time = 1 V/ns  
R2  
30 pF  
INCLUDING  
JIG AND  
SCOPE  
Equivalent to:  
THÉVENIN EQUIVALENT  
RTH  
OUTPUT  
VTH  
Parameters  
1.8V I/O  
10800  
10800  
5400  
Unit  
W
R1  
R2  
W
RTH  
VTH  
W
0.90  
V
Switching Characteristics (Over the Operating Range) [15]  
CYU001M16OFFA  
Min. Max.  
Parameter  
Read Cycle  
Description  
Unit  
tRC  
Read Cycle Time  
85  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
85  
tOHA  
tACE  
Data Hold from Address Change  
CE LOW to Data Valid  
85  
35  
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tDBE  
OE LOW to Data Valid  
OE LOW to Low Z16,17, 19]  
OE HIGH to High Z16,17, 19]  
CE LOW to Low Z16,17, 19]  
CE HIGH to High Z16,17, 19]  
BLE/BHE LOW to Data Valid  
Address Skew  
5
25  
10  
25  
85  
10  
tSK  
tLZBE  
tHZBE  
Write Cycle[18]  
tWC  
BLE/BHE LOW to Low Z[16,17, 19]  
BLE/BHE HIGH to High-Z[16,17, 19]  
5
25  
Write Cycle Time  
85  
75  
75  
0
ns  
ns  
ns  
ns  
ns  
ns  
tSCE  
CE LOW to Write End  
Address Set-up to Write End  
Address Hold from Write End  
Address Set-up to Write Start  
WE Pulse Width  
tAW  
tHA  
tSA  
0
tPWE  
65  
1000  
Notes:  
15. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of VCCQ(typ)/2, input pulse levels of to VCCQ(typ), and output loading of  
the specified IOL/IOH and 30-pF load capacitance.  
16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any  
given device.  
17. tHZOE, tHZCE, tHZBE and tHZWE transitions are measured when the outputs enter a high-impedance state.  
18. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE =VIL. All signals must be ACTIVE to initiate a write and any  
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates  
the write.  
19. High-Z and Low-Z parameters are characterized and are not 100% tested.  
Document #: 38-05311 Rev. *A  
Page 8 of 14  
CYU001M16OFFA  
MoBL3™  
Switching Characteristics (Over the Operating Range)(continued)[15]  
CYU001M16OFFA  
Min. Max.  
Parameter  
Description  
BLE/BHE LOW to Write End  
Unit  
ns  
tBW  
75  
30  
0
tSD  
Data Set-up to Write End  
Data Hold from Write End  
WE LOW to High Z16,17, 19.]  
WE HIGH to Low Z16,17, 19.]  
ns  
tHD  
ns  
tHZWE  
tLZWE  
25  
ns  
10  
ns  
Switching Waveforms  
[20]  
Read Cycle 1 (Address Transition Controlled)  
tRC  
ADDRESS  
tSK  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Read Cycle No. 2 (OE Controlled)[20]  
ADDRESS  
t
RC  
CE  
tSK  
t
t
HZCE  
ACE  
OE  
t
HZOE  
t
DOE  
LZOE  
BHE/BLE  
t
t
HZBE  
t
DBE  
t
LZBE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
Note:  
20. WE is HIGH for Read Cycle.  
Document #: 38-05311 Rev. *A  
Page 9 of 14  
CYU001M16OFFA  
MoBL3™  
Switching Waveforms(continued)  
Write Cycle No. 1(WE Controlled)[18, 19, 21, 22, 23]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
SK  
t
t
HA  
AW  
t
t
SA  
PWE  
WE  
t
BW  
BHE/BLE  
OE  
t
t
SD  
HD  
DATA  
DATA I/O  
VALID  
IN  
23  
NOTE  
t
HZOE  
Write Cycle No. 2 (CE Controlled)[18, 19, 21, 22, 23]  
t
WC  
ADDRESS  
t
SCE  
CE  
tSA  
t
t
HA  
AW  
t
PWE  
WE  
t
BW  
BHE/BLE  
OE  
t
t
SD  
HD  
VALID  
DATA  
DATA I/O  
NOTE 23  
IN  
t
HZOE  
Notes:  
21. Data I/O is high impedance if OE = VIH  
.
22. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
23. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.  
Document #: 38-05311 Rev. *A  
Page 10 of 14  
CYU001M16OFFA  
MoBL3™  
Switching Waveforms(continued)  
Write Cycle No. 3 (WE Controlled, OE LOW)[22, 23]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
BW  
BHE/BLE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
DATAI/O  
DATA VALID  
IN  
t
LZWE  
t
HZWE  
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[22, 23]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
tBW  
BHE/BLE  
WE  
t
SA  
tPWE  
t
t
HD  
SD  
DATA I/O  
VALID  
DATAIN  
NOTE 23  
Document #: 38-05311 Rev. *A  
Page 11 of 14  
CYU001M16OFFA  
MoBL3™  
Truth Table[25]  
CE ZZ WE OE BHE BLE  
Inputs/Outputs  
High Z  
Mode  
Deselect/Power-Down  
Deselect/Power-Down  
Deep Sleep Mode  
Read  
Power  
H
X
X
L
H
H
L
X
X
L
X
X
X
L
X
H
X
L
X
H
X
L
Standby (ISB  
Standby (ISB  
Deep Sleep Current (ICCDS  
Active (ICC  
Active (ICC  
)
High Z  
)
[24]  
High Z  
)
H
H
H
H
Data Out (I/O0–I/O15  
)
)
L
L
H
L
Data Out (I/O0–I/O7); Read  
I/O8–I/O15 in High Z  
)
L
H
H
L
L
H
Data Out (I/O8–I/O15); Read  
I/O0–I/O7 in High Z  
Active (ICC)  
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z  
High Z  
High Z  
Output Disabled  
Active (ICC  
Active (ICC  
Active (ICC  
)
Output Disabled  
Output Disabled  
)
)
L
Data In (I/O0–I/O15  
)
Write (Upper Byte and Lower Byte) Active (ICC  
)
L
H
Data In (I/O0–I/O7);  
I/O8–I/O15 in High Z  
Write (Lower Byte Only) Active (ICC)  
L
H
L
X
L
H
Data In (I/O8–I/O15); Write (Upper Byte Only)  
I/O0 –I/O7 in High Z  
Active (ICC)  
Ordering Information  
Speed  
Package  
Operating  
Range  
(ns)  
Ordering Code  
CYU001M16OFFA-85BVI  
zzzzzzz-85BVI  
Name  
BV48A  
BV48A  
Package Type  
85  
48-ball Fine Pitch BGA (6.0 x 8.0 x 1.0 mm)  
48-ball Fine Pitch BGA (6.0 x 8.0 x 1.0 mm)  
Industrial  
Industrial  
85  
Notes:  
24. This assumes that the Deep Sleep Mode is enabled in the PAR register.  
25. H = VIH, L = VIL, X = Don’t Care  
Document #: 38-05311 Rev. *A  
Page 12 of 14  
CYU001M16OFFA  
MoBL3™  
Package Diagram  
48-Lead VFBGA (6 x 8 x 1 mm) BV48A  
51-85150-*B  
MoBL is a registered trademark, and MoBL2, MoBL3, MoBL4, and More Battery Life are trademarks, of Cypress Semiconductor.  
All product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-05311 Rev. *A  
Page 13 of 14  
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CYU001M16OFFA  
MoBL3™  
Document History Page  
Document Title: CYU001M16OFFA 16Mb (1Mb x 16) Pseudo Static RAM  
Document Number: 38-05311  
Orig. of  
REV. ECN NO. Issue Date Change  
Description of Change  
**  
117415  
127140  
09/12/02  
07/15/03  
HRT New Data Sheet  
*A  
HRT Changed data sheet status from Preliminary to Final  
Changed marketing part number from CY81U016X16B9A to CYU001M16OFFA  
Included typical values for ICC @ f =1 Mhz, f = fmax and Isb2  
Added two power bins: S: Super Low and U: Ultra Low  
Modified Isb2 Max. S Bin: 125 µA and U Bin: 100 µA  
Changed the Tsk spec from 15 ns Max.to 10 ns Max.  
Document #: 38-05311 Rev. *A  
Page 14 of 14  
厂商 型号 描述 页数 下载

CYPRESS

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