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CYUSB3610

EZ-USB GX3: SuperSpeed USB

to Gigabit Ethernet Bridge Controller

EZ-USB GX3: SuperSpeed USB to Gigabit Ethernet Bridge Controller

■ Supports automatic loading of USB Device Descriptors,

Node-ID, etc. from internal memory or external EEPROM after

Features

power-on initialization

■ Low-power single chip USB 3.0 to 10/100/1000M Gigabit

Ethernet Bridge Controller with Energy Efficient Ethernet (EEE)

■ Single 25 MHz clock input from crystal or oscillator source

■ Integrates on-chip power-on reset circuit

■ Gigabit Ethernet Controller

❐ Supports IEEE 802.3az (Energy Efficient Ethernet)

❐ IEEE 802.3, 802.3u, and 802.3ab compatible

❐ Integrates 10/100/1000Mbps Gigabit Ethernet MAC/PHY

■ Integrates pipelined RISC SoC (System on Chip) for handling

protocol and control functions

❐ Supports dynamic cable length detection and dynamic power

■ 68-pin QFN 8 mm × 8 mm RoHS/REACH compliant package

■ Operating temperature: 0 °C to 70 °C

adjustment Green Ethernet (Gigabit mode only)

❐ Supports parallel detection and automatic polarity correction

❐ Supports crossover detection and auto-correction

Target Applications

❐ Supports IPv4/IPv6 packet Checksum Offload

Engine

(COE)

to reduce CPU loading, including IPv4

■ Docking Station

■ USB Dongle

IP/TCP/UDP/ICMP/IGMP

&

IPv6 TCP/UDP/ICMPv6

checksum check & generation

❐ Supports TCP Large Send Offload V1

■ Embedded systems

■ Network Printer

■ USB Port Replicator

■ POS, Card Reader

■ Netbook, UMPC, MID

■ Ultrabook

❐ Supports full duplex operation with IEEE 802.3x flow control

and half duplex operation with back-pressure flow control.

❐ Supports IEEE 802.1P Layer 2 Priority Encoding and

Decoding

❐ Supports IEEE 802.1QVLANtagging and2VLAN ID filtering;

received VLAN Tag (4 bytes) can be stripped off or preserved

❐ Supports Jumbo frame

❐ PHY loop-back diagnostic capability

■ USB Device Controller

❐ Integrates on-chip USB 3.0 PHY and controller

❐ Supports USB 3.0 power saving modes (U0, U1, U2, and U3)

■ IP STB, IP TV

■ Gaming Console

❐ High performance packet transfer rate over USB bus using

burst transfer mechanism

Functional Description

■ Advanced Power Management Features

❐ Supports power management offload (ARP & NS)

❐ Supports dynamic power management to reduce power

dissipation during idle or light traffic

❐ Supports AutoDetach power saving. Soft-disconnect from

USB host when Ethernet cable is unplugged

❐ Supports advanced link down power saving when Ethernet

cable is unplugged

The GX3 SuperSpeed USB to 10/100/1000M Gigabit Ethernet

Bridge Controller is a high-performance and highly integrated

controller that enables low-cost design, small form-factor, and

simple plug-and-play Gigabit Ethernet network connection

capability for docking stations, desktops, notebook PCs,

Ultrabooks, gaming consoles, digital-home appliances, and any

embedded system using a standard USB port.

GX3 implements a 10/100/1000Mbps Ethernet LAN function

based on IEEE802.3, IEEE802.3u, and IEEE802.3ab standards

with embedded SRAMs for packet buffering. It also integrates an

on-chip 10/100/1000Mbps EEE-compliant Ethernet PHY to

simplify system design. It features a USB interface to

communicate with a USB Host Controller and is compliant with

USB specification v3.0.

■ Wake-on-LAN Feature

❐ Supportssuspendmodeandremotewakeupvialink-change,

Magic Packet, Microsoft wakeup frame and external wakeup

❐ Supports Bonjour wake-on-demand

■ Supports serial EEPROM (93C56/66) for storing USB

Descriptors, Node-ID, etc

Cypress Semiconductor Corporation

Document Number: 001-94768 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 31, 2018

CYUSB3610

Block Diagram

CS

SCK

SDA

XTALIN

XTALOUT

MFA[3:0],

GPIO[3:0]

Data

RAM

PLL

oscillator

Reset

RESET#

Serial

EEPROM

interface

GPIOs,

LEDs

Pipelined

RISC

DMA

Engine

ROM

DP/DM

SSTXP(M)

SSRXP(M)

USB

3.0

PHY

USB

3.0

core

SuperSpeed USB to

Gigabit Ethernet

Bridge

Gigabit

Ethernet

PHY

MDIP[3:0]

MDIN[3:0]

Checksum

Offload

Engine

SRAM

buffer

Memory

Arbiter

GMAC

core

Document Number: 001-94768 Rev. *C

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CYUSB3610

Contents

Pin Configurations ...........................................................4

Signal Description ............................................................5

Pin Description .................................................................5

Settings .............................................................................8

Hardware Setting

USB Configuration Structure ........................................20

Electrical Specifications ................................................21

DC Characteristics ....................................................21

Thermal Characteristics ............................................24

Power Consumption ..................................................25

Power-up Sequence ..................................................27

AC Timing Characteristics .........................................28

Package Information ......................................................30

68-pin QFN 8 × 8 package ........................................30

Recommended PCB Footprint

for 68-pin QFN 8x8 package ............................................31

Ordering Information ......................................................32

Acronyms ........................................................................33

Document Conventions .................................................33

Units of measure .......................................................33

Document History Page .................................................34

Sales, Solutions, and Legal Information ......................35

Worldwide Sales and Design Support .......................35

Products ....................................................................35

PSoC® Solutions ......................................................35

Cypress Developer Community .................................35

Technical Support .....................................................35

for Operation Mode and Multi-Function Pins ......................8

Functional Overview ........................................................9

USB Core and Interfaces ............................................9

Energy Efficient Ethernet (EEE) ..................................9

10/100/1000M Ethernet PHY ......................................9

MAC Core ....................................................................9

Checksum Offload Engine (COE) ...............................9

Memory Arbiter ............................................................9

USB to Ethernet Bridge ...............................................9

SEEPROM Loader Interface .....................................10

GPIOs and LED .........................................................10

PLL Clock Generator .................................................10

Reset Generation ......................................................10

Default Wake-On-LAN (DWOL) Ready Mode ................11

Procedure to Enable Default WOL Ready Mode .......11

Flow Chart of Default WOL Ready Mode ..................13

Serial EEPROM Memory Map ........................................14

Detailed Description ..................................................15

Document Number: 001-94768 Rev. *C

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CYUSB3610

Pin Configurations

Figure 1. 68-pin QFN pinout

Document Number: 001-94768 Rev. *C

Page 4 of 35

CYUSB3610

Signal Description

The following abbreviations apply to the following pin description table.

Signal Name

Signal Description

Signal Name

Signal Description

I12

I3

Input, 1.2 V

Input, 3.3 V

AI

Analog Input

AO

AB

PU

PD

S

Analog Output

I5

Input, 3.3 V with 5 V tolerance

Output, 3.3 V

Analog Bi-directional I/O

Internal Pull Up (75 kΩ)

Internal Pull Down (75 kΩ)

Schmitt Trigger

O3

B5

B3

P

Bi-directional I/O, 3.3 V with 5 V tolerance

Bi-directional I/O, 3.3 V

Power/GND

T

Tri-stateable

Pin Description

Pin Name

Type

Pin No.

Pin Description

USB Interface

DP

AB

23

24

29

27

34

32

21

USB 2.0 D+ pin.

DM

USB 2.0 D– pin.

SSTXP

SSTXM

SSRXP

SSRXM

VBUS

AB

USB 3.0 SSTX+ pin.

USB 3.0 SSTX– pin.

USB 3.0 SSRX+ pin.

USB 3.0 SSRX– pin.

AB

I5/PD/S

VBUS pin input. Please connect to USB bus power.

Gigabit EEE Ethernet PHY Interface

RSET_BG

MDIP0

AO

AB

47

53

54

For Ethernet PHY’s internal biasing. Please connect to GND througha 2.49 kΩ +1% resistor.

In MDI mode, this is the first pair in 1000Base-T, i.e. the BI_DA+/- pair, and is the transmit

pair in 10Base-T and 100Base-TX.

In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the receive pair in

10Base-T and 100Base-TX.

MDIN0

MDIP1

MDIN1

AB

56

57

In MDI mode, this is the secondpair in 1000Base-T,i.e. the BI_DB+/- pair, and is the receive

pair in 10Base-T and 100Base-TX.

In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the transmit pair in

10Base-T and 100Base-TX.

MDIP2

AB

59

60

62

63

In MDI mode, this is the third pair in 1000Base-T, i.e., the BI_DC+/- pair.

In MDI crossover mode, this pair acts as the BI_DD+/- pair.

MDIN2

MDIP3

In MDI mode, this is the fourth pair in 1000Base-T, i.e., the BI_DD+/- pair.

In MDI crossover mode, this pair acts as the BI_DC+/- pair.

MDIN3

Clock Pins

XTALIN

XTALOUT

CLKOUT

I3

38

39

42

25 MHz ± 0.005% crystal or oscillator clock input.

25 MHz crystal or oscillator clock output.

O3

A controllable 25MHz clock output.

Please connect it to CLKIN pin with a 22 Ohm termination resistor near to CLKOUT pin.

CLKIN

I3

50

25 MHz clock input.

Please connect it to CLKOUT pin with a 22 Ohm termination resistor.

Document Number: 001-94768 Rev. *C

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CYUSB3610

Pin Description (continued)

Pin Name

Type

Pin No.

Pin Description

Serial EEPROM Interface

SCK

CS

B5/PD/T

B5/PU/T

16

EEPROM Clock. SCK is an output clock to EEPROM to provide timing reference for the

transfer of CS, and SDA signals. SCK only drive high / low only while accessing EEPROM

otherwise it is tri-stated and internally pulled down.

17

15

EEPROMChip Select. CS is assertedhighsynchronouslywith respectto risingedge of SCK

as chip select signal. CS drives high / low only while accessing EEPROM otherwise it is

tri-stated and internally pulled down.

SDA

EEPROM Data. SDA is the serial output data to EEPROM’s data input pin and is

synchronous with respect to the rising edge of SCK. SDA drives high / low only while

accessing EEPROM otherwise it is tri-stated and internally pulled up.

Misc. Pins

RESET#

I5/PU/S

I3/PU/S

I5/PD/S

18

41

20

Extrernal chip reset input.Active low. This input feeds to the internal power-on reset circuitry,

which provides the main reset source of this chip.

WAKEUP#

SLF_PWR

Remote-wakeup trigger from external pin. WAKEUP# should be asserted low for more than

2 cycles of 25 MHz clock to be effective.

Self_power Indication Input.

0: will indicate to Host that this device is a bus-powered device.

1: will indicate to Host that this device is a self-powered device.

GPIO[3]

B3/PD

3

4

5

6

General Purpose Input/Output Pin 3.

General Purpose Input/Output Pin 2.

General Purpose Input/Output Pin 1.

GPIO[2]

GPIO[1]

GPIO[0]/PME

General Purpose Input/Output Pin 0 or PME (Power Management Event). This pin is an

input pin by default after power-on reset. GPIO[0] also can be defined as PME output to

indicate wake up event detected.

MFA[3]

MFA[2]

MFA[1]

MFA[0]

B3

7

8

Itisamulti-functionpin.It acts as a USB SuperSpeed indicator on power up. It can be defined

as a GPIO pin. Please refer to Table 3 on page 8.

It is a multi-function pin. It acts as an Ethernet PHYLED indicator (Link 10/100/1000+Active)

by default. It can be defined as a GPIO pin. Please refer to Table 3 on page 8.

13

14

It is a multi-function pin. It acts as an Ethernet PHY LED indicator (Link 10/100/1000) by

default and can be a GPIO pin. Please refer to Table 3 on page 8.

It is a multi-function pin. It acts as an Ethernet PHY LED indicator (Active) and can be a

GPIO pin. Please refer to Table 3 on page 8.

NC

I3/PD/S

I3/PD

I3/S

68

1

Test pin. User can keep this pin NC.

Test pin. User should pull down this pin.

NC

2

RESERVED

NC

66

67

46

I3/S

I3

O3

11, 36, 44, Test pin. NC.

51, 52, 64

Power and Ground Pins

A3V3

P

25

22

Analog Power for USB 3.0 transceiver. 3.3V.

GND_3V3

U3TXVDDQ

U3TXVSS

Analog Ground for USB 3.0 transceiver.

Analog Power for USB 3.0 transceiver. 1.2 V.

Analog Ground for USB 3.0 transceiver.

26

28, 30

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CYUSB3610

Pin Description (continued)

Pin Name

U3RXVDDQ

U3RXVSS

E12VDDQ

E33VDDQ

E12VCC

E33VCC

CVDDQ

Type

P

Pin No.

31

Pin Description

Analog Power for USB 3.0 transceiver. 1.2 V.

P

33, 35

48

Analog Ground for USB 3.0 transceiver.

Analog Power for Ethernet PHY. 1.2 V.

Analog Power for Ethernet PHY. 3.3 V.

Analog Power for Ethernet PHY. 1.2 V.

Analog Power for Ethernet PHY. 3.3 V.

Digital I/O Power for Clock pins. 3.3 V.

Digital Ground for clock pins.

P

49

P

55, 61

58

P

37

VSS

P

40

DVDD

P

10, 19, 45, Digital Core Power. 1.2 V.

65

DVSS

VIO

P

9

Digital Ground to E-pad

Digital I/O Power. 3.3 V.

12, 43

Document Number: 001-94768 Rev. *C

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CYUSB3610

Settings

Hardware Setting for Operation Mode and Multi-Function Pins

The following hardware settings define the desired operation mode and some multi-function pin configurations. The logic levels shown

on setting the pins below are sampled from the chip I/O pins during power on reset based on the setting of the pin’s pull-up or pull-down

resistor in the schematic.

■ EEPROM Offset 05h, Flag[4]: Defines the multi-function pin GPIO[0] / PME

GPIO[0] is a general purpose I/O normally controlled by vendor commands. User can change this pin to operate as a PME (Power

Management Event) for remote wake up. Please refer to Flag (EEPROM: 05h) on page 15 for detailed description of “Flag” of bit

4 (PME_PIN).

■ GPIO[1] pin: Determines whether this chip will go to Default WOL (Wake-On-LAN) Ready Mode after power on reset.

Table 1. GPIO[1] Description

GPIO[1]

Description

0

1

Normal operation mode. By default, internal pull-up resistor (4.7 KΩ) is enabled.

Enable Default WOL Ready Mode. Notice that the external pulled-up resistor must be 4.7 KΩ.

For more details, please refer to Default Wake-On-LAN (DWOL) Ready Mode on page 11.

■ GPIO[2] pin: Determines whether SSTXP swaps with SSTXM and SSRXP swaps with SSRXM for USB3.0 PHY.

Table 2. GPIO[2] Description

GPIO[2]

Description

0

1

Disable swapping. By default, internal pull-up resistor (4.7 KΩ) is enabled.

Enable swapping. Notice that the external pulled-up resistor must be 4.7 KΩ.

■ MFA[3] ~ MFA[0] pins: There are 4 multi-function pins. They can be used either for driving indicator LEDs or as normal GPIOs

controlled by vendor command PIN Control Register MFA_EN.

Table 3. MFA_3 ~ MFA_0 pin configuration

Section LED Mode

PIN Name

Default Definition

(EEPROM: 42h) on

page 16

MFA Control Register

MFA[3]

MFA[2]

MFA[1]

MFA[0]

LED_USB indicator (Super-speed)

Programmable LED (Link 10/100/1000+Active)

Programmable LED (Link 10/100/1000)

Programmable LED (Active)

LED_3

LED_2

LED_1

LED_0

MFAIO_3

MFAIO_2

MFAIO_1

MFAIO_0

Document Number: 001-94768 Rev. *C

Page 8 of 35

CYUSB3610

Functional Overview

USB Core and Interfaces

The USB core is made up of USB 3.0 PHY and Device Controller. The USB 3.0 PHY processes USB Physical layer signals. The USB

3.0 Device Controller is interfaced with USB 3.0 PHY by PIPE/UTMI buses and it processes packets of link layer and protocol layer.

The USB 3.0 Device Controller supports Bulk IN, Bulk OUT and Interrupt IN transfers for data transactions.

Energy Efficient Ethernet (EEE)

GX3 supports IEEE 802.3az, also known as Energy Efficient Ethernet (EEE) at 10Mbps, 100Mbps and 1000Mbps. It also supports

EEE specified negotiation method to enable link partner to determine whether EEE is supported and to select the best set of

parameters common to both devices. It provides a protocol to coordinate transitions to/from a lower power consumption level (Low

Power Idle mode) based on link utilization. When no packets are being transmitted, the system goes to Low Power Idle mode to save

power. Once packets need to be transmitted, the system returns to normal mode, and starts transmitting packets without changing

the link status and without dropping/corrupting frames.

During the Low Power Idle mode, most of the circuits are disabled to save power. However, the transition time to/from Low Power

Idle mode is kept small enough to be transparent to the upper layer protocols and applications.

10/100/1000M Ethernet PHY

The 10/100/1000M Ethernet PHY is compliant with 10Base-T, 100Base-TX, and 1000Base-T IEEE 802.3 standards. It provides all

the necessary physical layer functions to transmit and receive Ethernet packets over CAT 5 UTP cable or CAT 3 UTP (10 Mbps only)

cable. It uses state-of-the-art DSP technology and an Analog Front End (AFE) to enable high-speed data transmission and reception

over UTP cable. Crossover Detection & Auto-Correction, polarity correction, adaptive equalization, cross-talk cancellation, echo

cancellation, timing recovery, and error correction functions are also implemented.

MAC Core

The MAC core supports IEEE 802.3, IEEE 802.3u and IEEE 802.3ab MAC sub-layer functions, such as basic MAC frame receive and

transmit, CRC checking and generation, filtering, forwarding, flow-control in full-duplex mode, and collision-detection and handling in

half-duplex mode, etc. It supports virtual local area network (VLAN)-tagged frames according to IEEE 802.1Q specification in both

transmit and receive functions. The MAC core also implements CRC-32 checking at full-speed using a multi-stage, cyclic redundancy

code (CRC) calculation architecture with optional forwarding of the frame check sequence (FCS) field to the user application CRC-32

generation and append on transmit.

Checksum Offload Engine (COE)

The Checksum Offload Engine (COE) supports IPv4, IPv6, layer 4 (TCP, UDP, ICMP, ICMPv6 and IGMP) header processing functions

and real time checksum calculation in the hardware.

The COE supports the following features in layer 3:

■ IP header parsing, including IPv4 and IPv6

■ IPv6 routing header type 0 supported

■ IPv4 header checksum check and generation (There is no checksum field in IPv6 header)

■ Detecting on RX direction for IP packets with error header checksum

The COE supports the following features in layer 4:

■ TCP and UDP checksum check and generation for non-fragmented packet

■ TCP Large Send Offload V1

■ ICMP, ICMPv6 and IGMP message checksum check and generation for non-fragmented packet

Memory Arbiter

The memory arbiter block stores received MAC frames into on-chip SRAM (packet buffer) and then forward it to the USB bus upon

request from the USB host via Bulk IN transfer. It also monitors the packet buffer usage in full-duplex mode for triggering PAUSE

frame (or in half-duplex mode to activate Back pressure jam signal) transmission out on transmit (TX) direction. The memory arbiter

block is also responsible for storing MAC frames received from the USB host via Bulk OUT transfer and scheduling transmission out

towards Ethernet network.

USB to Ethernet Bridge

The USB to Ethernet bridge block converts Ethernet MAC frames into USB packets or vice-versa. This block supports burst transfer

mechanism to offload software burden and to offer very high packet transfer throughput over USB bus.

Document Number: 001-94768 Rev. *C

Page 9 of 35

CYUSB3610

SEEPROM Loader Interface

The SEEPROM loader interface is responsible for reading configuration data automatically from the external serial EEPROM after

power-on reset.

If the content of EEPROM offset 05h (low byte) is equal to (0xFF - SUM [EEPROM offset 03h ~ 04h]), the EEPROM is the first

candidate for SEEEPROM loader.

GPIOs and LED

There are 4 GPIO pins (GPIO[0/1/2/3]) and 4 multi-function pins group A (MFA[0/1/2/3]) provided by this chip. The MFA[0/1/2/3] pins

are also used for LED indication. Please refer to LED Mode (EEPROM: 42h) on page 16 for details.

PLL Clock Generator

GX3 includes an on-chip internal oscillator circuit for 25 MHz which allows the chip to operate cost effectively with just external 25 MHz

crystals.

The external 25 MHz crystal or oscillator, via pins XTALIN/XTALOUT, provides the reference clock to internal oscillator circuit to

generate clock for the embedded Ethernet PHY, embedded USB PHY, and base clock for the ASIC.

The external 25 MHz Crystal spec is listed in below table. For more details on crystal timing, please refer to Clock Timing on page 28

and CYUSB3610 demo board reference schematic.

Table 4. External 25 MHz Crystal Units specifications

Parameter

Symbol

Typical Value

25.000000 MHz

Fundamental

+30 ppm

Nominal Frequency

Oscillation Mode

f_O

Frequency Tolerance (@25 °C)

Frequency Stability Over Operating Temperature Range

Equivalent Series Resistance

Load Capacitance

+30 ppm

ESR

CL

70 Ω max.

12 pF

Drive Level

350 µW

Operation Temperature Range

Aging

0

°C~ +70 °C

+3 ppm/year

Reset Generation

GX3 integrates an on-chip power-on-reset circuit, which simplifies the external reset circuitry on the board. The power-on-reset circuit

generates a reset pulse after 1.2 V core power ramps up to 0.72 V (typical threshold). The external reset pin, RESET#, can be directly

connected to the input of the power-on-reset circuit and can also be used as an additional hardware reset source. For more details

on RESET# timing, please refer to Reset Timing on page 28.

Document Number: 001-94768 Rev. *C

Page 10 of 35

CYUSB3610

Default Wake-On-LAN (DWOL) Ready Mode

This Default WOL Ready Mode application is different from normal operation where GX3 Suspend/Resume state usually has to be

configured by software driver during normal system operation. This application applies to a system that uses a predefined remote

wakeup event to turn on the system power supply and its peripheral circuits without having any system software running in the

beginning. This is quite useful when a system has been powered down already and a user needs to power on the system remotely.

GX3 can be configured to support Default WOL Ready Mode, where no system driver is required to configure its WOL related settings

after power on reset. A system design usually partitions its power supply into two or more groups and the GX3 is supplied with an

independent power separated from the system processor. The power supply of GX3 is usually available as soon as power plug is

connected. The power supply of system processor remains off initially when power plug is connected and is controlled by GX3’s PME

pin, which can be activated whenever GX3 detects a pre-defined wakeup event such as valid Magic Packet reception or the WAKEUP#

pin trigger. To reduce power consumption, initially the USB host controller communicating with GX3 can also be unpowered as the

system processor.

The PME pin of GX3 can control the power management IC (PMIC) to power up the system processor along with the USB host

controller, which will perform USB transactions with GX3 after both have been initialized. The pin polarity of PME is configured as

high active when enabling Default WOL Ready Mode. Note that the GX3 must be in self-power (via setting EEPROM Flag [0]) mode

for this function.

Procedure to Enable Default WOL Ready Mode

EN

PMIC

vcc

4.7k

VBUS

PME

GX3

Appilcation

Processor

GPIO[1]

RESET#

USB

Host

DP/DM

WAKEUP#

To enable Default WOL Ready Mode, configure GPIO[0] pin as PME (via setting EEPROM Flag [12]) and have GPIO[1] pulled-up

with a 4.7K resistor. After power on reset, GX3 will disable most functions including USB transceiver (see Note 2) but enable Magic

Packet detector logic, internal Ethernet PHY and its auto-negotiation function to be ready to

receive Magic Packet. When a valid Magic Packet is received, GX3 will assert the PME pin to indicate to system processor the wakeup

event. The PME pin, when being configured as static level output signal (via setting EEPROM Flag [15], see Note 3), can be used to

control the power management IC to enable system power supply. After asserting the PME pin, GX3 will also exit from the Default

WOL Ready Mode and revert back to normal operation mode to start normal USB device detection, handshaking, and enumeration.

The PME pin, when being configured as static level output signal, maintains its signal level until RESET# is asserted again. If RESET#

to GX3 is asserted with GPIO[1] pulled-up, the Default WOL Ready Mode will be re-entered. Otherwise (GPIO[1] being pulled-down),

it will enter into normal operation mode and the normal USB device detection, handshaking and enumeration process should take

place right after RESET# negation.

Notes

1. For complete truth table of wakeup events supported, please refer to below on the “GPIO[1] = 1” setting.

2. When the Default WOL Ready Mode is enabled, the DP/DM pins of GX3 will be in tri-state.

3. Please refer to Flag (EEPROM: 05h) on page 15. The bit [15:12] of Flag (PME_IND, PME_TYP, PME_POL, PME_PIN) = 0111.

4. It is recommended that VBUS pin be connected to system power group directly. This way the VBUS will become HIGH when power management IC enables the

system power supply.

Document Number: 001-94768 Rev. *C

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CYUSB3610

Flow Chart of Default WOL Ready Mode

(1) Operation Mode setting by Pin#19, #21

(2) Set GPIO_0 as PME definition

(3) Pull-up GPIO[1] to enable Default WOL Ready mode.

(4) Power on reset, either by on-chip power-on reset circuit or RESET# pin.

The Default WOL Ready Mode is enabled.

NO

Wakeup event asserts?

YES

(1) PME asserts with static level that is used as power

control to system processor.

(2) Default WOL Ready Mode is disabled.

System processor powers on and supplies VBUS

to GX3.

GX3 is in normal operation mode.

NO

Assert RESET# and

GPIO[1] = 1?

YES

(1) PME de-asserts.

(2) The Default WOL Ready Mode is

enabled.

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CYUSB3610

Serial EEPROM Memory Map

Table 6. Serial EEPROM Memory Map

EEPROM OFFSET

HIGH BYTE

LOW BYTE

Node ID 0 (Note 6)

00h

01h

02h

03h

04h

05h

06h

Node ID

1

3

5

Node ID

2

4

PID_HB

VID_HB

Flag

PID_LB

VID_LB

EEPROM Checksum (Note 7)

Reserved

07h

08h

Max. Power for Self Power

EndPoint1 for SS/HS

Max. Power for Bus Power

EndPoint1 for FS

09h

Language ID High Byte

Language ID Low Byte

Offset of Product String (0Eh)

Offset of Manufacturer String (1Ah)

Offset of Serial Number String (26h)

Offset of BOS-type Descriptor (2Dh)

0Ah

Length of Product String (bytes)

Length of Manufacturer String (bytes)

Length of Serial Number String (bytes)

Length of BOS-type Descriptor (bytes)

0Bh

0Ch

0Dh

19~0Eh

25~1Ah

2C~26h

3B~2Dh

3Ch

Product String: (Max.) 24 bytes

Manufacturer String: (Max.) 24 bytes

Serial Number String: (Max.) 14 bytes

BOS-type Descriptor: (Max.) 30 bytes

Reserved

Max. Burst: [7:4] for EP3, [3:0] for EP2

Fixed_pattern (10 bytes)

41~3Dh

42h

LED_Mode_HB

LED_Mode_LB

Notes

6. The Node ID 0 value cannot be set to 0xFF and 1st bit of Node ID 0 cannot be set to “1” (i.e. cannot be set to multicast MAC address).

7. The value of EEPROM Checksum field located at EEPROM offset 05h (low byte). The correct value must be equal to (0xFF - SUM [EEPROM offset 03h ~ 04h]). If

SUM [EEPROM offset 03h ~ 04h] has carry, please add ‘1’ to its result.

8. Total usage is about 134 bytes.

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CYUSB3610

Detailed Description

The following sections provide detailed descriptions for some of the fields in memory maps of serial EEPROM.

Node ID (00~02h)

The Node ID 0 to 5 bytes represent the MAC address of the device, for example, if MAC address = 04-23-45-67-89-AB, then Node

ID 0 = 04h, Node ID 1 = 23h, Node ID 2 = 45h, Node ID 3 = 67h, Node ID 4 = 89h, and Node ID 5 = ABh.

Default values: Node ID {0, 1, 2, 3, 4, 5} = 00-0E-C6-F9-D0-00.

Flag (EEPROM: 05h)

Table 7. Flag (EEPROM: 05h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PME_IND

PME_TYPE

PME_POL

PME_PIN

0

WOLLP

RWU

RWU: Remote Wakeup support.

1: Indicate that this device supports Remote Wakeup (default).

0: Not supported.

WOLLP: Wake-On-LAN Low Power function.

1: Enabled (default).

0: Disabled.

PME_PIN: PME / GPIO[0].

1: Set GPIO[0] pin as PME (default).

0: GPIO[0] pin is controlled by vendor command.

PME_POL: PME pin active Polarity.

1: PME active high (default).

0: PME active low.

PME_TYP: PME I/O Type.

1: PME output is a Push-Pull driver (default).

0: PME output to function as an open-drain buffer.

PME_IND: PME indication.

1: A 1.363 ms pulse active when detecting wake-up event.

0: A static signal active when detecting wake-up event (default).

Max. Power for Self/Bus Power (07h)

They are Max power values’ setting of powered device for EEPROM at offset 07h.

The default value of Bus Power is 3Eh.

For USB 3.0, the power value is 496 mA (Unit = 8 mA).

For USB 2.0, the power value is 248mA (Unit = 4 mA).

Self power setting follows conversion above.

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CYUSB3610

EndPoint1 for SS/HS/FS (EEPROM:08h)

The time interval (named “bInterval”) for polling Interrupt IN endpoint 1 for data transfers of SuperSpeed/High-Speed/Full-Speed is

stored at EEPROM offset 08h. It is expressed in frames or microframes depending on the device operating speed (i.e. either

1 millisecond or 125 μs units).

The default “bInterval” value is 0Bh for Super-Speed/High-Speed (the polling time of endpoint 1 = 2^(11-1)× 125 μs =128 ms) and is

80h for Full-Speed (the polling time of endpoint 1 = 128 × 1 ms = 128 ms).

Max. Burst for EP3/EP2 (EEPROM: 3Ch)

This value is bMaxBurst field in SS endpoint companion descriptor.

LED Mode (EEPROM: 42h)

LED Mode defines the indication setting for LED_0/1/2/3 function of MFA[0/1/2/3] pins.

Table 8. Bit 7~Bit 0: LED_Mode_LB

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

LED1_100

LED1_10

LED1_Active LED0_Duplex LED0_1000

LED0_100

LED0_10

LED0_Active

Table 9. Bit 15~Bit 8: LED_Mode_HB

Bit15

Bit14

Bit13

Bit12

Bit11

Bit10

Bit9

Bit8

1

LED2_Duplex LED2_1000

LED2_100

LED2_10

LED2_Active LED1_Duplex LED1_1000

Note: Bit 15 must be ‘1’ to enable the LED_mode setting; otherwise, it will work at default LED mode.

The LED mode table is as below:

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CYUSB3610

Table 10. LED Mode Setting Table

Full duplex

Link speed (Mbps)

Active

Description of Indication

(TX/RX)

1000

100

2

10

1

Bit

4

3

0

LED_0

0

USB3.0 Super Speed: It turns ON when device

operates at USB3.0 Super Speed.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Active (Default for LED0)

Link 10

Link 10+Active

Link 100

Link 100+Active

Link 100/10

Link 100/10+Active

Link 1000

Link 1000+Active

Link 1000/10

Link 1000/10+Active

Link 1000/100

Link 1000/100+Active

Link 1000/100/10

Link 1000/100/10+Active

Full duplex

Bit

9

8

7

6

5

LED_1

0

USB3.0 Super Speed: It turns ON when device

operates at USB3.0 Super Speed.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Active

Link 10

Link 10+Active

Link 100

Link 100+Active

Link 100/10

Link 100/10+Active

Link 1000

Link 1000+Active

Link 1000/10

Link 1000/10+Active

Link 1000/100

Link 1000/100+Active

Link 1000/100/10

Link 1000/100/10+Active

Full duplex

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Table 10. LED Mode Setting Table (continued)

Link speed (Mbps)

Active

Full duplex

Description of Indication

(TX/RX)

1000

13

100

12

0

10

11

0

Bit

14

10

LED_2

0

USB3.0 Super Speed: It turns ON when device

operates at USB3.0 Super Speed.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Active

Link 10

Link 10+Active

Link 100

Link 100+Active

Link 100/10

Link 100/10+Active

Link 1000

Link 1000+Active

Link 1000/10

Link 1000/10+Active

Link 1000/100

Link 1000/100+Active

Link 1000/100/10

Link 1000/100/10+Active

Full duplex

Bit

4

3

2

1

0

LED_3

0

1

USB3.0 Super Speed: The LED_0 mode MUST

be set to “Active” only when the LED_3 is used.

It will be ON when device operates at USB3.0

and

keep

flashing

when

device

is

receiving/transmitting packets.

Fixed_pattern (EEPROM: 41~3Dh)

Please write these 10 bytes of fixed_pattern with hexadecimal (from low bytes to high bytes) = “40 4A 40 00 40 30 0D 49 90 41”.

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CYUSB3610

Internal Memory Description

The internal Memory data is a fixed value. User can’t modify it.

Table 11. Internal Memory Description

Field Definition

Default Values

00 0E C6 F9 D0 00

Description

Node ID

Node ID 0 ~ 5

PID of GX3

Product ID (PID)

Vender ID (VID)

10 36

B4 04

Cypress VID

Flag - Remote Wakeup and PME 73

setting, etc.

Enable the “remote wakeup” and Low

Power WOL function (Note 9)

Max Power for Bus Power

3E

496 mA for USB 3.0

248 mA for USB 2.0

(Note 10)

Max Power for Self Power

01

8 mA for USB 3.0

4 mA for USB 2.0

(Note 10)

Length of Product String

03

Product String Length (Note 11)

Manufacturer String Length (Note 11)

“GX3”

Length of Manufacturer String

Product String (Max. 12 bytes)

07

41 58 33 00 00 00 00 00 00 00 00 00

43 79 70 72 65 73 73 00 00 00

Manufacture String (Max. 10

bytes)

“Cypress”

Fixed Pattern

40 4A 40 00 40 30 0D 49 90 41

Fixed pattern to be written

External EEPROM Description

User can assign the specific VID/PID, Serial Number, Manufacture String, Product String, etc. user defined fields by external

EEPROM. Please refer to GX3 EEPROM User Guide document for more details about how to configure GX3 EEPROM content.

Note the EEPROM checksum field should be changed together with the VID/PID fields.

Notes

9. Remote Wakeup/PME Settings

The offset 05h field of GX3 EEPROM is used to configure the Remote Wakeup and PME functions. Please refer to Serial EEPROM Memory Map on page 14 for the

detailed description of EEPROM offset 05h.

The RWU bit of GX3 EEPROM offset 05h is used to configure the “bmAttributes” field of Standard Configuration Descriptor that will be reported to the USB host

controller when the GET_DESCRIPTOR command with CONFIGURATION type is issued. Please refer to “Section 9.6.3 Configuration” of Universal Serial Bus 3.0

Spec for the detailed description of the “bmAttributes” field of Standard Configuration Descriptor.

The power mode about Bus-powered or Self-powered is decided by the SELF_PWR pin when chip powers on. This will be updated to the “bmAttributes” field of

Standard Configuration Descriptor.

10. Max Power Setting

The low byte of GX3 EEPROM offset 07h (for bus-powered) field and high byte of GX3 EEPROM offset 07h (for self-powered) field are used to configure the

“bMaxPower” field of Standard Configuration Descriptor that will be reported to the USB host controller when the GET_DESCRIPTOR command with

CONFIGURATION type is issued. Please refer to “Section 9.6.3 Configuration” of Universal Serial Bus 3.0 Spec for the detailed description of the “bMaxPower” field

of Standard Configuration Descriptor. These fields are used to define the Maximum power consumption of the USB device drawn from the USB bus in this specific

configuration when the device is fully operational.

11. Product/Manufacturer/Serial Number String Settings

The “Offset” fields of Product/Manufacturer/Serial Number String are fixed in GX3 EEPROM memory map. Please DO NOT change the recommended values of these

fields.

If you need to change the Product/Manufacturer/Serial Number strings on your GX3 EEPROM, please modify the “Length” fields of Product/Manufacturer/Serial

Number String to meet the exact string length of your Product/Manufacturer/Serial Number strings.

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CYUSB3610

USB Configuration Structure

GX3 supports only one USB configuration, one interface and four USB endpoints. The four endpoints are defined as below:

■ Endpoint 0: Control endpoint. It is used for configuring the device.

■ Endpoint 1: Interrupt endpoint. It is used for reporting network Link status.

■ Endpoint 2: Bulk IN endpoint. It is used for receiving Ethernet Packet.

■ Endpoint 3: Bulk OUT endpoint. It is used for transmitting Ethernet Packet.

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CYUSB3610

Electrical Specifications

DC Characteristics

Absolute Maximum Ratings

Table 12. Absolute Maximum Ratings

Symbol

Parameter

Rating

Unit

V

VCCK

Digital core power supply

–0.5 to 1.44

–0.5 to 1.6

–0.1 to 1.26

–0.5 to 4.2

–0.5 to 4.6

–0.4 to 3.7

–0.5 to 4.2

–0.5 to 5.8

U3TXVDDQ

U3RXVDDQ

E12VDDQ

E12VCC

VIO33

Analog Power for USB Transceiver. 1.2 V

Analog Power for Ethernet PHY. 1.2 V

Power supply of 3.3 V I/O

V

CVDDQ

A3V3

Power supply of 3.3 V for clock pin.

Analog Power 3.3 V for USB Transceiver.

Analog Power for Ethernet PHY. 3.3 V

Input voltage of 3.3 V I/O

V

E33VDDQ

E33VCC

V_IN3

V

Input voltage of 3.3 V I/O with 5 V tolerant

Storage temperature

V

TSTG

I_IN

–65 to 150 °C

DC input current

50

mA

I_OUT

Output short circuit current

Notes:

1.Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to the

optional sections of this datasheet. Exposure to absolute maximum rating condition for extended periods may affect device reliability.

2. The input and output negative voltage ratings may be exceeded if the input and output currents under ratings are observed.

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CYUSB3610

Recommended Operating Conditions

Table 13. Recommended Operating Conditions

Symbol

VCCK

Parameter

Min

1.14

3.13

2.97

3.13

–

Typ

1.2

3.3

–

Max

1.26

3.47

3.63

3.47

5.25

125

Unit

V

Digital core power supply

U3TXVDDQ

U3RXVDDQ

E12VDDQ

E12VCC

VIO

Analog Power for USB Transceiver. 1.2 V

Analog Power for Ethernet PHY. 1.2 V

Power supply of 3.3 V I/O

V

CVDDQ

A3V3

Power supply of 3.3 V for clock pin.

Analog Power 3.3 V for USB Transceiver.

Analog Power for Ethernet PHY. 3.3 V

Input voltage of 3.3 V I/O

V

E33VDDQ

E33VCC

V^IN3

V

Input voltage of 3.3 V I/O with 5 V tolerance

Maximum junction operating temperature

Ambient operating temperature

V

T^j

°C

T^a

0

–

70

Leakage Current and Capacitance

Table 14. Leakage Current and Capacitance

Symbol

Parameter

Conditions

V_IN= 3.3 V or 0 V

Min

Typ

Max

Unit

I^IN

True 3.3 V I/O input leakage

current

–

≤±1

–

μA

V_IN5 V or 0 V

=

3.3 V with 5 V tolerance I/O input

leakage current

–

<±1

–

pF

C^IN

Input capacitance

3.3 V I/O cells

–

2.25

3.6

–

pF

3.3 V with 5 V tolerant I/O cells

Note: C_INincludes the cell layout capacitance and pad capacitance (Estimated to be 0.5 pF).

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CYUSB3610

DC Characteristics of 3.3 V I/O Pins

Table 15. DC Characteristics of 3.3 V I/O Pins

Symbol

Parameter

Input low voltage

Conditions

Min

–

Typ

–

Max

0.8

–

Unit

V

Vil

LVTTL

Vih

Vt-

Input high voltage

2.0

0.8

–

V

Schmitt trigger negative going

threshold voltage

1.1

–

V

Vt+

Vol

Schmitt trigger positive going

threshold voltage

–

1.6

2.0

V

Output low voltage

Output high voltage

|Iol| = 4~8mA

–

0.4

–

V

Voh

Vopu ^[12]

|Ioh| = 4~8mA

2.4

Output pull-up voltage for 5 V

tolerance I/O cells

PU = High, PD = Low E = 0,

|I | = 1 μA

pu

V_IO

–

0.9

–

Rpu

Rpd

Input pull-up resistance

PU = High, PD = Low

PU = Low, PD = High

40

75

190

KΩ

Input pull-down resistance

Note

12. This parameter indicates that the pull-up resistor for the 5 V tolerance I/O cells cannot reach the V DC level even without the DC loading current.

IO

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CYUSB3610

Thermal Characteristics

Table 16. Thermal Characteristics

Description

Thermal resistance of junction to case

Thermal resistance of junction to ambient

Symbol

_JC

Rating

8.3

Units

C/W

°

_JA

21.4

°

Note: _JA, _JCdefined as below



_JA= (T_J– T_A) / P

_JC= (T_J– T_C) / P



T_J: maximum junction temperature (°C)

T_A: ambient or environment temperature (°C)

T_C: the top centre of compound surface temperature (°C)

P: input power (watts)

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CYUSB3610

Power Consumption

Table 17. Power Consumption

Symbol

I_VCC12

Description

Conditions

Min

–

Typ

335

67

Max

–

Unit

mA

Current Consumption at 1.2 V

Current Consumption at 3.3 V

Operating at Ethernet 1 Gbps (full

duplex) mode and USB Super

Speed mode

I_VCC33

–

mA

I_VCC12

I_VCC33

Current Consumption at 1.2 V

Current Consumption at 3.3 V

Operating at Ethernet 100 Mbps

full duplex mode and USB Super

Speed mode

–

189

41

–

mA

I_VCC12

I_VCC33

Current Consumption at 1.2 V

Current Consumption at 3.3 V

Operating at Ethernet 10 Mbps

half duplex mode and USB Super

Speed mode

–

151

48

–

mA

I_VCC12

I_VCC33

Current Consumption at 1.2 V

Current Consumption at 3.3 V

Operating at Ethernet 1 Gbps

(full duplex) mode and USB High

Speed mode

–

228

79

–

mA

I_VCC12

I_VCC33

Current Consumption at 1.2 V

Current Consumption at 3.3 V

Operating at Ethernet 100 Mbps

full duplex mode and USB High

Speed mode

–

85

50

–

mA

I_VCC12

I_VCC33

Current Consumption at 1.2 V

Current Consumption at 3.3 V

Operating at Ethernet 10 Mbps

half duplex mode and USB High

Speed mode

–

48

53

–

mA

I_VCC12

I_VCC33

Current Consumption at 1.2 V

Current Consumption at 3.3 V

Operating at Ethernet 1 Gbps

(full duplex) mode and USB Full

Speed mode

–

216

63

–

mA

I_VCC12

I_VCC33

Current Consumption at 1.2 V

Current Consumption at 3.3 V

Operating at Ethernet 100 Mbps

full duplex mode and USB Full

Speed mode

–

77

40

–

mA

I_VCC12

I_VCC33

Current Consumption at 1.2 V

Current Consumption at 3.3 V

Operating at Ethernet 10 Mbps

half duplex mode and USB Full

Speed mode

–

42

46

–

mA

I_VCC12

I_VCC33

Current Consumption at 1.2 V

Current Consumption at 3.3 V

Ethernet unlink (Disable

AutoDetach) and USB Super

Speed mode

–

151

29

–

mA

I_VCC12

I_VCC33

I_VCC12

I_VCC33

Current Consumption at 1.2 V

Current Consumption at 3.3 V

Current Consumption at 1.2 V

Current Consumption at 3.3 V

Ethernet unlink (Enable

AutoDetach)

–

23

12

–

mA

USB Suspend and Ethernet is

1 Gbps: enable Remote WakeUp

and disable WOLLP (WOL Low

Power)

200

47

I_VCC12

I_VCC33

Current Consumption at 1.2 V

Current Consumption at 3.3 V

USB Suspend and enable

Remote WakeUp and enable

WOLLP to 10Mbps

–

25

13

–

mA

I_VCC12

I_VCC33

Current Consumption at 1.2 V

Current Consumption at 3.3 V

Suspend and disable Remote

WakeUp (Refer to below

–

1.5

1.7

–

mA

I_{SYSTEM(Suspend)}item for total

power consumption at Suspend

mode)

IDLE Power Consumption for Etherent Linked in EEE / non-EEE

I_VCC12

I_VCC33

Current Consumption at 1.2 V

Current Consumption at 3.3 V

Operating at Ethernet 1 Gbps

mode and USB Super Speed

mode (Ethernet linked in EEE)

–

177

32

–

mA

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CYUSB3610

Table 17. Power Consumption (continued)

Symbol

I_VCC12

Description

Conditions

Min

–

Typ

320

66

Max

–

Unit

mA

Current Consumption at 1.2 V

Current Consumption at 3.3 V

Operating at Ethernet 1 Gbps

mode and USB Super Speed

mode (Ethernet linked in

non-EEE)

I_VCC33

–

mA

I_VCC12

I_VCC33

Current Consumption at 1.2 V

Current Consumption at 3.3 V

USB Suspend and enable

RemoteWakeUp(Ethernetlinked

in EEE 1Gbps mode)

–

56

–

mA

0.4

Green Ethernet Cable-Length Power Saving (GEPS)

I_VCC12

I_VCC33

Current Consumption at 1.2 V

Current Consumption at 3.3 V

Operating at Ethernet 1 Gbps

mode @ 1.5 meters and USB

Super Speed mode (Enable

GEPS)

–

320

66

–

mA

I_VCC12

I_VCC33

Current Consumption at 1.2 V

Current Consumption at 3.3 V

Operating at Ethernet 1 Gbps

mode @ 1.5 meters and USB

Super Speed mode (Disable

GEPS)

–

328

69

–

mA

I_DEVICE

1.2V/3.3Vpowerconsumptionat 1.2 V (Operating at Super

–

335

67

–

mA

full loading (chip only)

Speed/1 Gbps mode)

3.3 V (Operating at Super

Speed/1 Gbps mode)

I_SYSTEM

Total power consumption at full VBUS of 5.0 V ((Operating at

161

loading (demo board)

Super Speed/1 Gbps mode),

(Using Switching regulator with

dual VOUT 3.3/1.2 V))

I_{SYSTEM(Suspend)}Total power consumption at

Suspend mode (demo board)

VBUS of 5.0 V ((Disable Remote

WakeUp), (Using Switching

regulator with dual VOUT

3.3/1.2 V))

–

1.92

–

mA

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CYUSB3610

Power-up Sequence

At power-up, the GX3 requires the A3V3/CVDDQ/VIO/E33VDDQ/E33VCC power supply to rise to nominal operating voltage within

Trise3 and the VCC12 (Note) power supply to rise to nominal operating voltage within Trise2.

Trise3

3.3 V

A3V3/CVDDQ/VIO/

E33VDDQ/E33VCC

0 V

Tdelay32

Trise2

1.2 V

VCC12

0 V

Trst_pu

RESET#

Tclk

XTALIN/

XTALOUT

Note: The VCC12 includes VCCK, E12VCC, and E12VDDQ/TX/RX.

Table 18. Power-up Sequence Parameters

Symbol

T^rise3

Parameter

Condition

From 0 V to 3.3 V

From 0 V to 1.2 V

Min

–

Typ

–

Max

10

5

Unit

ms

3.3 V power supply rise time

1.2 V power supply rise time

3.3 V rise to 1.2 V rise time delay

T^rise2

–

T^delay32

–5

–

1 ^[14]

25 MHz crystal oscillator stable FromVCC3IO= 3.3V to stableclock

time period of XTALIN or XTALOUT

–

T^clk

RESET# low level interval time From VCC12 = 1.2 V and

from power-up VCC3IO = 3.3 V to RESET# going

high

0 ^[13]

–

10

ms

T^rst_pu

Notes

13. When the VCC12 power-up, the internal power-on-reset circuit will generate a few us (micro second) of hardware reset to chip and will start operation after the

XTALIN/N 25 MHz clock signals are stable.

14. The Tclk timing is depended on the 25 MHz crystal circuit. The 1 ms Tclk timing is reference timing based on the GX3 reference 25 MHz crystal circuit. Please refer

to GX3 reference schematic for details.

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CYUSB3610

AC Timing Characteristics

Notice that the following AC timing specifications for output pins are based on CL (Output load) equal to 50 pF.

Clock Timing

Table 19. Clock Timing Parameters

Symbol

T^P_XTALIN

T^H_XTALIN

T^L_XTALIN

Parameter

XTALIN clock cycle time

XTALIN clock high time

XTALIN clock low time

Condition

Min

–

Typ

40.0

20.0

Max

Unit

ns

–

ns

–

ns

Reset Timing

XTALIN

RESET#

Trst

Table 20. Reset Timing Parameters

Symbol

Trst

Description

Min

Typ

Max

Unit

Reset pulse width after XTALIN is

running

125

–

250000 XTALIN clock cycle ^[15]

Note

15. If the system applications require using hardware reset pin, RESET#, to reset GX3 during device initialization or normal operation after VBUS pin is asserted, the

above timing spec (Min = 5 μs, Max =10 ms) of RESET# should be met.

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CYUSB3610

Serial EEPROM Timing

Table 21. Serial EEPROM Timing Parameters

Symbol

Tclk

Description

Min

–

Typ

Max

–

Unit

ns

SCK clock cycle time

5120

Tch

Tcl

SCK clock high time

–

2560

–

SCK clock low time

–

2560

–

Tdv

Tod

Tscs

Thcs

Tlcs

Ts

SDA output valid to SCK rising edge time

SCK rising edge to SDA output delay time

CS output valid to SCK rising edge time

SCK falling edge to CS invalid time

Minimum CS low time

2560

2562

2560

7680

23039

20

–

SDA input setup time

–

Th

SDA input hold time

0

–

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CYUSB3610

Package Information

68-pin QFN 8 × 8 package

Figure 2. 68-pin QFN (8 × 8 × 0.85 mm) LT68D 6.2 × 6.2 mm E-Pad (Sawn Type) Package Outline, 001-96836

001-96836 **

Document Number: 001-94768 Rev. *C

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CYUSB3610

Recommended PCB Footprint for 68-pin QFN 8x8 package

Table 22. Details

Symbol

Description

Typical Dimension

0.40 mm

e

b

Lead pitch

Pad width

0.23 mm

L

Pad length

0.80 mm

U

V

W

–

6.30 mm

6.63 mm

7.20 mm

Document Number: 001-94768 Rev. *C

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CYUSB3610

Ordering Information

Table 23. Ordering Information

Part Number

Description

CYUSB3610-68LTXC

68 PIN, QFN Package, Commercial Grade Temperature Range 0 °C to +70 °C (Green, Lead-Free)

Document Number: 001-94768 Rev. *C

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CYUSB3610

Acronyms

Document Conventions

Units of measure

Acronym

Description

Checksum Offload Engine

Energy Efficient Ethernet

COE

EEE

Symbol

°C

Unit of measure

degree Celsius

gigabits per second

kilohm

GPIO

MDI

General Purpose Input Output

Medium Dependent Interface

No Connection

Gbps

kΩ

NC

Mbps

MHz

µW

mA

mm

ms

megabits per second

megahertz

RISC

USB

UTP

Reduced Instruction Set Computer

Universal Serial Bus

microwatt

Unshielded Twisted Pair

Virtual Local Area Network

Wake-On LAN

milliampere

millimeter

VLAN

W-LAN

millisecond

nanosecond

picofarad

ns

pF

ppm

V

parts per million

volt

Document Number: 001-94768 Rev. *C

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CYUSB3610

Document History Page

Document Title: CYUSB3610, EZ-USB GX3: SuperSpeed USB to Gigabit Ethernet Bridge Controller

Document Number: 001-94768

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

4703075

4870097

5713474

6192311

RAJV

MDDD

05/29/2015 New data sheet.

*A

*B

*C

08/03/2015 Changed status from Preliminary to Final.

04/26/2017 Updated logo and Copyright.

AESATMP8

MDDD

05/31/2018 Updated to new template.

Completing Sunset Review.

Document Number: 001-94768 Rev. *C

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CYUSB3610

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

Arm^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Technical Support

Internet of Things

Memory

cypress.com/support

cypress.com/memory

cypress.com/mcu

Microcontrollers

PSoC

cypress.com/psoc

cypress.com/pmic

cypress.com/touch

cypress.com/usb

Power Management ICs

Touch Sensing

USB Controllers

Wireless Connectivity

cypress.com/wireless

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 001-94768 Rev. *C

Revised May 31, 2018

Page 35 of 35

厂商	型号	描述	页数
CYPRESS	CYU001M16OFFA-85BVI	[ Pseudo Static RAM, 1MX16, 85ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, BGA-48 ]	14 页
CYPRESS	CYU01M16SCCU	16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ]	12 页
CYPRESS	CYU01M16SCCU-70BVXI	16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ]	12 页
CYPRESS	CYU01M16SCE	16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ]	11 页
CYPRESS	CYU01M16SCEU-70BVXI	16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ]	11 页
CYPRESS	CYU01M16SCEU-70BVXIT	[ Pseudo Static RAM, 1MX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48 ]	11 页
CYPRESS	CYU01M16SCG	16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ]	11 页
CYPRESS	CYU01M16SCG-70BVXI	16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ]	11 页
CYPRESS	CYU01M16SFCU	16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ]	12 页
CYPRESS	CYU01M16SFCU-70BVXI	16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ]	12 页