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SZPACDN004

型号:

SZPACDN004

品牌:

ONSEMI[ ONSEMI ]

页数:

7 页

PDF大小:

102 K

PACDN004, SZPACDN004  
2-Channel ESD Protection  
Array  
Product Description  
The PACDN004 is a diode array designed to provide two channels  
of ESD protection for electronic components or sub−systems. Each  
channel consists of a pair of diodes which steers the ESD current pulse  
www.onsemi.com  
either to the positive (V ) or negative (V ) supply. The PACDN004  
P
N
will protect against ESD pulses up to 15 kV Human Body Model,  
and 8 kV contact discharge per International Standard  
IEC 61000−4−2.  
SOT−143  
PACDN004SR  
CASE 527AF  
SOT−143  
SZPACDN004SR  
CASE 318A  
This device has identical characteristics as the PACDN006  
(6−channel array). They can be used together in order to provide  
a larger number of protected inputs if required. This device is  
particularly well−suited for a wide range of portable electronics  
(e.g. cellular phones, PDAs, notebook computers) because of its small  
package footprint, high ESD protection level and low loading  
capacitance. It is also suitable for protecting video output lines and I/O  
ports in computers and peripherals.  
SIMPLIFIED ELECTRICAL SCHEMATIC  
V
P
4
The PACDN004 is available with RoHS compliant lead−free  
finishing.  
2
3
CH1  
CH2  
Features  
Two Channels of ESD Protection  
8 kV Contact, 15 kV Air ESD Protection per Channel  
(IEC 61000−4−2 Standard)  
1
15 kV of ESD Protection per Channel (HBM)  
V
N
Low Loading Capacitance of 3 pF Typical  
Low Leakage Current is Ideal for Battery−Powered Devices  
Miniature 4−Pin SOT−143 Package  
MARKING DIAGRAM  
SZ Prefix for Automotive and Other Applications Requiring Unique  
Site and Control Change Requirements; AEC−Q101 Qualified and  
PPAP Capable  
D014  
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS  
D014  
= PACDN004SR  
Compliant  
Applications  
ORDERING INFORMATION  
Consumer Electronic Products  
Cellular Phones  
PDAs  
Notebook Computers  
Desktop PCs  
Digital Cameras and Camcorders  
VGA (Video) Port Protection for Desktop and Portable PCs  
Device  
Package  
Shipping  
PACDN004SR  
SOT−143 3000/Tape & Reel  
(Pb−Free)  
SZPACDN004SR  
SOT−143 3000/Tape & Reel  
(Pb−Free)  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
© Semiconductor Components Industries, LLC, 2015  
1
Publication Order Number:  
July, 2015 − Rev. 5  
PACDN004/D  
PACDN004, SZPACDN004  
TYPICAL APPLICATION CIRCUIT  
V
CC  
1
4
0.22 mF*  
PACDN004  
2
Video  
Driver  
Camera  
Video  
NTSC Video  
Connector  
Digital Camera Video Port  
ESD Protection  
* Decoupling capacitor must be placed as close as possible to Pin4.  
PACKAGE / PINOUT DIAGRAM  
Top View  
V
1
2
4
3
V
P
N
CH1  
CH2  
SOT−143  
Table 1. PIN DESCRIPTIONS  
PACDN004 (SOT−143)  
Pin  
1
Name  
Type  
GND  
I/O  
Description  
V
N
Negative Voltage Supply Rail or Ground Reference Rail  
ESD Channel 1  
2
CH1  
CH2  
3
I/O  
ESD Channel 2  
4
V
P
Supply  
Positive Voltage Supply Rail  
www.onsemi.com  
2
PACDN004, SZPACDN004  
SPECIFICATIONS  
Table 2. ABSOLUTE MAXIMUM RATINGS  
Parameter  
Rating  
6.0  
Units  
V
Supply Voltage (V − V )  
P
N
Diode Forward DC Current (Note 1)  
Operating Temperature Range  
Storage Temperature Range  
DC Voltage at any Channel Input  
Package Power Rating  
20  
mA  
°C  
−40 to +85  
−65 to +150  
°C  
(V − 0.5) to (V + 0.5)  
V
N
P
225  
mW  
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality  
should not be assumed, damage may occur and reliability may be affected.  
1. Only one diode conducting at a time.  
Table 3. STANDARD OPERATING CONDITIONS  
Parameter  
Rating  
−40 to +85  
0 to 5.5  
Units  
°C  
Operating Temperature Range  
Operating Supply Voltage (V − V )  
V
P
N
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond  
the Recommended Operating Ranges limits may affect device reliability.  
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)  
Symbol  
Parameter  
Supply Current  
Conditions  
(V − V ) = 5.5 V  
Min  
Typ  
Max  
10  
Units  
mA  
I
P
P
N
V
Diode Forward Voltage  
I = 20 mA  
0.65  
0.95  
1.0  
5
V
F
F
I
Channel Leakage Current  
Channel Input Capacitance  
0.1  
3
mA  
LEAK  
C
@ 1 MHz, V = 5 V,  
pF  
IN  
P
V
N
= 0 V, V = 2.5 V  
IN  
V
ESD  
ESD Protection  
kV  
Peak Discharge Voltage at any  
Channel Input, in System  
a) Human Body Model,  
MIL−STD−883, Method 3015  
b) Contact Discharge per  
IEC 61000−4−2 Standard  
(Note 2)  
(Notes 2 and 3)  
(Notes 2 and 4)  
15  
8
c) Air Discharge per IEC 61000−4−2 (Notes 2 and 4)  
15  
V
CL  
Channel Clamp Voltage  
@ 15 kV ESD HBM  
(Notes 2 and 3)  
V
Positive Transients  
Negative Transients  
V
P
V
N
+ 13.0  
− 13.0  
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
1. All parameters specified at T = 25°C unless otherwise noted. V = 5 V, V = 0 V unless noted.  
A
P
N
2. From I/O pins to V or V only. V bypassed to V with a 0.22 mF ceramic capacitor (see Application Information for more details).  
P
N
P
N
3. Human Body Model per MIL−STD−883, Method 3015, C  
= 100 pF, R  
= 330 W, V = 5.0 V, V grounded.  
= 1.5 kW, V = 5.0 V, V grounded.  
Discharge  
Discharge P N  
4. Standard IEC 61000−4−2 with C  
= 150 pF, R  
Discharge  
Discharge P N  
www.onsemi.com  
3
 
PACDN004, SZPACDN004  
PERFORMANCE INFORMATION  
Input Capacitance vs. Input Voltage  
Figure 1. Typical Variation of CIN vs. VIN  
(VP = 5 V, VN = 0 V, 0.1 mF Chip Capacitor between VP and VN)  
APPLICATION INFORMATION  
Design Considerations  
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic  
series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically  
a connector) and the ESD protection device. Refer to Application of Positive ESD Pulse between Input Channel and Ground,  
which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power  
supply is represented by L and L . The voltage V on the line being protected is:  
1
2
CL  
VCL + FwdVoltageDropofD1 ) VSUPPLY ) L1   d(IESD)ńdt ) L2   d(IESD)ńdt  
is the ESD current pulse, and V is the positive supply voltage.  
where I  
ESD  
SUPPLY  
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge  
per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(I )/dt can be  
ESD  
−9  
approximated by DI  
/Dt, or 30/(1x10 ). So just 10 nH of series inductance (L and L combined) will lead to a 300 V  
1 2  
ESD  
increment in V  
!
CL  
Similarly for negative ESD pulses, parasitic series inductance from the V pin to the ground rail will lead to drastically  
N
increased negative voltage on the line being protected.  
Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies exhibit  
a much higher output impedance to fast transient current spikes. In the V equation above, the V  
term, in reality, is  
CL  
SUPPLY  
given by (V + I  
x R  
), where V and R  
are the nominal supply DC output voltage and effective output impedance  
DC ESD  
OUT  
DC  
OUT  
of the power supply respectively. As an example, a R  
10 A.  
of 1ĂW would result in a 10 V increment in V for a peak I  
of  
OUT  
CL  
ESD  
If the inductances and resistance described above are close to zero, the rail−clamp ESD protection diodes will do a good job  
of protection. However, since this is not possible in practical situations, a bypass capacitor must be used to absorb the very high  
frequency ESD energy. So for any brand of rail−clamp ESD protection diodes, a bypass capacitor should be connected between  
the V pin of the diodes and the ground plane (V pin of the diodes) as shown in the Application Circuit diagram below. A value  
P
N
of 0.22 mF is adequate for IEC−61000−4−2 level 4 contact discharge protection ( 8 kV). Ceramic chip capacitors mounted with  
short printed circuit board traces are good choices for this application. Electrolytic capacitors should be avoided as they have  
poor high frequency characteristics. For extra protection, connect a zener diode in parallel with the bypass capacitor to mitigate  
www.onsemi.com  
4
PACDN004, SZPACDN004  
the effects of the parasitic series inductance inherent in the capacitor. The breakdown voltage of the zener diode should be  
slightly higher than the maximum supply voltage.  
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected  
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V pin of the Protection  
P
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the  
ESD device to minimize stray series inductance.  
Additional Information  
See also ON Semiconductor Application Notes AP209, “Design Considerations for ESD Protection” and AP219, “ESD  
Protection for USB 2.0 Systems”.  
L
2
POSITIVE SUPPLY RAIL  
V
P
PATH OF ESD CURRENT PULSE I  
ESD  
D
D
LINE BEING  
1
SYSTEM OR  
CIRCUITRY  
BEING  
L
1
PROTECTED  
0.22 mF  
ONE  
CHANNEL  
OF  
CHANNEL  
INPUT  
PROTECTED  
2
PACDN004  
V
CL  
20 A  
0 A  
GROUND RAIL  
V
N
CHASSIS GROUND  
Figure 2. Application of Positive ESD Pulse between Input Channel and Ground  
www.onsemi.com  
5
PACDN004, SZPACDN004  
PACKAGE DIMENSIONS  
SOT−143  
CASE 318A−06  
ISSUE U  
D
e
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.  
2. CONTROLLING DIMENSION: MILLIMETERS.  
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIM­  
UM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE  
MATERIAL.  
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO­  
TRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS,  
AND GATE BURRS SHALL NOT EXCEED 0.25 PER SIDE.  
DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR  
PROTRUSION. INTERLEAD FLASH AND PROTRUSION SHALL  
NOT EXCEED 0.25 PER SIDE.  
D
E
A
GAUGE  
PLANE  
SEATING  
PLANE  
L
L2  
5. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H.  
6. DATUMS A AND B ARE DETERMINED AT DATUM H.  
DETAIL A  
E1  
MILLIMETERS  
b1  
e1  
DIM MIN  
MAX  
1.12  
0.15  
0.51  
0.94  
0.20  
3.05  
2.64  
1.40  
3X  
b
B
A
A1  
b
0.80  
0.01  
0.30  
0.76  
0.08  
2.80  
2.10  
1.20  
M
0.20  
C A-B D  
TOP VIEW  
b1  
c
D
H
c
E
c
0.10  
C
E1  
e
1.92 BSC  
0.20 BSC  
0.35 0.70  
0.25 BSC  
A
DETAIL A  
e1  
L
A1  
SEATING  
PLANE  
C
SIDE VIEW  
END VIEW  
L2  
RECOMMENDED  
SOLDERING FOOTPRINT  
1.92  
4X  
0.75  
2.70  
0.20  
0.96  
3X  
0.54  
DIMENSIONS: MILLIMETERS  
www.onsemi.com  
6
PACDN004, SZPACDN004  
PACKAGE DIMENSIONS  
SOT−143, 4 Lead  
CASE 527AF  
ISSUE A  
D
e
SYMBOL  
MIN  
NOM  
MAX  
A
A1  
A2  
b
1.22  
0.15  
1.07  
0.50  
0.89  
0.20  
3.04  
2.64  
1.40  
0.80  
0.05  
0.75  
0.30  
0.76  
0.08  
2.80  
2.10  
1.20  
4
1
3
2
0.90  
b2  
E1  
E
c
D
2.90  
E
E1  
e
1.30  
1.92 BSC  
0.20 BSC  
0.50  
e1  
TOP VIEW  
b
e1  
L
0.40  
0.60  
L1  
L2  
θ
0.54 REF  
0.25  
0°  
8°  
L2  
q
c
A2  
A1  
A
L
b2  
L1  
SIDE VIEW  
END VIEW  
Notes:  
(1) All dimensions are in millimeters. Angles in degrees.  
(2) Complies with JEDEC TO-253.  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice  
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All  
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights  
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should  
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,  
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal  
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
N. American Technical Support: 800−282−9855 Toll Free  
USA/Canada  
Europe, Middle East and Africa Technical Support:  
Phone: 421 33 790 2910  
Japan Customer Focus Center  
Phone: 81−3−5817−1050  
ON Semiconductor Website: www.onsemi.com  
Order Literature: http://www.onsemi.com/orderlit  
Literature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada  
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada  
Email: orderlit@onsemi.com  
For additional information, please contact your local  
Sales Representative  
PACDN004/D  
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