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8SLVS1118NLGI

型号：

8SLVS1118NLGI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

24 页

PDF大小：

555 K

下载PDF手册
1:18, Low Skew, Low Additive Jitter  
LVDS/ LVPECL Fanout Buffer  
8SLVS1118  
Datasheet  
Description  
Features  
The 8SLVS1118 is a high-performance, low-power, differential  
1:18 output fanout buffer. This highly versatile device is designed  
for the fanout of high-frequency, very low additive phase-noise  
clock and data signals. Guaranteed output-to-output and  
part-to-part skew characteristics make the 8SLVS1118 ideal for  
clock distribution applications that demand well-defined  
performance and repeatability.  
▪ 1:18, low skew, low additive jitter LVPECL/LVDS fanout buffer  
▪ Low power consumption  
▪ Differential PCLK, nPCLK clock pair accepts the following  
differential/single-ended input levels: LVDS, LVPECL, and  
LVCMOS  
▪ Maximum input clock frequency: 2GHz  
▪ Propagation delay: 290ps (typical)  
▪ Output skew: 40ps (typical)  
The device is characterized to operate from a 2.5V or 3.3V power  
supply. The integrated bias voltage references enable easy  
interfacing AC-coupled signals to the device inputs.  
▪ Low additive phase jitter, RMS: 39fs (typical),  
Integration Range: 12kHz – 20MHz,  
(fREF 156.25MHz, VPP 1V, VDD 3.3V)  
▪ Full 2.5V and 3.3V supply voltage modes  
▪ Device current consumption: 180mA (typical) IEE for LVPECL  
output mode, 400mA (typical) IDD for LVDS output mode  
▪ 48-VFQFN, lead-free (RoHS 6) packaging  
▪ Transistor count: 1762  
▪ -40°C to +85°C ambient operating temperature  
▪ Supports case temperature up to 105°C  
Block Diagram  
Q0  
8SLV1118I  
nQ0  
Q1  
nQ1  
Q2  
nQ2  
51k  
Pull-down  
.
.
.
PCLK  
nPCLK  
Pull-up /  
Pull-down  
51k  
51k  
Q17  
nQ17  
Voltage  
Reference  
VREF  
Pull-down  
SEL_LVDS  
51k  
©2017 Integrated Device Technology, Inc.  
1
July 17, 2017  
8SLVS1118 Datasheet  
Pin Assignment  
Figure 1. Pin Assignment for 7mm 7mm VFQFN Package – Top View  
48 47 46 45 44 43 42 41 40 39 38 37  
1
nQ10  
35 Q10  
nQ9  
33 Q9  
36  
GND  
2
Q16  
3
34  
nQ16  
4
Q17  
5
32  
nQ8  
Q8  
nQ17  
6
31  
VDD  
8SLVS1118  
7
30 nQ7  
29 Q7  
VDD_IN  
8
9
VREF  
nPCLK  
28  
27 Q6  
nQ6  
10  
PCLK  
26  
25  
nQ5  
Q5  
11  
12  
SEL_LVDS  
GND  
13 14 15 16 17 18 19 20 21 22 23 24  
Pin Descriptions  
Table 1. Pin Descriptions[a]  
Number  
Name  
Type  
Description  
1
2
GND  
Q16  
Power  
Output  
Output  
Output  
Output  
Power  
Power  
Output  
Ground supply pin.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Output power supply pin.  
3
nQ16  
Q17  
4
5
nQ17  
VDD  
6
7
VDD_IN  
VREF  
nPCLK  
PCLK  
SEL_LVDS  
GND  
Power supply pin.  
8
Bias voltage reference for the PCLK, nPCLK input pair.  
9
Input [PD/PU] Inverting differential clock/data input.  
10  
11  
12  
13  
14  
15  
16  
Input [PD]  
Input [PD]  
Power  
Non-inverting differential clock/data input.  
Control input. Output amplitude select for differential outputs.  
Power supply ground.  
VDD  
Power  
Output power supply pin.  
Q0  
Output  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
nQ0  
Output  
Q1  
Output  
©2017 Integrated Device Technology, Inc.  
2
July 17, 2017  
8SLVS1118 Datasheet  
Table 1. Pin Descriptions[a] (Cont.)  
Number  
Name  
Type  
Description  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
ePad  
nQ1  
Q2  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Power  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Power  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Power  
Power  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Output power supply pin.  
nQ2  
Q3  
nQ3  
Q4  
nQ4  
VDD  
Q5  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Output power supply pin.  
nQ5  
Q6  
nQ6  
Q7  
nQ7  
Q8  
nQ8  
Q9  
nQ9  
Q10  
nQ10  
VDD  
Q11  
nQ11  
Q12  
nQ12  
Q13  
nQ13  
Q14  
nQ14  
Q15  
nQ15  
VDD  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Differential output pair. LVPECL/ LVDS interface levels.  
Output power supply pin.  
GND_EPAD  
Exposed pad of package. Connect to ground.  
[a] Pull-up (PU) and pull-down (PD) resistors are indicated in parentheses. Pull-up and pull-down refers to internal input resistors.  
For typical values, see DC Input Characteristics.  
©2017 Integrated Device Technology, Inc.  
3
July 17, 2017  
8SLVS1118 Datasheet  
Function Table  
Table 2. SEL_LVDS Output Amplitude Selection Table  
SEL_LVDS  
Qx Output Amplitude (mV)  
0 (default)  
1
750 (LVPECL)  
450 (LVDS)  
Absolute Maximum Ratings  
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the  
device. Functional operation of the 8SLVS1118 at absolute maximum ratings is not implied. Exposure to absolute maximum rating  
conditions may affect device reliability.  
Table 3. Absolute Maximum Ratings  
Item  
Rating  
Supply Voltage, VDD_IN  
Inputs, VI  
3.6V  
-0.5V to 3.6V  
Outputs, IO (LVDS)  
Continuous Current  
Surge current  
10mA  
15mA  
Outputs, IO (LVPECL)  
Continuous Current  
Surge current  
50mA  
100mA  
Input Sink/source, IREF  
±2mA  
Maximum Junction Temperature, TJ,MAX  
Storage Temperature, TSTG  
ESD – Human Body Model[a]  
125°C  
-65°C to 150°C  
2000V  
ESD – Charged Device Model[a]  
1500V  
[a] According to JEDEC JS-001-2012/JESD22-C101E.  
©2017 Integrated Device Technology, Inc.  
4
July 17, 2017  
 
 
8SLVS1118 Datasheet  
DC Electrical Characteristics  
Table 4. DC Input Characteristics  
Symbol  
CIN  
RPULLDOWN Input Pull-down Resistor  
RPULLUP Input Pull-up Resistor  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Input Capacitance  
2
pF  
k  
k  
51  
51  
Table 5. Power Supply DC Characteristics, VDD_IN VDD 3.3V ±5%, TA -40°C to 85°C  
Symbol  
VDD_IN  
VDD  
Parameter  
Power Supply Voltage  
Output Supply Voltage  
Power Supply Current  
Test Conditions  
Minimum  
3.135  
Typical  
3.3  
Maximum  
3.465  
3.465  
15  
Units  
V
3.135  
3.3  
V
IDD_IN  
mA  
IEE  
IDD  
Power Supply Current  
Output Supply Current  
SEL_LVDS = 0  
SEL_LVDS = 1  
220  
480  
mA  
mA  
Table 6. Power Supply DC Characteristics, VDD_IN VDD 2.5V ±5%, TA -40°C to 85°C  
Symbol  
VDD_IN  
VDD  
Parameter  
Power Supply Voltage  
Output Supply Voltage  
Power Supply Current  
Test Conditions  
Minimum  
2.375  
Typical  
2.5  
Maximum  
2.625  
2.625  
13  
Units  
V
2.375  
2.5  
V
IDD_IN  
mA  
IEE  
IDD  
Power Supply Current  
Output Supply Current  
SEL_LVDS = 0  
SEL_LVDS = 1  
215  
475  
mA  
mA  
Table 7. LVCMOS Inputs DC Characteristics, VDD_IN VDD 2.5V ±5%, 3.3V ±5%, TA -40°C to 85°C  
Symbol  
Parameter  
Input High Voltage  
Test Conditions  
DD_IN 3.3V ±5%  
Minimum  
Typical  
Maximum  
Units  
V
DD_IN 0.3  
DD_IN 0.3  
0.8  
V
V
V
V
2
V
V
VIH  
V
DD_IN 2.5V ±5%  
DD_IN 3.3V ±5%  
DD_IN 2.5V ±5%  
1.7  
-0.3  
-0.3  
V
VIL  
Input Low Voltage  
0.7  
V
Input High Current  
Input Low Current  
IIH  
IIL  
SEL_LVDS  
SEL_LVDS  
V
DD_IN VIN VDD_MAX  
150  
µA  
µA  
V
DD_IN VDD_MAX,  
V
IN 0V  
-10  
©2017 Integrated Device Technology, Inc.  
5
July 17, 2017  
8SLVS1118 Datasheet  
Table 8. LVDS DC Characteristics – VDD 3.3V ±5%, TA -40°C to 85°C  
Symbol  
VOD  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum Units  
Differential Output Voltage  
VOD Magnitude Change  
Offset Voltage  
370  
490  
50  
mV  
mV  
V
VOD  
VOS  
1.9  
2.7  
50  
VOS  
VOS Magnitude Change  
mV  
Table 9. LVDS DC Characteristics – VDD 2.5V ± 5%, TA -40°C to 85°C  
Symbol  
VOD  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum Units  
Differential Output Voltage  
VOD Magnitude Change  
Offset Voltage  
360  
480  
50  
mV  
mV  
V
VOD  
VOS  
1.1  
1.9  
50  
VOS  
VOS Magnitude Change  
mV  
Table 10. LVPECL DC Characteristics, VDD_IN VDD 2.5V ±5%, 3.3V ±5%, TA -40°C to 85°C[a]  
Symbol  
IIH  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum Units  
Input High Current  
Input Low Current  
Reference Voltage  
PCLK, nPCLK  
V
IN VDD_IN VDD_MAX  
150  
µA  
µA  
µA  
V
PCLK  
V
V
IN 0V, VDD_IN VDD_MAX  
IN 0V, VDD_IN VDD_MAX  
-10  
-150  
IIL  
nPCLK  
VREF  
IREF = 100µA, VDD_IN 3.3V  
IREF = 100µA, VDD_IN 2.5V  
2.05  
2.45  
1.85  
1.55  
VOH  
VOL  
Output High Voltage[b]  
Output Low Voltage[b]  
VDD – 1.1  
VDD – 1.8  
VDD – 0.7  
VDD – 1.4  
V
V
[a] Core supply voltage cannot be lower than the output supply voltage.  
[b] Outputs terminated with 50to VDD – 2V.  
©2017 Integrated Device Technology, Inc.  
6
July 17, 2017  
 
 
8SLVS1118 Datasheet  
AC Electrical Characteristics  
Table 11. AC Electrical Characteristics, VDD_IN VDD 2.5V ±5%, 3.3V ±5%, TA -40°C to 85°C[a]  
Test Conditions  
Symbol  
fREF  
Parameter  
Minimum  
Typical  
Maximum  
Units  
Input Frequency  
Input Edge Rate  
2
GHz  
V/ns  
ps  
V/t  
1.5  
tPD  
Propagation  
Delay[b], [c]  
PCLK to  
any Qx  
290  
400  
tsk(o)  
tsk(p)  
tsk(pp)  
Output Skew[d], [e]  
Pulse Skew[f]  
Part-to-part Skew[e], [g]  
40  
4
60  
20  
ps  
ps  
ps  
fs  
f
f
REF 100MHz  
200  
60  
REF 156.25MHz; square wave,  
PP 1V;  
Integration range: 1kHz – 40MHz  
57  
Buffer Additive Phase  
Jitter, RMS;  
VDDIN = VDD = 3.3V  
750mV amplitude;  
see Additive Phase Jitter  
V
tJIT  
f
V
REF 156.25MHz square wave,  
PP 1V;  
39  
43  
fs  
Integration range: 12kHz – 20MHz  
N(30M) Clock Single-side  
30MHz offset from carrier and  
≤-160  
dBc/Hz  
Band Phase Noise  
noise floor  
10–90%  
20–80%  
160  
105  
300  
200  
1.2  
ps  
ps  
V
tR / tF  
VPP  
Output Rise/ Fall Time  
Input Voltage  
PCLK,  
0.15  
0.3  
Amplitude[h], [i] nPCLK  
VPP_DIFF  
Differential  
Input Voltage  
Amplitude  
PCLK,  
nPCLK  
2.4  
V
V
V
–
VCMR  
Common Mode  
1.125  
DD  
Input Voltage[h], [i], [j]  
(V  
)
PP/2  
VO(pp)  
Output Voltage Swing,  
Peak-to-peak  
SEL_LVDS = 0  
SEL_LVDS = 1  
SEL_LVDS = 0  
SEL_LVDS = 1  
0.55  
0.30  
1.10  
0.60  
0.73  
0.43  
1.46  
0.86  
0.95  
0.60  
1.90  
1.20  
V
V
V
V
VDIFF_OUT Differential  
Output Voltage Swing,  
Peak-to-peak  
LVPECL SEL_LVDS 0,  
Outputs outputs loaded with 50to VDD − 2V  
550  
300  
730  
430  
950  
600  
mV  
mV  
Differential  
Output  
Voltage  
VOD  
LVDS SEL_LVDS 1,  
Outputs outputs loaded with 100  
©2017 Integrated Device Technology, Inc.  
7
July 17, 2017  
8SLVS1118 Datasheet  
Table 11. AC Electrical Characteristics, VDD_IN VDD 2.5V ±5%, 3.3V ±5%, TA -40°C to 85°C[a]  
Test Conditions  
Symbol  
VOS  
Parameter  
LVDS  
Minimum  
Typical  
Maximum  
Units  
SEL_LVDS 1, VDDIN = VDD = 3.3V  
SEL_LVDS 1, VDDIN = VDD = 2.5V  
2.05  
1.25  
2.25  
1.45  
2.45  
1.65  
V
V
Offset Voltage  
Outputs  
[a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted  
in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been  
reached under these conditions.  
[b] Measured from the differential input crossing point to the differential output crossing point.  
[c] Input VPP 400mV.  
[d] Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.  
[e] This parameter is defined in accordance with JEDEC Standard 65.  
[f] Output pulse skew is the absolute value of the difference of the propagation delay times: tPLH – tPHL .  
[g] Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal  
load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.  
[h] VIL should not be less than -0.3V. VIH should not be higher than VDD_IN  
.
[i] For single-ended LVCMOS input applications, refer to application section, Wiring the Differential Input to Accept Single-Ended Levels.  
[j] Common Mode Input Voltage is defined as the cross-point voltage.  
©2017 Integrated Device Technology, Inc.  
8
July 17, 2017  
8SLVS1118 Datasheet  
Additive Phase Jitter  
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase  
Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise  
is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value  
of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental.  
When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the  
fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over  
the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.  
Figure 2. Additive Phase Jitter. Frequency: 156.25MHz, Integration Range: 12kHz to 20MHz 39fs Typical  
Offset from Carrier Frequency (Hz)  
As with most timing specifications, phase noise measurements have issues relating to the limitations of the measurement equipment. The  
noise floor of the equipment can be higher or lower than the noise floor of the device. Additive phase noise is dependent on both the  
noise floor of the input source and measurement equipment.  
Measured using a Wenzel 156.25MHz Oscillator as the input source.  
©2017 Integrated Device Technology, Inc.  
9
July 17, 2017  
8SLVS1118 Datasheet  
Applications Information  
Recommendations for Unused Input and Output Pins  
Inputs  
PCLK/nPCLK Inputs  
For applications not requiring the use of the differential input, both PCLK and nPCLK can be left floating. Though not required, but for  
additional protection, a 1kresistor can be tied from PCLK to ground.  
Outputs  
LVDS Outputs  
All unused LVDS output pairs can be either left floating or terminated with 100across. If they are left floating there should be no trace  
attached.  
LVPECL Outputs  
All unused LVPECL output pairs can be left floating. We recommend that there is no trace attached. Both sides of the differential output  
pair should either be left floating or terminated.  
VREF  
The unused VREF pin can be left floating. We recommend that there is no trace attached.  
Wiring the Differential Input to Accept Single-Ended Levels  
Figure 3 shows how a differential input can be wired to accept single ended levels. The reference voltage V1 VDD/2 is generated by the  
bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as  
close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1in the center of the input voltage  
swing. For example, if the input clock swing is 1.8V and VDD 1.8V, R1 and R2 value should be adjusted to set V1 at 0.9V. The values  
below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output  
impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at  
the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission  
line impedance. For most 50applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading  
for slower and weaker LVCMOS driver.  
Figure 3. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels  
©2017 Integrated Device Technology, Inc.  
10  
July 17, 2017  
 
8SLVS1118 Datasheet  
When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input  
can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced while maintaining an edge rate faster than  
1V/ns. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended  
applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD 0.3V. Though some of  
the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes.  
The datasheet specifications are characterized and guaranteed by using a differential signal.  
2.5V LVPECL Input w ith Built-in 50Termination Interface  
The PCLK /nPCLK with built-in 50terminations accept LVDS, LVPECL, LVCMOS and other differential signals. Both VSWING and VOH  
must meet the VPP and VCMR input requirements. Figure 4 to Figure 5 show interface examples for PCLK /nPCLK with built-in 50  
termination input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from  
another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver  
termination requirements.  
Figure 4. PCLK/ nPCLK Input with Built-in 50Driven by an LVDS Driver  
2.5V  
3.3V or 2.5V  
Zo = 50Ω  
Zo = 50Ω  
PCLK  
VT  
nPCLK  
Receiver  
With  
LVDS  
Built-In  
50Ω  
Figure 5. PCLK/ nPCLK Input with Built-in 50Driven by an LVPECL Driver  
2.5V  
2.5V  
Zo = 50Ω  
Zo = 50Ω  
PCLK  
VT  
nPCLK  
Receiver  
With  
LVPECL  
R1  
Built-In  
50Ω  
18Ω  
©2017 Integrated Device Technology, Inc.  
11  
July 17, 2017  
 
 
8SLVS1118 Datasheet  
3.3V LVPECL Input w ith Built-in 50Termination Interface  
The PCLK /nPCLK with built-in 50terminations accept LVDS, LVPECL, LVCMOS and other differential signals. Both VSWING and VOH  
must meet the VPP and VCMR input requirements. Figure 6 to Figure 7 show interface examples for PCLK /nPCLK with built-in 50  
termination input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from  
another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver  
termination requirements.  
Figure 6. PCLK/ nPCLK Input with Built-in 50Driven by an LVDS Driver  
2.5V  
3.3V or 2.5V  
Zo = 50Ω  
Zo = 50Ω  
PCLK  
VT  
nPCLK  
Receiver  
With  
LVDS  
Built-In  
50Ω  
Figure 7. PCLK/ nPCLK Input with Built-in 50Driven by an LVPECL Driver  
3.3V  
2.5V  
Zo = 50Ω  
Zo = 50Ω  
PCLK  
VT  
nPCLK  
Receiver  
With  
LVPECL  
R1  
18  
Built-In  
50Ω  
Ω
©2017 Integrated Device Technology, Inc.  
12  
July 17, 2017  
 
 
8SLVS1118 Datasheet  
LVDS Driver Termination  
For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90and 132. The actual value  
should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100  
parallel resistor at the receiver and a 100differential transmission-line environment. In order to avoid any transmission-line reflection  
issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS  
compliant devices with two types of output structures: current source and voltage source.  
The standard termination schematic as shown in Figure 8 can be used with either type of output structure. Figure 9, which can also be  
used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value  
should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is  
current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and  
common-mode input range should be verified for compatibility with the output.  
Figure 8. Standard LVDS Termination  
Figure 9. Optional LVDS Termination  
©2017 Integrated Device Technology, Inc.  
13  
July 17, 2017  
 
 
8SLVS1118 Datasheet  
Termination for 3.3V LVPECL Outputs  
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are  
recommended only as guidelines.  
The differential outputs generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or  
current sources must be used for functionality. These outputs are designed to drive 50transmission lines. Matched impedance  
techniques should be used to maximize operating frequency and minimize signal distortion. Figure 10 and Figure 11 show two different  
layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board  
designers simulate to guarantee compatibility across all printed circuit and clock component process variations.  
Figure 10. 3.3V LVPECL Output Termination  
Figure 11. 3.3V LVPECL Output Termination  
3.3V  
R3  
R4  
125  
125  
3.3V  
3.3V  
Zo = 50  
Zo = 50  
+
_
Input  
R1  
84  
R2  
84  
©2017 Integrated Device Technology, Inc.  
14  
July 17, 2017  
 
 
8SLVS1118 Datasheet  
Termination for 2.5V LVPECL Outputs  
Figure 12 and Figure 13 show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50to  
DD – 2V. For VDD 2.5V, the VDD – 2V is very close to ground level. The R3 in Figure 13 can be eliminated and the termination is shown  
V
in Figure 14.  
Figure 12. 2.5V LVPECL Driver Termination Example  
2.5V  
2.5V  
VDD = 2.5V  
R1  
R3  
250  
250  
50Ω  
50Ω  
+
–
2.5V LVPECL Driver  
R2  
62.5  
R4  
62.5  
Figure 13. 2.5V LVPECL Driver Termination Example  
2.5V  
VDD = 2.5V  
50Ω  
+
50Ω  
–
2.5V LVPECL Driver  
R1  
50  
R2  
50  
R3  
18  
Figure 14. 2.5V LVPECL Driver Termination Example  
2.5V  
VDD = 2.5V  
50Ω  
+
50Ω  
–
2.5V LVPECL Driver  
R1  
50  
R2  
50  
©2017 Integrated Device Technology, Inc.  
15  
July 17, 2017  
 
 
 
8SLVS1118 Datasheet  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 15. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed  
on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts.  
While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific  
and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis  
and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved  
when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is  
also recommended that the via diameter should be 12mils to 13mils (0.30mm to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed  
pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land  
pattern.  
Note: These recommendations are to be used as a guideline only. For further information, please refer to the application note on the  
Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Lead-frame Base Package, Amkor Technology.  
Figure 15. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (Draw ing not to scale)  
SOLDER  
SOLDER  
PIN  
EXPOSED HEAT SLUG  
PIN  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
©2017 Integrated Device Technology, Inc.  
16  
July 17, 2017  
 
8SLVS1118 Datasheet  
Case Temperature Considerations  
This device supports applications in a natural convection environment which does not have any thermal conductivity through ambient air.  
The printed circuit board (PCB) is typically in a sealed enclosure without any natural or forced air flow and is kept at or below a specific  
temperature. The device package design incorporates an exposed pad (ePad) with enhanced thermal parameters which is soldered to  
the PCB where most of the heat escapes from the bottom exposed pad. For this type of application, it is recommended to use the  
junction-to-board thermal characterization parameter JB (Psi-JB) to calculate the junction temperature (TJ) and ensure it does not  
exceed the maximum allowed junction temperature in the Absolute Maximum Ratings table.  
The junction-to-board thermal characterization parameter, JB, is calculated using the following equation:  
TJ TCB JB PD, where  
TJ Junction temperature at steady state condition in (oC).  
TCB Case temperature (Bottom) at steady state condition in (oC).  
JB Thermal characterization parameter to report the difference between junction temperature and the temperature of the board  
measured at the top surface of the board.  
PD power dissipation (W) in desired operating configuration.  
TJ  
TCB  
The ePad provides a low thermal resistance path for heat transfer to the PCB and represents the key pathway to transfer heat away from  
the IC to the PCB. It’s critical that the connection of the exposed pad to the PCB is properly constructed to maintain the desired IC case  
temperature (TCB). A good connection ensures that temperature at the exposed pad (TCB) and the board temperature (TB) are relatively  
the same. An improper connection can lead to increased junction temperature, increased power consumption and decreased electrical  
performance. In addition, there could be long-term reliability issues and increased failure rate.  
Example Calculation for Junction Temperature (TJ): TJ TCB JB PD  
Package type  
Body size (mm)  
ePad size (mm)  
Thermal Via  
48-VFQFN  
7 7 0.8  
5.65 5.65  
5 5 Matrix  
1.2oC/W  
JB  
TCB  
PD  
105oC  
1.715W  
For the above variables, the junction temperature is equal to 107.1oC. Since this is below the maximum junction temperature of 125oC,  
there are no long-term reliability concerns.  
©2017 Integrated Device Technology, Inc.  
17  
July 17, 2017  
8SLVS1118 Datasheet  
Pow er Considerations (LVDS Output Mode)  
This section provides information on power dissipation and junction temperature for the 8SLVS1118.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The following is the power dissipation for VDD_IN = VDD = 3.465V, which gives worst case results.  
Maximum current at 85°C: IDD_IN_MAX + IDD_MAX = 495mA.  
Power_MAX = 3.465V x 495mA = 1715mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that  
the bond wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow  
and a multi-layer board, the appropriate value is 22.4°C/W per Table 12.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 1.715W * 22.4°C/W = 123.4°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the  
type of board (multi-layer).  
Table 12. Thermal Resistance JA for 48-VFQFN, Forced Convection  
JA (°C/W) vs. Air Flow (m/s)  
Meters per Second  
0
1
2
48-Lead VFQFN Multi-Layer PCB, JEDEC Standard Test Boards  
22.4  
18.9  
17.4  
©2017 Integrated Device Technology, Inc.  
18  
July 17, 2017  
 
8SLVS1118 Datasheet  
Pow er Considerations (LVPECL Output Mode)  
This section provides information on power dissipation and junction temperature for the 8SLVS1118.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the 8SLVS1118 is the sum of the core power plus the power dissipated at the output(s).  
The following is the power dissipation for VDD_IN = 3.465V, which gives worst case results.  
Note: Please refer to Section 3 for details on calculating power dissipated at the outputs.  
Power (core)MAX = VDD_IN * IEE_MAX = 3.465V * 220mA = 762.3mW  
Power (outputs)MAX = 35mW/Loaded Output pair  
If all outputs are loaded, the total power is 18 * 35mW = 630mW  
Total Power_MAX (3.465V, with all outputs switching) = 762.3mW + 630mW = 1392.3mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that  
the bond wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow  
and a multi-layer board, the appropriate value is 22.4°C/W per Table 13.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 1.3923W * 22.4°C/W = 116.2°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the  
type of board (multi-layer).  
Table 13. Thermal Resistance JA for 48-VFQFN, Forced Convection  
JA by Velocity  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
22.4°C/W  
18.9°C/W  
17.4°C/W  
©2017 Integrated Device Technology, Inc.  
19  
July 17, 2017  
 
8SLVS1118 Datasheet  
3. Calculations and Equations.  
The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination  
are shown in Table 10.  
Figure 16. LVPECL Driver Circuit and Termination  
VDD  
Q1  
VOUT  
RL  
VDD - 2V  
To calculate worst case power dissipation at the output(s), use the following equations which assume a 50load, and a termination  
voltage of VDD – 2V.  
▪ For logic high, VOUT = VOH_MAX = VDD_MAX – 0.7V  
(VDD_MAX – VOH_MAX) = 0.7V  
▪ For logic low, VOUT = VOL_MAX = VDD_MAX – 1.4V  
(VDD_MAX – VOL_MAX) = 1.4V  
Pd_H is the power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
Pd_H = [(VOH_MAX – (VDD_MAX – 2V))/RL] * (VDD_MAX – VOH_MAX) = [(2V – (VDD_MAX – VOH_MAX))/RL] * (VDD_MAX – VOH_MAX) =  
[(2V – 0.7V)/50] * 0.7V = 18.2mW  
Pd_L = [(VOL_MAX – (VDD_MAX – 2V))/RL] * (VDD_MAX – VOL_MAX) = [(2V – (VDD_MAX – VOL_MAX))/RL] * (VDD_MAX – VOL_MAX) =  
[(2V – 1.4V)/50] * 1.4V = 16.8mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 35mW  
©2017 Integrated Device Technology, Inc.  
20  
July 17, 2017  
8SLVS1118 Datasheet  
Package Outline Draw ings  
Figure 17. Package Outline Draw ings – Sheet 1  
©2017 Integrated Device Technology, Inc.  
21  
July 17, 2017  
8SLVS1118 Datasheet  
Figure 18. Package Outline Draw ings – Sheet 2  
©2017 Integrated Device Technology, Inc.  
22  
July 17, 2017  
8SLVS1118 Datasheet  
Marking Diagram  
1. Line 1, line 2, and line 3 indicates the part number.  
2. Line 4:  
▪ “#” indicates stepping.  
▪ “YYWW” indicates the date code  
(YY denotes the last two digits of the year, and  
“WW” denotes a work week number that the part was assembled.  
▪ “$” indicates the mark code.  
Ordering Information  
Table 14. Ordering Information  
Part/Order Number  
Marking  
Package  
Shipping Packaging  
Temperature  
8SLVS1118NLGI  
8SLVS1118NLGI8  
IDT8SLVS1118NLGI  
IDT8SLVS1118NLGI  
48-lead VFQFN, Lead-Free  
Tray  
48-lead VFQFN, Lead-Free;  
Quadrant 1 (EIA-481-C)  
Tape & Reel, Pin 1 Orientation:  
EIA-481-C  
-40°C to  
+85°C  
8SLVS1118NLGI/W  
IDT8SLVS1118NLGI  
48-lead VFQFN, Lead-Free;  
Quadrant 2 (EIA-481-D/E)  
Tape & Reel, Pin 1 Orientation:  
EIA-481-D/E  
Table 15. Pin 1 Orientation in Tape and Reel Packaging  
Part Number Suffix  
Pin 1 Orientation  
Illustration  
8SLVS1118NLGI8  
Quadrant 1 (EIA-481-C)  
8SLVS1118NLGI/W  
Quadrant 2 (EIA-481-D/E)  
©2017 Integrated Device Technology, Inc.  
23  
July 17, 2017  
8SLVS1118 Datasheet  
Revision History  
Revision Date  
Description of Change  
July 17, 2017  
Initial release.  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
www.IDT.com/go/support  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,  
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same  
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability  
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not  
convey any license under intellectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-  
sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property  
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved.  
©2017 Integrated Device Technology, Inc.  
24  
July 17, 2017  
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