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8SLVD1204NLGI

型号：

8SLVD1204NLGI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

18 页

PDF大小：

374 K

下载PDF手册
2:4, LVDS Output Fanout Buffer, 2.5V  
IDT8SLVD1204I  
Datasheet  
Description  
Features  
The IDT8SLVD1204I is a high-performance differential LVDS fanout  
buffer. The device is designed for the fanout of high-frequency, very  
low additive phase-noise clock and data signals. The  
IDT8SLVD1204I is characterized to operate from a 2.5V power  
supply. Guaranteed output-to-output and part-to-part skew  
characteristics make the IDT8SLVD1204I ideal for those clock  
distribution applications demanding well-defined performance and  
repeatability.  
• Four low skew, low additive jitter LVDS output pairs  
• Two selectable differential clock input pairs  
• Differential PCLK, nPCLK pairs can accept the following  
differential input levels: LVDS, LVPECL  
• Maximum input clock frequency: 2GHz  
• LVCMOS/LVTTL interface levels for the control input select pin  
• Output skew: 20ps (maximum)  
Two selectable differential inputs and four low skew outputs are  
available. The integrated bias voltage reference enables easy  
interfacing of single-ended signals to the device inputs. The device is  
optimized for low power consumption and low additive phase noise.  
• Propagation delay: 300ps (maximum)  
• Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,  
10kHz - 20MHz: 95fs (maximum)  
• Full 2.5V supply voltage  
• Lead-free (RoHS 6), 16-Lead VFQFPN packaging  
• -40°C to 85°C ambient operating temperature  
Block Diagram  
Pin Assignment  
VDD  
12 11 10  
13  
9
Q2  
nQ2  
Q3  
VREF  
8
7
6
5
Pulldown  
14  
15  
16  
nPCLK0  
PCLK0  
VDD  
PCLK0  
Q0  
Pullup/Pulldown  
nPCLK0  
nQ0  
nQ3  
1
2
3
4
GND GND  
Q1  
0
VDD  
nQ1  
IDT8SLVD1204I  
16 lead VFQFPN  
3.0mm x 3.0mm x 0.9mm package body  
1.7mm x 1.7mm ePad  
Pulldown  
Q2  
PCLK1  
Pullup/Pulldown  
1
nPCLK1  
nQ2  
NL Package  
Top View  
GND GND  
VDD  
Q3  
nQ3  
Pullup/Pulldown  
SEL  
GND  
Reference  
VREF  
Voltage  
Generator  
IDT8SLVD1204I January 21, 2018  
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©2018 Integrated Device Technology, Inc.  
IDT8SLVD1204I DATASHEET  
Pin Description and Pin Characteristic Tables  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
1
GND  
Power  
Input  
Input  
Input  
Power supply ground.  
Pullup/  
Pulldown  
Reference select control pin. See Table 3 for function. LVCMOS/LVTTL  
interface levels.  
2
3
4
SEL  
PCLK1  
nPCLK1  
Pulldown  
Non-inverting differential clock/data input.  
Pullup/  
Pulldown  
Inverting differential clock/data input. VDD/2 default when left floating.  
5
6
VDD  
Power  
Input  
Power supply pin.  
PCLK0  
Pulldown  
Non-inverting differential clock/data input.  
Pullup/  
Pulldown  
7
nPCLK0  
Input  
Inverting differential clock/data input. VDD/2 default when left floating.  
8
VREF  
Output  
Output  
Output  
Output  
Output  
Bias voltage reference for the PCLK, nPCLK inputs.  
Differential output pair 0. LVDS interface levels.  
Differential output pair 1. LVDS interface levels.  
Differential output pair 2. LVDS interface levels.  
Differential output pair 3. LVDS interface levels.  
9, 10  
11, 12  
13, 14  
15, 16  
Q0, nQ0  
Q1, nQ1  
Q2, nQ2  
Q3, nQ3  
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
pF  
Input Capacitance  
Input Pulldown Resistor  
Input Pullup Resistor  
2
RPULLDOWN  
RPULLUP  
51  
51  
k  
k  
Function Table  
Table 3. SEL Input Selection Function Table  
Input  
SEL  
Operation  
0
PCLK0, nPCLK0 is the selected differential clock input.  
PCLK1, nPCLK1 is the selected differential clock input.  
Input buffers are disabled and outputs are static.  
1
Open (default)  
NOTE: SEL is an asynchronous control.  
IDT8SLVD1204I January 21, 2018  
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©2018 Integrated Device Technology, Inc.  
IDT8SLVD1204I DATASHEET  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress  
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC  
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VDD  
Inputs, VI  
4.6V  
-0.5V to VDD + 0.5V  
Outputs, IO  
Continuous Current  
Surge Current  
10mA  
15mA  
VREF current Sink/Source, IREF  
±2mA  
Maximum Junction Temperature, TJ,MAX  
Storage Temperature, TSTG  
125°C  
-65C to 150C  
2000V  
ESD - Human Body Model, NOTE 1  
ESD - Charged Device Model, NOTE 1  
1500V  
NOTE 1: According to JEDEC/JESD JS-001-2012/22-C101E.  
Electrical Characteristics  
Table 4A. Power Supply Characteristics, V = 2.5V ± 5%, T = -40°C to 85°C  
DD  
A
Symbol Parameter  
VDD Power Supply Voltage  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
2.375  
2.5  
2.625  
V
SEL = 0 or 1; fREF = 100MHz;  
Q0 to Q3 terminated 100between nQx, Qx  
84  
84  
84  
100  
100  
100  
mA  
mA  
mA  
SEL = 0 or 1; fREF = 800MHz;  
Q0 to Q3 terminated 100between nQx, Qx  
IDD  
Power Supply Current  
SEL = 0 or 1; fREF = 2GHz;  
Q0 to Q3 terminated 100between nQx, Qx  
Table 4B. LVCMOS/LVTTL DC Characteristics, V = 2.5V ± 5%, T = -40°C to 85°C  
DD  
A
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Open-Pin Voltage  
(Default State)  
VdI3  
SEL  
Open  
VDD / 2  
V
VIH  
VIL  
IIH  
Input High Voltage SEL  
Input Low Voltage SEL  
Input High Current SEL  
Input Low Current SEL  
0.7 * VDD  
-0.3  
VDD + 0.3  
0.2 * VDD  
150  
V
V
VDD = VIN = 2.625V  
µA  
µA  
IIL  
VDD = 2.625V, VIN = 0V  
-150  
IDT8SLVD1204I January 21, 2018  
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©2018 Integrated Device Technology, Inc.  
IDT8SLVD1204I DATASHEET  
Table 4C. Differential Input DC Characteristics, V = 2.5V ± 5%, T = -40°C to 85°C  
DD  
A
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
µA  
Input High  
Current  
PCLK0, nPCLK1  
PCLK1, nPCLK1  
IIH  
V
DD = VIN = 2.625V  
VDD = 2.625V, VIN = 0V  
VDD = 2.625V, VIN = 0V  
IREF = ±1mA  
150  
PCLK0, PCLK1  
-10  
µA  
Input Low  
Current  
IIL  
nPCLK0,  
nPCLK1  
-150  
µA  
VREF  
VPP  
Reference Voltage for Input Bias  
Peak-to-Peak Voltage; NOTE 1  
VDD – 1.50  
0.1  
VDD – 1.35  
VDD – 1.15  
1.5  
V
V
V
f
f
REF < 1.5 GHz  
REF > 1.5 GHz  
0.2  
1.5  
Common Mode Input Voltage;  
NOTE 1, 2  
VCMR  
1.0  
VDD – 0.6  
V
NOTE 1: VIL should not be less than -0.3V.  
NOTE 2: Common mode input voltage is defined at the crosspoint.  
Table 4D. LVDS DC Characteristics, V = 2.5V ± 5%, T = -40°C to 85°  
DD  
A
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
450  
Units  
mV  
mV  
V
VOD  
Differential Output Voltage  
250  
VOD  
VOS  
VOD Magnitude Change  
Offset Voltage  
50  
1.15  
1.45  
50  
VOS  
VOS Magnitude Change  
mV  
IDT8SLVD1204I January 21, 2018  
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©2018 Integrated Device Technology, Inc.  
IDT8SLVD1204I DATASHEET  
AC Electrical Characteristics  
Table 5. AC Electrical Characteristics, V = 2.5V ± 5%, T = -40°C to 85°C  
DD  
A
Symbol  
Parameter  
Test Conditions  
Minimum Typical  
Maximum  
Units  
Input  
PCLK[0:1],  
fREF  
2
GHz  
Frequency nPCLK[0:1]  
Input PCLK[0:1],  
Edge Rate nPCLK[0:1]  
V/t  
1.5  
V/ns  
ps  
Propagation Delay;  
NOTE 1  
PCLK[0:1], nPCLK[0:1] to any Qx, nQx  
for VPP = 0.1V or 0.3V  
tPD  
120  
210  
300  
tsk(o)  
tsk(i)  
Output Skew; NOTE 2, 3  
Input Skew; NOTE 3  
Pulse Skew  
20  
20  
15  
ps  
ps  
ps  
tsk(p)  
fREF = 100MHz  
Part-to-Part Skew;  
NOTE 3, 4  
tsk(pp)  
230  
205  
135  
135  
130  
95  
ps  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fREF = 122.88MHz Square Wave, VPP = 1V,  
Integration Range: 1kHz – 40MHz  
138  
92  
92  
89  
65  
65  
87  
64  
64  
fREF = 122.88MHz Square Wave, VPP = 1V,  
Integration Range: 10kHz – 20MHz  
f
REF = 122.88MHz Square Wave, VPP = 1V,  
Integration Range: 12kHz – 20MHz  
fREF = 156.25MHz Square Wave, VPP = 1V,  
Integration Range: 1kHz – 40MHz  
Buffer Additive Phase  
Jitter, RMS; refer to  
Additive Phase Jitter  
Section  
fREF = 156.25MHz Square Wave, VPP = 1V,  
Integration Range: 10kHz – 20MHz  
tJIT  
f
REF = 156.25MHz Square Wave, VPP = 1V,  
Integration Range: 12kHz – 20MHz  
95  
fREF = 156.25MHz Square Wave, VPP = 0.5V,  
Integration Range: 1kHz – 40MHz  
130  
95  
fREF = 156.25MHz Square Wave, VPP = 0.5V,  
Integration Range: 10kHz – 20MHz  
f
REF = 156.25MHz Square Wave, VPP = 0.5V,  
95  
Integration Range: 12kHz – 20MHz  
20% to 80%  
outputs loaded with 100  
tR / tF  
Output Rise/ Fall Time  
Mux Isolation; NOTE 5  
40  
250  
ps  
MUXISOLATION  
fREF = 100MHz  
72  
dB  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device  
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal  
equilibrium has been reached under these conditions.  
NOTE 1: Measured from the differential input crosspoint to the differential output crosspoint.  
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint.  
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.  
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and  
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoint.  
NOTE 5: Qx, nQx outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information section.  
IDT8SLVD1204I January 21, 2018  
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©2018 Integrated Device Technology, Inc.  
IDT8SLVD1204I DATASHEET  
Additive Phase Jitter  
The spectral purity in a band at a specific offset from the fundamental  
compared to the power of the fundamental is called the dBc Phase  
Noise. This value is normally expressed using a Phase noise plot  
and is most often the specified plot in many applications. Phase noise  
is defined as the ratio of the noise power present in a 1Hz band at a  
specified offset from the fundamental frequency to the power value of  
the fundamental. This ratio is expressed in decibels (dBm) or a ratio  
of the power in the 1Hz band to the power in the fundamental. When  
the required offset is specified, the phase noise is called a dBc value,  
which simply means dBm at a specified offset from the fundamental.  
By investigating jitter in the frequency domain, we get a better  
understanding of its effects on the desired application over the entire  
time record of the signal. It is mathematically possible to calculate an  
expected bit error rate given a phase noise plot.  
Additive Phase Jitter @ 156.25MHz, V = 1V,  
PP  
Integration Range (12kHz to 20MHz) = 65fs (typical)  
Offset from Carrier Frequency (Hz)  
As with most timing specifications, phase noise measurements have  
issues relating to the limitations of the measurement equipment. The  
noise floor of the equipment can be higher or lower than the noise  
floor of the device. Additive phase noise is dependent on both the  
noise floor of the input source and measurement equipment.  
Measured using a Wenzel 156.25MHz Oscillator as the input source.  
IDT8SLVD1204I January 21, 2018  
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©2018 Integrated Device Technology, Inc.  
IDT8SLVD1204I DATASHEET  
Parameter Measurement Information  
V
DD  
V
DD  
nPCLK[0:1]  
PCLK[0:1]  
GND  
LVDS Output Load Test Circuit  
Differential Input Level  
nPCLK[0:1]  
PCLK[0:1]  
nQx  
Qx  
nQy  
nQy  
Qy  
Qy  
tPLH  
tPHL  
tsk(p)= |tPHL - tPLH  
|
Pulse Skew  
Output Skew  
Part 1  
nQx  
nQ[0:3]  
80%  
80%  
Qx  
VOD  
20%  
Part 2  
20%  
nQy  
Q[0:3]  
tF  
tR  
Qy  
tsk(pp)  
Part-to-Part Skew  
Output Rise/Fall Time  
IDT8SLVD1204I January 21, 2018  
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©2018 Integrated Device Technology, Inc.  
IDT8SLVD1204I DATASHEET  
Parameter Measurement Information, continued  
nPCLK0  
Spectrum of Output Signal Q  
PCLK0  
MUX selects active  
input clock signal  
A0  
nPCLK1  
PCLK1  
MUX_ISOLATION = A0 – A1  
nQ[0:3]  
MUX selects other input  
A1  
Q[0:3]  
tPD2  
tPD1  
ƒ
Frequency  
tsk(i)  
(fundamental)  
tsk(i) = |tPD1 - tPD2  
|
Input Skew  
MUX Isolation  
nPCLK[0:1]  
PCLK[0:1]  
nQ[0:3]  
Q[0:3]  
tPD  
Propagation Delay  
Offset Voltage Setup  
Differential Output Voltage Setup  
IDT8SLVD1204I January 21, 2018  
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©2018 Integrated Device Technology, Inc.  
IDT8SLVD1204I DATASHEET  
Applications Information  
Recommendations for Unused Input and Output Pins  
Inputs:  
Outputs:  
PCLK/nPCLK Inputs  
LVDS Outputs  
For applications not requiring the use of a differential input, both the  
PCLK and nPCLK pins can be left floating. Though not required, but  
for additional protection, a 1kresistor can be tied from PCLK to  
ground.  
All unused LVDS output pairs can be either left floating or terminated  
with 100across. If they are left floating, there should be no trace  
attached.  
Wiring the Differential Input to Accept Single-Ended Levels  
Figure 1 shows how a differential input can be wired to accept single  
ended levels. The reference voltage V1 = VDD/2 is generated by the  
bias resistors R1 and R2. The bypass capacitor (C1) is used to help  
filter noise on the DC bias. This bias circuit should be located as  
close to the input pin as possible. The ratio of R1 and R2 might need  
to be adjusted to position the V1 in the center of the input voltage  
swing. For example, if the input clock swing is 2.5V and VDD = 2.5V,  
R1 and R2 value should be adjusted to set V1 at 1.25V. The values  
below are for when both the single ended swing and VDD are at the  
same voltage. This configuration requires that the sum of the output  
impedance of the driver (Ro) and the series resistance (Rs) equals  
the transmission line impedance. In addition, matched termination at  
the input will attenuate the signal in half. This can be done in one of  
two ways. First, R3 and R4 in parallel should equal the transmission  
line impedance. For most 50applications, R3 and R4 can be 100.  
The values of the resistors can be increased to reduce the loading for  
slower and weaker LVCMOS driver. When using single-ended  
signaling, the noise rejection benefits of differential signaling are  
reduced. Even though the differential input can handle full rail  
LVCMOS signaling, it is recommended that the amplitude be  
reduced. The datasheet specifies a lower differential amplitude,  
however this only applies to differential signals. For single-ended  
applications, the swing can be larger, however VIL cannot be less  
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some  
of the recommended components might not be used, the pads should  
be placed in the layout. They can be utilized for debugging purposes.  
The datasheet specifications are characterized and guaranteed by  
using a differential signal.  
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels  
IDT8SLVD1204I January 21, 2018  
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©2018 Integrated Device Technology, Inc.  
IDT8SLVD1204I DATASHEET  
2.5V LVPECL Clock Input Interface  
The PCLK /nPCLK accepts LVPECL, LVDS, and other differential  
signals. Both signals must meet the VPP and VCMR input  
requirements. Figures 2A to 2C show interface examples for the  
PCLK/ nPCLK input driven by the most common driver types. The  
input interfaces suggested here are examples only. If the driver is  
from another vendor, use their termination recommendation. Please  
consult with the vendor of the driver component to confirm the driver  
termination requirements.  
2.5V  
2.5V  
2.5V  
PCLK  
nPCLK  
LVPECL  
Input  
LVPECL  
Figure 2A. PCLK/nPCLK Input Driven by a  
2.5V LVPECL Driver  
Figure 2B. PCLK/nPCLK Input Driven by a  
2.5V LVPECL Driver with AC Couple  
PCLK  
nPCLK  
Figure 2C. PCLK/nPCLK Input Driven by a  
2.5V LVDS Driver  
IDT8SLVD1204I January 21, 2018  
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©2018 Integrated Device Technology, Inc.  
IDT8SLVD1204I DATASHEET  
LVDS Driver Termination  
For a general LVDS interface, the recommended value for the  
termination impedance (ZT) is between 90and 132. The actual  
value should be selected to match the differential impedance (Z0) of  
your transmission line. A typical point-to-point LVDS design uses a  
100parallel resistor at the receiver and a 100differential  
transmission-line environment. In order to avoid any  
transmission-line reflection issues, the components should be  
surface mounted and must be placed as close to the receiver as  
possible. IDT offers a full line of LVDS compliant devices with two  
types of output structures: current source and voltage source. The  
standard termination schematic as shown in Figure 3A can be used  
with either type of output structure. Figure 3B, which can also be  
used with both output types, is an optional termination with center tap  
capacitance to help filter common mode noise. The capacitor value  
should be approximately 50pF. If using a non-standard termination, it  
is recommended to contact IDT and confirm if the output structure is  
current source or voltage source type. In addition, since these  
outputs are LVDS compatible, the input receiver’s amplitude and  
common-mode input range should be verified for compatibility with  
the output.  
ZO ZT  
LVDS  
Receiver  
LVDS  
Driver  
ZT  
Figure 3A. Standard Termination  
ZT  
ZO ZT  
LVDS  
Driver  
2
ZT  
2
LVDS  
Receiver  
C
Figure 3B. Optional Termination  
LVDS Termination  
IDT8SLVD1204I January 21, 2018  
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IDT8SLVD1204I DATASHEET  
VFQFPN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 4. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally/  
Electrically Enhance Leadframe Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
SOLDER  
SOLDER  
PIN  
PIN  
EXPOSED HEAT SLUG  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
IDT8SLVD1204I January 21, 2018  
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©2018 Integrated Device Technology, Inc.  
IDT8SLVD1204I DATASHEET  
Power Considerations  
This section provides information on power dissipation and junction temperature for the IDT8SLVD1204I. Equations and example calculations  
are also provided.  
1. Power Dissipation.  
The total power dissipation for the IDT8SLVD1204I is the sum of the core power plus the output power dissipation due to the load. The following  
is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.  
•
Total Power (core)MAX = VDD_MAX * IDD_MAX = 2.625V * 100mA = 262.5mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 74.7°C/W per Table 6 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.263W * 74.7°C/W = 104.6°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 6. Thermal Resistance for 16-Lead VFQFPN, Forced Convection  
JA  
JA at 0 Air Flow  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
74.7°C/W  
65.3°C/W  
58.5°C/W  
IDT8SLVD1204I January 21, 2018  
13  
©2018 Integrated Device Technology, Inc.  
IDT8SLVD1204I DATASHEET  
Reliability Information  
Table 7. vs. Air Flow Table for a 16-Lead VFQFPN  
JA  
JA at 0 Air Flow  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
74.7°C/W  
65.3°C/W  
58.5°C/W  
Transistor Count  
The transistor count for the IDT8SLVD1204I is: 417  
IDT8SLVD1204I January 21, 2018  
14  
©2018 Integrated Device Technology, Inc.  
IDT8SLVD1204I DATASHEET  
Package Outline Drawings  
The package outline drawings are located at the end of this document. The package information is the most current data available and is  
subject to change without notice or revision of this document.  
Ordering Information  
Table 8. Ordering Information  
Part/Order Number  
Marking  
Package  
Shipping Packaging  
Temperature  
8SLVD1204NLGI  
1204I  
“Lead-Free” 16-Lead VFQFPN  
Tube  
-40C to 85C  
Tape & Reel,  
pin 1 orientation: EIA-481-C  
8SLVD1204NLGI8  
8SLVD1204NLGI/W  
1204I  
1204I  
“Lead-Free” 16-Lead VFQFPN  
“Lead-Free” 16-Lead VFQFPN  
-40C to 85C  
-40C to 85C  
Tape & Reel,  
pin 1 orientation: EIA-481-D  
Table 9. Pin 1 Orientation in Tape and Reel Packaging  
Part Number Suffix  
Pin 1 Orientation  
Illustration  
CARRIER TAPE TOPSIDE  
(Round Sprocket Holes)  
Correct Pin 1 ORIENTATION  
8
Quadrant 1 (EIA-481-C)  
USER DIRECTION OF FEED  
Correct Pin 1 ORIENTATION  
CARRIER TAPE TOPSIDE  
(Round Sprocket Holes)  
/W  
Quadrant 2 (EIA-481-D)  
USER DIRECTION OF FEED  
IDT8SLVD1204I January 21, 2018  
15  
©2018 Integrated Device Technology, Inc.  
Revision History  
Revision Date  
January 21, 2018  
July 8, 2014  
Description of Change  
• Updated the package outline drawings; however, no technical changes.  
• Replaced the package term VFQFN with VFQFPN.  
Corrected part number  
February 26, 2014 Ordering Info: Changed Tray to Tube.  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
www.idt.com/go/support  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without  
notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed  
in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any  
particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intel-  
lectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of  
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc All rights reserved.  
IDT8SLVD1204I January 21, 2018  
16  
©2018 Integrated Device Technology, Inc.  
16-VFQFPN Package Outline Drawing  
3.0 x 3.0 x 0.9 mm, 0.5mm Pitch, 1.70 x 1.70 mm Epad  
NL/NLG16P2, PSC-4169-02, Rev 05, Page 1  
‹ꢀ,QWHJUDWHGꢀ'HYLFHꢀ7HFKQRORJ\ꢁꢀ,QFꢂ  
16-VFQFPN Package Outline Drawing  
3.0 x 3.0 x 0.9 mm, 0.5mm Pitch, 1.70 x 1.70 mm Epad  
NL/NLG16P2, PSC-4169-02, Rev 05, Page 2  
Package Revision History  
Description  
Rev 04 Remove Bookmak at Pdf Format & Update Thickness Tolerance  
Change QFN to VFQFPN  
Date Created Rev No.  
Oct 25, 2017  
Jan 18, 2018  
Rev 05  
‹ꢀ,QWHJUDWHGꢀ'HYLFHꢀ7HFKQRORJ\ꢁꢀ,QFꢂ  
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