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8SLVD1212ANLGI

型号：

8SLVD1212ANLGI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

20 页

PDF大小：

500 K

下载PDF手册
8SLVD1212  
Datasheet  
1:12, LVDS Output Fanout Buffer  
Features  
Description  
▪ Twelve low skew, low additive jitter LVDS output pairs  
The 8SLVD1212 is a high-performance differential LVDS fanout  
buffer. The device is designed for the fanout of high-frequency,  
very low additive phase-noise clock and data signals.  
▪ Two selectable, differential clock input pairs  
▪ Differential PCLK, nPCLK pairs can accept the following  
differential input levels: LVDS, LVPECL, CML  
The 8SLVD1212 is characterized to operate from a 2.5V power  
supply. Guaranteed output-to-output and part-to-part skew  
characteristics make the device ideal for clock distribution  
applications that demand well-defined performance and  
repeatability.  
▪ Maximum input clock frequency: 2GHz (maximum)  
▪ LVCMOS/LVTTL interface levels for the control input select  
pins  
▪ Output skew: 40ps (maximum)  
Two selectable differential inputs and twelve low skew outputs are  
available. The integrated bias voltage reference enables easy  
interfacing of single-ended signals to the device inputs.  
▪ Propagation delay: 310ps (typical)  
▪ Low additive phase jitter, RMS; fREF = 156.25MHz,  
10kHz to 20MHz: 77fs (typical)  
The 8SLVD1212 is optimized for low power consumption and low  
additive phase noise.  
▪ Device current consumption (IDD): 213mA (maximum)  
▪ 2.5V supply voltage  
▪ Lead-free (RoHS 6), 6 6 mm, 40-VFQFN packaging  
▪ -40°C to 85°C ambient operating temperature  
Block Diagram  
8SLVD1212  
Q0  
nQ0  
Voltage  
Reference  
VREF0  
Q1  
nQ1  
VDD  
Q2  
nQ2  
PCLK0  
nPCLK0  
Q3  
nQ3  
Q4  
GND  
VDD  
nQ4  
fREF  
Q5  
nQ5  
PCLK1  
nPCLK1  
Q6  
nQ6  
Q7  
nQ7  
GND  
VDD  
Q8  
nQ8  
SEL  
Q9  
nQ9  
GND  
Q10  
nQ10  
Voltage  
Reference  
VREF1  
Q11  
nQ11  
©2017 Integrated Device Technology, Inc.  
1
December 22, 2017  
 
 
8SLVD1212 Datasheet  
Contents  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin Descriptions and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Additive Phase Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Parameter Measurement Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Recommendations for Unused Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Wiring the Differential Input to Accept Single-Ended Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
2.5V LVPECL Clock Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
LVDS Driver Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
VFQFN EPAD Thermal Release Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Power Considerations (8SLVD1212A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Reliability Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Package Outline Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Marking Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
©2017 Integrated Device Technology, Inc.  
2
December 22, 2017  
8SLVD1212 Datasheet  
Pin Assignments  
Figure 1. Pin Assignments  
38 37 36 35 34 33 32 31  
39  
40  
1
2
SEL  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
GND  
nQ7  
PCLK1  
nPCLK1  
VREF1  
VDD  
3
Q7  
nQ6  
Q6  
4
5
8SLVD1212  
VDD  
nQ5  
Q5  
6
VREF0  
7
nPCLK0  
nQ4  
Q4  
8
PCLK0  
nc  
9
GND  
10  
11 12  
13 14  
16 17 18 19 20  
15  
Pin Descriptions and Characteristics  
Table 1. Pin Descriptions[a]  
Number  
Name  
Type  
Description  
Pullup/  
Pulldown  
Reference select control pin. See Table 3 for function. LVCMOS/LVTTL  
interface levels.  
1
2
3
SEL  
Input  
Input  
Input  
PCLK1  
nPCLK1  
Pulldown  
Non-inverting differential clock/data input.  
Pullup/  
Pulldown  
Inverting differential clock/data input. V /2 default when left floating.  
DD  
4
5
6
7
V
Output  
Power  
Power  
Output  
Bias voltage reference for the PCLK1, nPCLK1 inputs.  
Power supply pins.  
REF1  
V
DD  
DD  
V
Power supply pins.  
V
Bias voltage reference for the PCLK0, nPCLK0 inputs.  
REF0  
Pullup/  
Pulldown  
8
nPCLK0  
Input  
Inverting differential clock/data input. V /2 default when left floating.  
DD  
9
PCLK0  
nc  
Input  
Unused  
Power  
Output  
Output  
Output  
Output  
Pulldown  
Non-inverting differential clock/data input.  
Do not connect.  
10  
11  
12  
13  
14  
15  
V
Power supply pins.  
DD  
Q0  
nQ0  
Q1  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
nQ1  
©2017 Integrated Device Technology, Inc.  
3
December 22, 2017  
8SLVD1212 Datasheet  
Table 1. Pin Descriptions[a] (Cont.)  
Number  
Name  
Type  
Description  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38,  
39  
40  
Q2  
nQ2  
Q3  
Output  
Output  
Output  
Output  
Power  
Power  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Power  
Power  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Power  
Power  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
nQ3  
V
Power supply pins.  
DD  
GND  
Q4  
Power supply ground.  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
nQ4  
Q5  
nQ5  
Q6  
nQ6  
Q7  
nQ7  
GND  
Power supply ground.  
Power supply pins.  
V
DD  
Q8  
nQ8  
Q9  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
nQ9  
Q10  
nQ10  
Q11  
nQ11  
V
Power supply pins.  
DD  
GND_EP  
Exposed pad of package. Connect to GND.  
[a] Pulldown and Pullup refer to internal input resistors. For typical values, see Table 2.  
Table 2. Pin Characteristics  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
C
R
R
Input Capacitance  
2
pF  
k  
k  
IN  
Input Pulldown Resistor  
Input Pullup Resistor  
50  
50  
PULLDOWN  
PULLUP  
©2017 Integrated Device Technology, Inc.  
4
December 22, 2017  
 
8SLVD1212 Datasheet  
Function Table  
Table 3. SEL Input Function Table[a]  
SEL  
Operation  
0
1
PCLK0, nPCLK0 is the selected differential clock input.  
PCLK1, nPCLK1 is the selected differential clock input.  
Input buffers are disabled and outputs are static.  
Open  
[a] SEL is an asynchronous control.  
Absolute Maximum Ratings  
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the  
device. Functional operation of the 8SLVD1212 at absolute maximum ratings is not implied. Exposure to absolute maximum rating  
conditions may affect device reliability.  
Table 4. Absolute Maximum Ratings  
Item  
Rating  
Supply Voltage, V  
4.6V  
DD  
Inputs, V  
-0.5V to V + 0.5V  
I
DD  
Outputs, I  
O
Continuous Current  
Surge Current  
10mA  
15mA  
Input Sink/Source, I  
±2mA  
125°C  
REF  
Maximum Junction Temperature, T  
J,MAX  
Storage Temperature, T  
-65°C to 150°C  
2000V  
STG  
[a]  
ESD - Human Body Model  
ESD - Charged Device Mode  
[a] According to JEDEC/JS-001-2012/ 22-C101E.  
[a]  
500V  
©2017 Integrated Device Technology, Inc.  
5
December 22, 2017  
 
8SLVD1212 Datasheet  
DC Electrical Characteristics  
Table 5. Pow er Supply DC Characteristics, VDD = 2.5V ±5%, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
V
Power Supply Voltage  
2.375  
2.5  
2.625  
213  
V
DD  
Q0 to Q11 terminated 100  
between nQx, Qx  
184  
mA  
I
Power Supply Current  
DD  
Table 6. LVCMOS/LVTTL DC Characteristics, VDD = 2.5V ±5%, TA = -40°C to 85°C  
Symbol  
Parameter  
Input voltage  
Test Conditions  
Minimum  
Typical  
/ 2  
Maximum  
Units  
V
V
V
Floating  
V
V
V
MID  
DD  
Input High Voltage  
Input Low Voltage  
Input High Current  
Input Low Current  
0.7 V  
V
+ 0.3  
DD  
IH  
IL  
DD  
-0.3  
0.2 V  
V
DD  
I
I
SEL  
SEL  
V
V
= V = 2.625V  
150  
µA  
µA  
IH  
IL  
DD  
DD  
IN  
= 2.625V, V = 0V  
-150  
IN  
Table 7. Differential Inputs Characteristics, VDD = 2.5V ±5%, TA = -40°C to 85°C  
Symbol  
Parameter  
PCLK0,  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Input  
High Current  
nPCLK0  
PCLK1,  
nPCLK1  
I
I
V
= V = 2.625V  
150  
µA  
IH  
IL  
IN  
DD  
PCLK0,  
PCLK1  
V
= 0V, V = 2.625V  
-10  
µA  
µA  
V
IN  
DD  
Input  
Low Current  
nPCLK0,  
nPCLK1  
V
= 0V, V = 2.625V  
-150  
IN  
DD  
Reference Voltage for  
Input Bias  
(V /2) -  
(V /2) +  
DD  
DD  
V
V
V
, V  
I
= ±0.5mA  
V /2  
DD  
REF0 REF1  
REFx  
0.15  
0.15  
f
f
< 1.5GHz  
> 1.5GHz  
0.1  
1.5  
V
V
REF  
REF  
[a]  
Peak-to-Peak Voltage  
PP  
0.2  
1.5  
Common Mode Input  
Voltage  
1.0  
V
- (V /2)  
V
[a][b]  
CMR  
DD  
pp  
[a] VIL should not be less than -0.3V. VIH should not be greater than VDD  
[b] Common mode input voltage is defined at the crosspoint.  
.
©2017 Integrated Device Technology, Inc.  
6
December 22, 2017  
 
8SLVD1212 Datasheet  
Table 8. LVDS DC Characteristics, VDD = 2.5V ±5%, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
V
Differential Output Voltage  
Outputs Loaded with 100  
247  
454  
50  
mV  
mV  
V
OD  
V  
V
Magnitude Change  
OD  
OD  
V
Offset Voltage  
Magnitude Change  
1.125  
1.375  
50  
OS  
V  
V
mV  
OS  
OS  
AC Electrical Characteristics  
Table 9. AC Electrical Characteristics, VDD = 2.5V ±5%, TA = -40°C to 85°C[a]  
Symbol  
Parameter  
PCLK[0:1],  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Input  
f
2
GHz  
REF  
Frequency  
nPCLK[0:1]  
Input  
Edge Rate  
PCLK[0:1],  
nPCLK[0:1]  
V/t  
1.5  
V/ns  
PCKx, nPCLKx to any Qx, nQx  
[b]  
t
Propagation Delay  
200  
310  
500  
40  
ps  
ps  
ps  
ps  
PD  
for V = 0.1V or 0.3V  
PP  
[c][d]  
tsk(o)  
tsk(p)  
tsk(pp)  
Output Skew  
f
= 100MHz, 500MHz,  
[e][f]  
REF  
Pulse Skew  
80  
1GHz, 1.5GHz  
[d][g]  
Part-to-Part Skew  
300  
f
= 156.25MHz, V = 1.0V,  
PP  
REF  
Buffer Additive Phase Jitter,  
RMS  
t
Integration Range: 10kHz –  
20MHz  
77  
90  
fs  
JIT  
20% to 80%  
t / t  
Output Rise/ Fall Time  
100  
75  
200  
ps  
R
F
Outputs Loaded with 100  
[h]  
MUX  
Mux Isolation  
f
= 100MHz  
REF  
dB  
ISOLATION  
[a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted  
in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been  
reached under these conditions.  
[b] Measured from the differential input crosspoint to the differential output crosspoint.  
[c] Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint.  
[d] This parameter is defined in accordance with JEDEC Standard 65.  
[e] Output pulse skew tsk(p) is absolute difference of the propagation delay times: |tPLH - tPHL|.  
[f] Output duty cycle is frequency dependent: odc= input duty cycle +/- ((tsk(p)/2)*(1/output period))*100.  
[g] Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal  
load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross point.  
[h] Qx, nQx outputs measured differentially (for more information, see Figure 10).  
©2017 Integrated Device Technology, Inc.  
7
December 22, 2017  
 
8SLVD1212 Datasheet  
Additive Phase Jitter  
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase  
Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise  
is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value  
of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental.  
When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the  
fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over  
the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.  
Figure 2. Additive Phase Jitter  
Additive Phase Jitter 77fs (typical)  
Offset from Carrier Frequency (Hz)  
As with most timing specifications, phase noise measurements have issues relating to the limitations of the measurement equipment. The  
noise floor of the equipment can be higher or lower than the noise floor of the device. Additive phase noise is dependent on both the  
noise floor of the input source and measurement equipment.  
Measured using a Rohde and Schwartz SMA100A as the input source.  
©2017 Integrated Device Technology, Inc.  
8
December 22, 2017  
8SLVD1212 Datasheet  
Parameter Measurement Information  
Figure 3. 2.5V LVDS Output Load Test Circuit  
Figure 4. Differential Input Level  
V
DD  
nPCLK[0:1]  
PCLK[0:1]  
V
DD  
VPP  
Cross Points  
VCMR  
GND  
Figure 5. Pulse Skew  
Figure 6. Output Skew  
nPCLK[0:1]  
PCLK[0:1]  
nQx  
Qx  
nQy  
nQy  
Qy  
Qy  
tPLH  
tPHL  
tsk(p)= |tPHL - tPLH  
|
Figure 7. Part-to-Part Skew  
Figure 8. Output Rise/Fall Time  
Part 1  
nQx  
nQ[0:11]  
80%  
80%  
Qx  
VOD  
20%  
Part 2  
20%  
nQy  
Q[0:11]  
tF  
tR  
Qy  
tsk(pp)  
©2017 Integrated Device Technology, Inc.  
9
December 22, 2017  
8SLVD1212 Datasheet  
Figure 9. Propagation Delay  
Figure 10. MUX Isolation  
Spectrum of Output Signal Q  
MUX selects active  
input clock signal  
nPCLK[0:1]  
PCLK[0:1]  
A0  
MUX_ISOLATION = A0 – A1  
nQ[0:11]  
Q[0:11]  
MUX selects other input  
A1  
tPD  
ƒ
Frequency  
(fundamental)  
Figure 11. Differential Output Voltage Setup  
Figure 12. Offset Voltage Setup  
©2017 Integrated Device Technology, Inc.  
10  
December 22, 2017  
8SLVD1212 Datasheet  
Applications Information  
Recommendations for Unused Input and Output Pins  
Inputs  
PCLK/nPCLK Inputs  
For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but  
for additional protection, a 1kresistor can be tied from PCLK to ground.  
Outputs  
LVDS Outputs  
All unused LVDS output pairs can be either left floating or terminated with 100across. If they are left floating, there should be no trace  
attached.  
Wiring the Differential Input to Accept Single-Ended Levels  
Figure 13 shows how a differential input can be wired to accept single ended levels. The reference voltage V1 = VDD/2 is generated by  
the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as  
close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1 in the center of the input voltage  
swing. For example, if the input clock swing is 2.5V and VDD = 2.5V, R1 and R2 value should be adjusted to set V1 at 1.25V.  
The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of  
the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched  
termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the  
transmission line impedance. For most 50applications, R3 and R4 can be 100. The values of the resistors can be increased to  
reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential  
signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be  
reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended  
applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Suggested edge  
rate faster than 1V/ns.  
Though some of the recommended components might not be used, the pads should be placed in the layout. They can be used for  
debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal.  
Figure 13. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels  
©2017 Integrated Device Technology, Inc.  
11  
December 22, 2017  
 
8SLVD1212 Datasheet  
2.5V LVPECL Clock Input Interface  
The PCLK /nPCLK accepts LVPECL, LVDS, CML and other differential signals. Both signals must meet the VPP and VCMR input  
requirements. Figure 14 to Figure 18 show interface examples for the PCLK/ nPCLK input driven by the most common driver types. The  
input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please  
consult with the vendor of the driver component to confirm the driver termination requirements.  
Figure 14. PCLK/nPCLK Input Driven by a CML  
Driver  
Figure 15. PCLK/nPCLK Input Driven by a  
2.5V LVPECL Driver w ith AC Couple  
2.5V  
2.5V  
2.5V  
PCLK  
nPCLK  
LVPECL  
Input  
CML  
Figure 16. PCLK/nPCLK Input Driven by a  
Built-In Pullup CML Driver  
Figure 17. PCLK/nPCLK Input Driven by a  
2.5V LVDS Driver  
2.5V  
2.5V  
PCLK  
PCLK  
nPCLK  
nPCLK  
LVPECL  
Input  
CML Built-In Pullup  
Figure 18. PCLK/nPCLK Input Driven by a  
2.5V LVPECL Driver  
2.5V  
2.5V  
2.5V  
PCLK  
nPCLK  
LVPECL  
Input  
LVPECL  
©2017 Integrated Device Technology, Inc.  
12  
December 22, 2017  
 
 
8SLVD1212 Datasheet  
LVDS Driver Termination  
For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90and 132. The actual value  
should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100  
parallel resistor at the receiver and a 100differential transmission-line environment. In order to avoid any transmission-line reflection  
issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS  
compliant devices with two types of output structures: current source and voltage source.  
The standard termination schematic as shown in Figure 19 can be used with either type of output structure. Figure 20, which can also be  
used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value  
should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is  
current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and  
common-mode input range should be verified for compatibility with the output.  
Figure 19. Standard LVDS Termination  
Figure 20. Optional LVDS Termination  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed  
on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts.  
While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e., “heat pipes”) are application specific  
and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis  
and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved  
when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is  
also recommended that the via diameter should be 12 to 13 mils (0.30 to 0.33 mm) with 1oz copper via barrel plating. This is desirable to  
avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug  
and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern.  
Note: These recommendations are to be used as a guideline only.  
©2017 Integrated Device Technology, Inc.  
13  
December 22, 2017  
 
 
8SLVD1212 Datasheet  
For more information, see the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe  
Base Package, Amkor Technology.  
Figure 21. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (Drawing not to Scale)  
Power Considerations (8SLVD1212A)  
This section provides information on power dissipation and junction temperature for the 8SLVD1212. Equations and example calculations  
are also provided.  
1. Power Dissipation.  
The total power dissipation for the 8SLVD1212 is the sum of the core power plus the output power dissipation due to the load. The  
following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.  
The maximum current at 85°C is as follows:  
IDD_MAX = 213mA  
Power (core)MAX = VDD_MAX * IDD_MAX = 2.625V * 213mA = 559.1mW  
Total Power_MAX = 559.1mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that  
the bond wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow  
and a multi-layer board, the appropriate value is 33°C/W per Table 10.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.549W * 33°C/W = 103.1°C. This is below the limit of 125°C.  
©2017 Integrated Device Technology, Inc.  
14  
December 22, 2017  
 
8SLVD1212 Datasheet  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the  
type of board (multi-layer).  
Table 10. Thermal Resistance JA for 40-Lead VFQFN, Forced Convection  
(°C/W) vs. Air Flow (m/s)  
JA  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
33°C/W  
26.3°C/W  
24°C/W  
Reliability Information  
Table 11. JA vs. Air Flow Table for a 40-Lead VFQFN, Forced Convection  
(°C/W) vs. Air Flow (m/s)  
JA  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
33°C/W  
26.3°C/W  
24°C/W  
Transistor Count  
The transistor count for the 8SLVD1212 is: 7829  
Package Outline Draw ings  
The package outline drawings are located at the end of this document. The package information is the most current data available and is  
subject to change without notice or revision of this document.  
Marking Diagram  
1. Line 1 and 2 indicates the part number.  
2. Line 3: “YYWW” is the last digit of the year and week that the part was assembled.  
▪
▪
“#” denotes sequential lot number.  
“$” denotes mark code.  
1. Line 1 and 2 indicates the part number.  
2. Line 3: “YYWW” is the last digit of the year and week that the part was assembled.  
▪
▪
“#” denotes sequential lot number.  
“$” denotes mark code.  
©2017 Integrated Device Technology, Inc.  
15  
December 22, 2017  
8SLVD1212 Datasheet  
Ordering Information  
Orderable Part Number  
Die Revision  
Status  
Package  
Shipping Packaging  
Temperature  
8SLVD1212NLGI  
Tray  
-40°C to 85°C  
Tape and Reel,  
Pin 1 orientation:  
EIA-481-C  
8SLVD1212NLGI8  
-40°C to 85°C  
RoHS 6/6, 6   
6 mm 40-VFQFN  
[a]  
―
NRND  
Tape and Reel,  
Pin 1 orientation:  
EIA-481-D  
8SLVD1212NLGI/W  
8SLVD1212ANLGI  
8SLVD1212ANLGI8  
-40°C to 85°C  
-40°C to 85°C  
-40°C to 85°C  
Tray  
Tape and Reel,  
Pin 1 orientation:  
EIA-481-C  
RoHS 6/6, 6   
6 mm 40-VFQFN  
[b]  
A
Active  
Tape and Reel,  
Pin 1 orientation:  
EIA-481-D  
8SLVD1212ANLGI/W  
-40°C to 85°C  
[a] Not recommended for new designs (see PCN # N1711-01). Last time buy: March 18, 2018.  
[b] Release to production: November 30, 2017.  
Table 12. Pin 1 Orientation in Tape and Reel Packaging  
Part Number Suffix  
Pin 1 Orientation  
Illustration  
CARRIER TAPE TOPSIDE  
(Round Sprocket Holes)  
Correct Pin 1 ORIENTATION  
8
Quadrant 1 (EIA-481-C)  
USER DIRECTION OF FEED  
CARRIER TAPE TOPSIDE  
(Round Sprocket Holes)  
Correct Pin 1 ORIENTATION  
/W  
Quadrant 2 (EIA-481-D)  
USER DIRECTION OF FEED  
©2017 Integrated Device Technology, Inc.  
16  
December 22, 2017  
 
8SLVD1212 Datasheet  
Revision History  
Revision Date  
Description of Change  
▪ Updated footnote [a] in Ordering Information  
December 22, 2017  
December 19, 2017  
▪ Updated Power Considerations (8SLVD1212A)  
▪ Updated the two footnotes in Ordering Information  
November 22, 2017  
Initial release.  
Corporate Headquarters  
Sales  
Tech Support  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
www.IDT.com/go/support  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,  
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same  
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability  
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not  
convey any license under intellectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-  
sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property  
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.  
©2017 Integrated Device Technology, Inc.  
17  
December 22, 2017  
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