8V43FS92432 DATA SHEET
LOAD and GET are inverse command to each other. LOAD updates
the PLL dividers and GET updates the configuration registers. A fast
and convenient way to change the PLL frequency is to use the INC
(increment M) and DEC (decrement M) commands of the
synthesizer. INC (DEC) directly increments (decrements) the
PLL-feedback divider M and immediately changes the PLL
frequency by the smallest step G (see Table 8 for the frequency
granularity G). The INC and DEC commands are designed for
multiple and rapid PLL frequency changes as required in frequency
margining applications. INC and DEC do not require the user to
update the PLL dividers by the LOAD command, INC and DEC do
not update the PLL_L and PLL_H registers either (use LOAD for an
initial PLL divider setting and, if desired, use GET to read the PLL
configuration). Note that the synthesizer does not check any
boundary conditions such as the VCO frequency range. Applying
the INC and DEC commands could result in invalid VCO frequencies
(VCO frequency beyond lock range).
Register 0xF0 (CMD) is a write-only command register.
The purpose of CMD is to provide a fast way to increase or decrease
the PLL frequency and to update the registers. The register accepts
four commands, INC (increment M), DEC (decrement M), LOAD and
GET (update registers). It is recommended to write the INC, DEC
commands only after a valid PLL configuration is achieved. INC and
DEC only affect the M-divider of the PLL (PLL feedback). Applying
INC and DEC commands can result in a PLL configuration beyond
the specified lock range and the PLL may loose lock. The
8V43FS92432 does not verify the validity of any commands such as
LOAD, INC, and DEC. The INC and DEC commands change the
PLL feedback divider without updating PLL_L and PLL_H.
Table 17. CMD (0xF0): PLL Command (Write-Only)
Command
Op-Code
Description
INC
xxxx0001b
(0x01)
Increase internal PLL frequency
M= M+1
Register Maps
DEC
LOAD
GET
xxxx0010b
(0x02)
Decrease internal PLL frequency
M= M-1
Table 14. Configuration Registers
Address Name
Content
Access
R/W
xxxx0100b
(0x04)
Update the PLL divider config.
PLL divider M, N, P= PLL_L, PLL_H
0x00
0x01
PLL_L
Least significant 8 bits of M
PLL_H Most significant 2 bits of M, P, NA,
NB, and lock state
R/W
xxxx1000b
(0x08)
Update the configuration registers
PLL_L, PLL_H= PLL divider M, N, P
0xF0
CMD
Command register (write only)
W only
I2C — Register Access in Parallel Mode
Register 0x00 (PLL_L) contains the least significant bits of the PLL
feedback divider M.
The 8V43FS92432 supports the configuration of the synthesizer
through the parallel interlace (nPLOAD = 0) and serial interface
(nPLOAD = 1). Register contents and the divider configurations are
not changed when the user switches from parallel mode to serial
mode. However, when switching from serial mode to parallel mode,
the PLL dividers immediately reflect the logical state of the hardware
pins M[9:0], NA[2:0], NB, and P.
Table 15. PLL_L (0x00, R/W) Register
Bit
7
6
5
4
3
2
1
0
Name M7
M6
M5
M4
M3
M2
M1
M0
Register content:
Applications using the parallel interface to obtain a PLL configuration
can use the serial interface to verify the divider settings. In parallel
mode (nPLOAD = 0), the 8V43FS92432 allows read-access to
PLL_L and PLL_H through I2C (if nPLOAD = 0, the current PLL
configuration is stored in PLL_L, PLL_H. The GET command is not
necessary and also not supported in parallel mode). After changing
from parallel to serial mode (nPLOAD = 1), the last PLL
configuration is still stored in PLL_L, PLL_H. The user now has full
write and read access to both configuration registers through the I2C
bus and can change the configuration at any time.
M[7:0]
PLL feedback-divider M, bits [7–0]
Register 0x01 (PLL_H) contains the two most significant bits of the
PLL feedback divider M, four bits to control the PLL post-dividers N
and the PLL pre-divider P. The bit 0 in PLL_H register indicates the
lock condition of the PLL and is set by the synthesizer automatically.
The LOCK state is a copy of the PLL lock signal output (LOCK). A
write-access to LOCK has no effect.
Table 16. PLL_H (0x01, R/W) Register
Bit
7
6
5
4
3
2
1
0
Table 18. PLL Configuration in Parallel and Serial Modes
Name M9
M8
NA2 NA1 NA0
NB
P
LOCK
PLL
Configuration
Serial (Registers
PLL_L, PLL_H)
Register content:
M[9:8]
Parallel
Set pins M9–M0
Set pins NA2...NA0
Set pin NB
PLL feedback-divider M, bits 9–8
M[9:0]
NA[2:0]
NB
M[9:0] (R/W)
NA[2:0] (R/W)
NB (R/W)
NA[2:0] PLL post-divider NA, see Table 10
NB
PLL post-divider NB, see Table 11
PLL pre-divider P, see Table 9
P
P
Set pin P
P (R/W)
LOCK
Copy of LOCK output signal (read-only)
LOCK status
LOCK pin 26
LOCK (Read only)
Note that the LOAD command is required to update the PLL dividers
by the content of both PLL_L and PLL_H registers.
1360MHZ DUAL OUTPUT LVPECL CLOCK SYNTHESIZER
12
REVISION 1 10/28/15
