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8V41N012NLGI8

型号:

8V41N012NLGI8

品牌:

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数:

31 页

PDF大小:

840 K

Clock Generator for Cavium Processors  
8V41N012  
Datasheet  
General Description  
Features  
The 8V41N012 is a PLL-based clock generator specifically designed  
for Cavium Networks Octeon II processors. This high performance  
device is optimized to generate the processor core reference clock,  
the PCI-Express, sRIO, XAUI, SerDes reference clocks and the  
clocks for both the Gigabit Ethernet MAC and PHY. The output fre-  
quencies are generated from a 25MHz external input source or an  
external 25MHz parallel resonant crystal. The industrial temperature  
range of the 8V41N012 supports telecommunication, networking,  
and storage requirements.  
Ten selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz  
clocks for PCI Express, sRIO and GbE, HCSL interface levels  
One single-ended QG LVCMOS/LVTTL clock output at 125MHz  
One single-ended QF LVCMOS/LVTTL clock output at 50MHz  
Two single-ended QREFx LVCMOS/LVTTL outputs at 25MHz  
Selectable external crystal or differential (single-ended)  
input source  
Crystal oscillator interface designed for 25MHz, parallel  
resonant crystal  
Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,  
LVHSTL, HCSL input levels  
Internal resistor bias on nCLK pin allows the user to drive CLK  
input with external single-ended (LVCMOS/ LVTTL) input levels  
Supply Modes, (125MHz QG output and 25MHz QREFx outputs):  
Core / Output  
3.3V / 3.3V  
3.3V / 2.5V  
Supply Modes, (HCSL outputs, and 50MHz QF output):  
Core / Output  
3.3V / 3.3V  
Pin Assignment  
-40°C to 85°C ambient operating temperature  
Lead-free (RoHS 6) packaging  
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37  
55  
56  
57  
58  
QE0  
nQE0  
QE1  
36 GND  
nQB1  
34 QB1  
35  
nQB0  
QB0  
33  
nQE1  
GND 59  
32  
31  
30  
29  
28  
27  
60  
VDDO_QB  
OE_A  
GND  
OE_E  
61  
62  
63  
FSEL_C0  
FSEL_C1  
GND  
8V41N012  
nQA1  
QA1  
VDDA 64  
FSEL_D0  
65  
66  
67  
68  
69  
70  
71  
72  
nQA0  
QA0  
26  
25  
24  
FSEL_D1  
VDD  
VDDO_QA  
nMR  
GND  
23  
22 VDD  
VDDO_QG  
QG  
GND  
21  
QF  
20  
GND  
VDDO_QF  
OE_G  
19  
1
2
5 6 7 8 9 10 11 12 13 14 15 16 17 18  
4
72-Lead, 10mm x 10mm VFQFN  
NOTE: Exposed pad must always be connected to GND.  
NOTE: Pin 1 is located at bottom left corner as shown.  
©2016 Integrated Device Technology, Inc.  
1
Revison C, November 2, 2016  
8V41N012 Datasheet  
Block Diagram  
Pulldown  
nMR  
Pullup  
Pullup  
OE_A  
QA0  
00 = 100MHz  
01 = 125MHz  
10 = 156.25MHz  
11 = 312.5MHz  
nQA0  
QA1  
nQA1  
OE_B  
QB0  
00 = 100MHz  
01 = 125MHz  
10 = 156.25MHz  
11 = 312.5MHz  
Pulldown  
2
2
2
2
2
FSEL_A[1:0]  
nQB0  
QB1  
Pulldown  
FSEL_B[1:0]  
Clock  
Output  
Control  
Logic  
nQB1  
OE_C  
Pulldown  
FSEL_C[1:0]  
Pullup  
Pullup  
Pullup  
Pulldown  
FSEL_D[1:0]  
QC0  
00 = 100MHz  
01 = 125MHz  
10 = 156.25MHz  
11 = 312.5MHz  
Pulldown  
nQC0  
QC1  
FSEL_E[1:0]  
nQC1  
OE_D  
QD0  
00 = 100MHz  
01 = 125MHz  
10 = 156.25MHz  
11 = 312.5MHz  
Pullup  
nQD0  
QD1  
PLL_SEL  
nQD1  
OE_E  
Pullup  
REF_SEL  
XTAL_IN  
QE0  
00 = 100MHz  
01 = 125MHz  
10 = 156.25MHz  
11 = 312.5MHz  
OSC  
nQE0  
QE1  
1
0
XTAL_OUT  
FemtoClock NG  
VCO  
1
0
nQE1  
Pulldown  
PU/PD  
CLK  
50MHz  
QF  
nCLK  
Pullup  
Pullup  
OE_G  
QG  
I_REF  
125MHz  
OE_REF  
QREF0  
QREF1  
©2016 Integrated Device Technology, Inc.  
2
Revison C, November 2, 2016  
8V41N012 Datasheet  
Pin Descriptions and Characteristics  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
Active HIGH output enable for QREF0 and QREF1 outputs. LVCMOS/LVTTL  
interface levels.  
0 = QREF0, QREF1 outputs disabled/high impedance  
1 = QREF0, QREF1 outputs enabled (default)  
1
OE_REF  
Input  
Pullup  
2
VDDO_QREF  
Power  
Output  
QREF0, QREF1 output supply pin (LVCMOS/LVTTL). 3.3V or 2.5V supply.  
3,  
4
QREF0,  
QREF1  
Single-ended REF outputs. 3.3V or 2.5V LVCMOS/LVTTL interface levels.  
5, 21, 23,  
29, 36, 43,  
51, 59, 63,  
71  
GND  
Power  
Power supply ground.  
Selects the QEx, nQEx output frequency. LVCMOS/LVTTL interface levels.  
00 = 100MHz (default)  
01 = 125MHz  
10 = 156.25MHz  
11 = 312.5MHz  
6,  
7
FSEL_E0  
FSEL_E1  
Input  
Input  
Pulldown  
Pullup  
Input source control pin. LVCMOS/LVTTL interface levels.  
0 = CLK, nCLK  
1 = XTAL (default)  
8
REF_SEL  
VDD  
9, 22, 45,  
67  
Power  
Input  
Core supply pins.  
10,  
11  
XTAL_IN  
XTAL_OUT  
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.  
PLL bypass control pin. LVCMOS/LVTTL interface levels.  
0 = Bypass mode  
1 = PLL mode (default)  
12  
PLL_SEL  
Input  
Input  
Pullup  
Selects the QAx, nQAx output frequency. LVCMOS/LVTTL interface levels.  
00 = 100MHz (default)  
01 = 125MHz  
10 = 156.25MHz  
11 = 312.5MHz  
13,  
14  
FSEL_A0  
FSEL_A1  
Pulldown  
Pulldown  
15  
16  
CLK  
Input  
Input  
Non-inverting differential clock input.  
Pullup/  
Pulldown  
nCLK  
Inverting differential clock input. Internal resistor bias to VDD/2.  
Selects the QBx, nQBx output frequency. LVCMOS/LVTTL interface levels.  
00 = 100MHz (default)  
01 = 125MHz  
10 = 156.25MHz  
11 = 312.5MHz  
17,  
18  
FSEL_B0  
FSEL_B1  
Input  
Pulldown  
19  
20  
VDDO_QF  
QF  
Power  
Output  
Power  
Output  
Output  
QF output supply pin (LVCMOS/LVTTL). 3.3V supply.  
Single-ended output. 3.3V LVCMOS/LVTTL interface levels.  
Bank A (HCSL) output supply pin. 3.3 V supply.  
24  
VDDO_QA  
QA0, nQA0  
QA1, nQA1  
25, 26  
27, 28  
Bank A differential output pair. HCSL interface levels.  
Bank A differential output pair. HCSL interface levels.  
Active HIGH output enable for Bank A outputs. LVCMOS/LVTTL interface levels.  
0 = Bank A outputs disabled/high impedance  
1 = Bank A outputs enabled (default)  
30  
31  
OE_A  
Input  
Pullup  
VDDO_QB  
Power  
Bank B (HCSL) output supply pin. 3.3V supply.  
Continued on next page  
©2016 Integrated Device Technology, Inc.  
3
Revison C, November 2, 2016  
8V41N012 Datasheet  
Table 1. Pin Descriptions, Continued  
Number  
32, 33  
Name  
Type  
Description  
QB0, nQB0  
QB1, nQB1  
Output  
Output  
Bank B differential output pair. HCSL interface levels.  
34, 35  
Bank B differential output pair. HCSL interface levels.  
Active HIGH output enable for Bank B outputs. LVCMOS/LVTTL interface levels.  
0 = Bank B outputs disabled/high impedance  
1 = Bank B outputs enabled (default)  
37  
OE_B  
Input  
Pullup  
Pullup  
38  
VDDO_QC  
QC0, nQC0  
QC1, nQC1  
Power  
Output  
Output  
Bank C (HCSL) output supply pin. 3.3V supply.  
Bank C differential output pair. HCSL interface levels.  
Bank C differential output pair. HCSL interface levels.  
39, 40  
41, 42  
Active HIGH output enable for Bank C outputs. LVCMOS/LVTTL interface levels.  
0 = Bank C outputs disabled/high impedance  
44  
OE_C  
Input  
1 = Bank C outputs enabled (default)  
46  
VDDO_QD  
Power  
Output  
Bank D (HCSL) output supply pin. 3.3V supply.  
47, 48  
QD0, nQD0  
Bank D differential output pair. HCSL interface levels.  
49, 50  
QD1, nQD1  
Output  
Bank D differential output pair. HCSL interface levels.  
Active HIGH output enable for Bank D outputs. LVCMOS/LVTTL interface levels.  
0 = Bank D outputs disabled/high impedance  
1 = Bank D outputs active (default)  
52  
OE_D  
Input  
Pullup  
External fixed precision resistor (475) from this pin to ground provides a  
reference current used for differential current-mode.  
53  
IREF  
Input  
54  
VDDO_QE  
Power  
Output  
Bank E (HCSL) output supply pin. 3.3V supply.  
55, 56  
QE0, nQE0  
Bank E differential output pair. HCSL interface levels.  
57, 58  
QE1, nQE1  
Output  
Bank E differential output pair. HCSL interface levels.  
Active HIGH output enable for Bank E outputs. LVCMOS/LVTTL interface levels.  
0 = Bank E outputs disabled/high impedance  
60  
OE_E  
Input  
Pullup  
1 = Bank E outputs enabled (default)  
Selects the QCx, nQCx output frequency. LVCMOS/LVTTL interface levels.  
00 = 100MHz (default)  
01 = 125MHz  
10 = 156.25MHz  
11 = 312.5MHz  
61,  
62  
FSEL_C0  
FSEL_C1  
Input  
Power  
Input  
Pulldown  
64  
VDDA  
Analog supply pin.  
Selects the QDx, nQDx output frequency. LVCMOS/LVTTL interface levels.  
00 = 100MHz (default)  
01 = 125MHz  
10 = 156.25MHz  
11 = 312.5MHz  
Active LOW Master Reset. LVCMOS/LVTTL interface levels.  
0 = Reset. The internal dividers are reset causing the true outputs Qx to go low and  
the inverted outputs nQx to go high. (default)  
1 = Active. The internal dividers and the outputs are active.  
65,  
66  
FSEL_D0  
FSEL_D1  
Pulldown  
Pulldown  
68  
nMR  
Input  
69  
70  
VDDO_QG  
QG  
Power  
Output  
QG output supply pins (LVCMOS/LVTTL). 3.3V or 2.5V supply.  
Bank G single-ended output. 3.3V or 2.5V LVCMOS/LVTTL interface levels.  
Active HIGH output enable for Bank G output. LVCMOS/LVTTL interface levels.  
0 = Bank G outputs disabled/high impedance  
1 = Bank G outputs enabled (default)  
72  
OE_G  
EPAD  
Input  
Pullup  
Connect to GND.  
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
©2016 Integrated Device Technology, Inc.  
4
Revison C, November 2, 2016  
8V41N012 Datasheet  
Table 2. Pin Characteristics  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
2.5  
6
Maximum  
Units  
pF  
CLK, nCLK  
Control Pins  
Input  
Capacitance  
CIN  
pF  
RPULLUP  
Input Pullup Resistor  
Input Pulldown Resistor  
QF, QG,  
50  
k  
RPULLDOWN  
50  
k  
VDDO_QF = VDDO_QG  
VDDO_QREF = 3.465V  
=
15  
19  
QREF[1:0]  
Output  
ROUT  
Impedance  
QG,  
VDDO_QREF, VDDO_QG = 2.625V  
QREF[1:0]  
Function Tables  
Table 3A. FSEL_X Control Input Function Table  
Table 3D. OE_[A:E] Control Input Function Table  
Input  
Output Frequency  
Q[Ax:Ex], nQ[Ax:Ex]  
100MHz  
Input  
OE_[A:E]  
0
Outputs  
FSEL_X[1:0]  
Q[Ax:Ex], nQ[Ax:Ex]  
High-Impedance  
Enabled  
00 (default)  
01  
10  
11  
125MHz  
1 (default)  
156.25MHz  
312.50MHz  
Table 3E. OE_G Control Input Function Table  
NOTE: FSEL_X denotes FSEL_A, _B, _C, _D, _E.  
NOTE: Any two outputs operated at the same frequency will be  
synchronous.  
Input  
OE_G  
0
Outputs  
QG  
High-Impedance  
Enabled  
Table 3B. PLL_SEL Control Input Function Table  
Input  
1 (default)  
PLL_SEL  
0
Operation  
PLL Bypass  
PLL Mode  
Table 3F. OE_REF Control Input Function Table  
1 (default)  
Input  
OE_REF  
0
Output  
QREF[1:0]  
High-Impedance  
Enabled  
Table 3C. REF_SEL Control Input Function Table  
Input  
1 (default)  
REF_SEL  
0
Clock Source  
CLK, nCLK  
1 (default)  
XTAL_IN, XTAL_OUT  
©2016 Integrated Device Technology, Inc.  
5
Revison C, November 2, 2016  
8V41N012 Datasheet  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress  
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC  
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VDD  
3.6V  
Inputs, VI  
XTAL_IN  
0V to 2V  
Other Inputs  
-0.5V to VDD + 0.5V  
Outputs, VO  
-0.5V to VDDO_QX + 0.5V  
26.6°C/W (0 mps)  
-65C to 150C  
Package Thermal Impedance, JA  
Storage Temperature, TSTG  
DC Electrical Characteristics  
Table 4A. Power Supply DC Characteristics,  
V
= 3.3V ± 5%, V  
= V  
= V  
= 3.3V ± 5%, T = -40°C to 85°C  
DD  
DDO_Q[A:E]  
DDO_Q[F:G]  
DDO_QREF A  
Symbol  
VDD  
Parameter  
Core Supply Voltage  
Test Conditions  
Minimum  
3.135  
Typical  
3.3  
Maximum  
3.465  
VDD  
Units  
V
VDDA  
Analog Supply Voltage  
Output Supply Voltage  
Power Supply Current  
Analog Supply Current  
Output Supply Current  
VDD – 0.225  
3.135  
3.3  
V
VDDO_QX  
IDD  
3.3  
3.465  
235  
V
193  
36  
mA  
mA  
mA  
IDDA  
45  
IDDO_QX  
No Load  
24  
30  
NOTE: VDDO_QX denotes VDDO_Q[A:E], VDDO_Q[F:G], VDDO_QREF.  
NOTE: IDDO_QX denotes IDDO_Q[A:E] + IDDO_Q[F:G] + IDDO_QREF.  
Table 4B. Power Supply DC Characteristics, V = 3.3V ± 5%, V  
= V  
= 2.5V ± 5%, T = -40°C to 85°C  
DDO_QREF A  
DD  
DDO_QG  
Symbol  
VDD  
Parameter  
Test Conditions  
Minimum  
Typical  
3.3  
Maximum  
3.465  
Units  
Core Supply Voltage  
Analog Supply Voltage  
3.135  
V
V
VDDA  
VDD – 0.225  
2.375  
3.3  
VDD  
VDDO_QG  
VDDO_QREF  
/
Output Supply Voltage  
2.5  
2.625  
V
IDD  
Power Supply Current  
Analog Supply Current  
193  
36  
235  
45  
mA  
mA  
IDDA  
IDDO_QG  
IDDO_QREF  
+
Output Supply Current  
No Load  
8
15  
mA  
©2016 Integrated Device Technology, Inc.  
6
Revison C, November 2, 2016  
8V41N012 Datasheet  
Table 4C. LVCMOS/LVTTL DC Characteristics,  
= V = V = 3.3V ± 5%; V  
V
= V  
= 3.3V ± 5% or 2.5V ± 5%, T = -40°C to 85°C  
DD  
DDO_Q[A:E]  
DDO_QF  
DDO_QG  
DDO_QREF  
A
Symbol Parameter  
Test Conditions  
Minimum  
2.2  
Typical  
Maximum Units  
VIH  
VIL  
Input High Voltage  
Input Low Voltage  
VDD + 0.3  
0.8  
V
V
-0.3  
nMR, FSEL_A[1:0],  
FSEL_B[1:0], FSEL_C[1:0],  
FSEL_D[1:0], FSEL_E[1:0]  
V
DD = VIN = 3.465V  
150  
10  
µA  
uA  
µA  
uA  
Input  
High  
Current  
IIH  
REF_SEL, PLL_SEL,  
OE_REF, OE_A, OE_B,  
OE_C, OE_D, OE_E, OE_G  
VDD = VIN = 3.465V  
nMR, FSEL_A[1:0],  
FSEL_B[1:0], FSEL_C[1:0],  
FSEL_D[1:0], FSEL_E[1:0]  
V
DD = 3.465V, VIN = 0V  
DD = 3.465V, VIN = 0V  
-10  
Input  
Low  
Current  
IIL  
REF_SEL, PLL_SEL,  
OE_REF, OE_A, OE_B,  
OE_C, OE_D, OE_E, OE_G  
V
-150  
VDDO_QF = VDDO_QG,  
VDDO_QREF = 3.465V  
2.6  
1.8  
V
V
VOH  
Output High Voltage  
Output Low Voltage  
VDDO_QG, VDDO_QREF = 2.625V  
VDDO_QF = VDDO_QG,  
VDDO_QREF = 3.465V or  
VOL  
0.6  
V
VDDO_QG, VDDO_QREF = 2.625V  
Table 4D. Differential DC Characteristics, V = 3.3V ± 5%, T = -40°C to 85°C  
DD  
A
Symbol Parameter  
IIH Input High Current  
Test Conditions  
Minimum  
Typical  
Maximum Units  
CLK, nCLK  
VDD = VIN = 3.465V  
150  
µA  
µA  
µA  
V
CLK  
V
DD = 3.465V, VIN = 0V  
-5  
IIL  
Input Low Current  
nCLK  
VDD = 3.465V, VIN = 0V  
-150  
0.15  
0.5  
VPP  
Peak-to-Peak Input Voltage; NOTE 1  
1.3  
VCMR  
Common Mode Input Voltage; NOTE 1, 2  
VDD – 0.85  
V
NOTE 1: VIL should not be less than -0.3V.  
NOTE 2: Common mode voltage is defined as VIH.  
Table 5. Crystal Characteristics  
Parameter  
Test Conditions  
Minimum  
Typical  
Fundamental  
25  
Maximum Units  
Mode of Oscillation  
Frequency  
MHz  
Equivalent Series Resistance (ESR)  
Load Capacitance (CL)  
Shunt Capacitance  
50  
7
12  
pF  
pF  
©2016 Integrated Device Technology, Inc.  
7
Revison C, November 2, 2016  
8V41N012 Datasheet  
Table 6. Input Frequency Characteristics,  
= V = V = 3.3V ± 5%; V  
V
= V  
= 3.3V ± 5% or 2.5V ± 5%, T = -40°C to 85°C  
DD  
DDO_Q[A:E]  
DDO_QF  
DDO_QG  
DDO_QREF  
A
Typical  
25  
Symbol Parameter  
Test Conditions  
Minimum  
Maximum  
Units  
CLK, nCLK  
MHz  
Input  
FIN  
XTAL_IN,  
XTAL_OUT  
Frequency  
25  
MHz  
AC Electrical Characteristics  
Table 7A. PCI Express Jitter Specifications, V = V  
= 3.3V ± 5%, T = -40°C to 85°C  
A
DD  
DDO_Q[A:E]  
PCIe Industry  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum Specification Units  
Phase Jitter  
Peak-to-Peak;  
NOTE 1, 4  
ƒ = 100MHz, 25MHz Crystal Input  
Evaluation Band: 0Hz - Nyquist  
(clock frequency/2)  
tj  
6.97  
11.18  
86  
ps  
(PCIe Gen 1)  
ƒ = 100MHz, 25MHz Crystal Input  
High Band: 1.5MHz - Nyquist  
(clock frequency/2)  
tREFCLK_HF_RMS  
(PCIe Gen 2)  
Phase Jitter  
RMS; NOTE 2, 4  
0.70  
0.03  
0.16  
1.84  
0.07  
0.49  
3.10  
3.0  
ps  
ps  
ps  
tREFCLK_LF_RMS  
(PCIe Gen 2)  
Phase Jitter  
RMS; NOTE 2, 4  
ƒ = 100MHz, 25MHz Crystal Input  
Low Band: 10kHz - 1.5MHz  
ƒ = 100MHz, 25MHz Crystal Input  
Evaluation Band: 0Hz - Nyquist  
(clock frequency/2)  
tREFCLK_RMS  
(PCIe Gen 3)  
Phase Jitter  
RMS; NOTE 3, 4  
0.8  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device  
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal  
equilibrium has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the  
datasheet.  
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen  
1 is 86ps peak-to-peak for a sample size of 106 clock periods.  
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and  
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS  
(High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).  
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express  
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.  
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.  
©2016 Integrated Device Technology, Inc.  
8
Revison C, November 2, 2016  
8V41N012 Datasheet  
Table 7B. HCSL AC Characteristics,  
V
= V  
= V  
= 3.3V ± 5%; V  
= V  
= 3.3V ± 5% or 2.5V ± 5%, T = -40°C to 85°C  
DD  
DDO_Q[A:E]  
DDO_QF  
DDO_QG  
DDO_QREF  
A
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum Units  
FSEL_x[1:0] = 00  
FSEL_x[1:0] = 01  
FSEL_x[1:0] = 10  
FSEL_x[1:0] = 11  
100  
125  
MHz  
MHz  
MHz  
MHz  
Q[A:E],  
nQ[A:E]  
fOUT  
Output Frequency  
156.25  
312.5  
Ring-Back Voltage Margin;  
NOTE 1, 2  
Q[A:E],  
nQ[A:E]  
VRB  
-100  
500  
100  
mV  
ps  
Time before VRB is allowed;  
NOTE 1, 2  
Q[A:E],  
nQ[A:E]  
tSTABLE  
VMAX  
VMIN  
Absolute Max Output Voltage;  
NOTE 3, 4  
Q[A:E],  
nQ[A:E]  
1150  
mV  
mV  
mV  
mV  
V/ns  
V/ns  
%
Absolute Min Output Voltage;  
NOTE 3, 5  
Q[A:E],  
nQ[A:E]  
-300  
175  
Absolute Crossing Voltage;  
NOTE 3, 6, 7  
Q[A:E],  
nQ[A:E]  
VCROSS  
550  
140  
4.0  
VCROS Total Variation of VCROSS over Q[A:E],  
All Edges; NOTE 3, 6, 8  
nQ[A:E]  
S
Q[A:E],  
nQ[A:E]  
tSLEW+  
Rising Edge Rate; NOTE 1, 9  
0.6  
0.6  
48  
Q[A:E],  
nQ[A:E]  
tSLEW-  
odc  
Falling Edge Rate; NOTE 1, 9  
Output Duty Cycle  
4.0  
Q[A:E],  
nQ[A:E]  
50  
52  
100MHz, Integration Range:  
(12kHz to 20MHz)  
0.32  
0.31  
0.30  
0.29  
0.45  
0.45  
0.45  
0.45  
ps  
125MHz, Integration Range:  
(12kHz to 20MHz)  
ps  
RMS Phase Jitter, (Random);  
NOTE 10  
Q[A:E],  
nQ[A:E]  
tjit(Ø)  
156.25MHz, Integration Range:  
(12kHz to 20MHz)  
ps  
312.5MHz, Integration Range:  
(12kHz to 20MHz)  
ps  
tjit(RJ)  
tjit(DJ)  
Random Jitter, RMS; NOTE 11  
2
1
5
3
ps  
ps  
Q[A:E], nQ[A:E] = 125MHz,  
25MHz XTAL, PLL Mode  
Deterministic Jitter, Pk-to-Pk; NOTE 11  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE: All parameters measured at f  
and in PLL mode unless noted otherwise.  
OUT  
NOTE: Refer to applications section for information on peak-to-peak jitter calculations.  
NOTE 1: Measurement taken from differential waveform.  
NOTE 2: t  
is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is  
STABLE  
allowed to drop back into the V ±100mV range. See Parameter Measurement Information Section.  
RB  
NOTE 3: Measurement taken from single-ended waveform.  
NOTE 4: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.  
NOTE 5: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.  
NOTE 6: Measured at the crossing point where the instantaneous voltage value of the rising edge of Q[Ax:Ex] equals the falling edge of  
nQ[Ax:Ex].  
NOTE 7: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing  
points for this measurement.  
Notes continued on next page.  
©2016 Integrated Device Technology, Inc.  
9
Revison C, November 2, 2016  
8V41N012 Datasheet  
NOTE 8: Defined as the total variation of all crossing voltages of rising Q[Ax:Ex] and falling nQ[Ax:Ex]. This is the maximum allowed variance in  
Vcross for any particular system.  
NOTE 9: Measured from -150mV to +150mV on the differential waveform (derived from Q[Ax:Ex] minus nQ[Ax:Ex]). The signal must be  
monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.  
NOTE 10: Measurements taken with 25MHz XTAL as input source and spur off.  
NOTE 11: Measurements taken with Wavecrest SIA-3000 Analyzer.  
Table 7C. LVCMOS AC Characteristics,  
V
= V  
= V  
= 3.3V ± 5%; V  
= V  
= 3.3V ± 5% or 2.5V ± 5%, T = -40°C to 85°C  
DDO_QREF A  
DD  
DDO_Q[A:E]  
DDO_QF  
DDO_QG  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
50  
Maximum Units  
QF  
MHz  
MHz  
MHz  
fOUT  
Output Frequency  
QG  
125  
25  
QREF[1:0]  
QF, QG,  
QREF[1:0]  
tr/tf  
Output Rise/Fall Time  
Output Duty Cycle  
20% to 80%  
180  
47  
700  
53  
ps  
%
QF, QG,  
QREF[1:0]  
odc  
50  
0.35  
0.30  
0.32  
2
50MHz, Integration Range:  
(12kHz to 20MHz)  
QF  
0.45  
0.40  
0.40  
5
ps  
ps  
ps  
ps  
ps  
RMS Phase Jitter, (Random);  
NOTE 1  
125MHz, Integration Range:  
(12kHz to 20MHz)  
tjit(Ø)  
QG  
25MHz, Integration Range:  
(12kHz to 5MHz)  
QREF[1:0]  
QF, QG,  
QREF[1:0]  
Q[A:E], nQ[A:E] = 125MHz,  
25MHz XTAL, PLL Mode  
tjit(RJ)  
tjit(DJ)  
Random Jitter, RMS; NOTE 2  
Q[A:E], nQ[A:E] = 125MHz,  
25MHz XTAL, PLL Mode  
QF  
3
25  
Deterministic Jitter, Pk-to-Pk;  
NOTE 2  
QG  
1
1
5
3
ps  
ps  
QREF[1:0]  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device  
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal  
equilibrium has been reached under these conditions.  
NOTE: All parameters measured at fOUT and in PLL mode unless noted otherwise.  
NOTE: Refer to applications section for information on peak-to-peak jitter calculations.  
NOTE 1: Measurements taken with 25MHz XTAL as input source and spur off.  
NOTE 2: Measurements taken with Wavecrest SIA-3000 Analyzer. QG characterized with QREF[1:0] disabled.  
©2016 Integrated Device Technology, Inc.  
10  
Revison C, November 2, 2016  
8V41N012 Datasheet  
Typical Phase Noise at 156.25MHz  
Offset Frequency (Hz)  
©2016 Integrated Device Technology, Inc.  
11  
Revison C, November 2, 2016  
8V41N012 Datasheet  
Parameter Measurement Information  
2.05V±5%  
1.25V±5%  
1.65V±5%  
1.65V±5%  
2.05V±5%  
SCOPE  
V
V
V
DD,  
V
DD  
SCOPE  
DDO_Q[F:G],  
DDO_QREF  
V
VDDA  
DDO_QG,  
Qx  
V
DDO_QREF  
Qx  
VDDA  
GND  
GND  
-1.65V±5%  
-1.25V±5%  
3.3V Core/3.3V LVCMOS Output Load Test Circuit  
3.3V Core/2.5V LVCMOS Output Load Test Circuit  
3.3V±5%  
3.3V±5%  
3.3V±5%  
3.3V±5%  
SCOPE  
V
DD,  
50  
50  
V
V
DD,  
V
DDO_Q[A:E]  
DDO_Q[A:E]  
V
DDA  
V
DDA  
IREF  
GND  
0V  
475  
0V  
This load condition is used for VMAX , VMIN, VRB, STABLE,  
t
This load condition is used for tjit and odc measurements.  
VCROSS, VCROSS and tSLEW± measurements.  
3.3V Core/3.3V HCSL Output Load Test Circuit 1  
3.3V Core/3.3V HCSL Output Load Test Circuit 2  
V
DD  
nCLK  
CLK  
VPP  
VCMR  
Cross Points  
GND  
Differential Input Level  
RMS Phase Jitter  
©2016 Integrated Device Technology, Inc.  
12  
Revison C, November 2, 2016  
8V41N012 Datasheet  
Parameter Measurement Information, continued  
QF, QG,  
QREF[1:0]  
80%  
80%  
tR  
20%  
20%  
QF, QG,  
QREF[1:0]  
tF  
LVCMOS Output Duty Cycle/Pulse Width  
LVCMOS Output Rise/Fall Time  
Differential Measurement Points for Rise/Fall Time  
Edge Rate  
Single-ended Measurement Points for Absolute Cross  
Point/Swing  
Single-ended Measurement Points for Delta Cross Point  
Differential Measurement Points for Ringback  
©2016 Integrated Device Technology, Inc.  
13  
Revison C, November 2, 2016  
8V41N012 Datasheet  
Parameter Measurement Information, continued  
Differential Measurement Points for Duty Cycle/Period  
©2016 Integrated Device Technology, Inc.  
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Revison C, November 2, 2016  
8V41N012 Datasheet  
Applications Information  
Peak-to-Peak Jitter Calculations  
A standard deviation of a statistical population or data set is the  
square root of its variance. A standard deviation is used to calculate  
the probability of an anomaly or to predict a failure. Many times, the  
term "root mean square" (RMS) is used synonymously for standard  
deviation. This is accurate when referring to the square root of the  
mean squared deviation of a signal from a given baseline and when  
the data set contains a Gaussian distribution with no deterministic  
components. A low standard deviation indicates that the data set is  
close to the mean with little variation. A large standard deviation  
indicates that the data set is spread out and has a large variation from  
the mean.  
Table 8. BER Table  
RMS Multiplier Data,  
RMS Multiplier Clock,  
“DTD = 1”  
BER  
“DTD = 0.5”  
10-3  
6.180  
6.582  
7.782  
10-4  
7.438  
10-5  
8.530  
8.834  
10-6  
9.507  
9.784  
10-7  
10.399  
11.224  
11.996  
12.723  
13.412  
14.069  
14.698  
15.301  
15.883  
10.654  
11.462  
12.218  
12.934  
13.614  
14.260  
14.882  
15.478  
16.028  
10-8  
A standard deviation is required when calculating peak-to-peak jitter.  
Since true peak-to-peak jitter is random and unbounded, it is  
important to always associate a bit error ratio (BER) when specifying  
a peak-to-peak jitter limit. Without it, the specification does not have  
a boundary and will continue get larger with sample size. Given that  
a BER is application specific, many frequency timing devices specify  
jitter as an RMS. This allows the peak-to-peak jitter to be calculated  
for the specific application and BER requirement. Because a  
standard deviation is the variation from the mean of the data set, it is  
important to always calculate the peak-to-peak jitter using the typical  
RMS value.  
10-9  
10-10  
10-11  
10-12  
10-13  
10-14  
10-15  
Table 8 shows the BER with its appropriate RMS Multiplier. There are  
two columns for the RMS multiplier, one should be used if your signal  
is data and the other should be used if the signal is a repetitive clock  
signal. The difference between the two is the data transition density  
(DTD). The DTD is the number of rising or falling transitions divided  
by the total number of bits. For a clock signal, they are equal, hence  
the DTD is 1. For Data, on average, most common encoding  
standards have a 0.5 DTD.  
Once the BER is chosen, there are two circumstances to consider. Is  
the data set purely Gaussian or does it contains any deterministic  
component? If it is Gaussian, then the peak to peak jitter can be  
calculated by simply multiplying the RMS multiplier with the typical  
RMS specification. For example, if a 10-12 BER is required for a clock  
signal, multiply 14.260 times the typical jitter specification.  
Jitter (peak-to-peak) = RMS Multiplier * RMS (typical)  
If the datasheet contains deterministic components, then the random  
jitter (RJ) and deterministic jitter (DJ) must be separated and  
analyzed separately. RJ, also known as Gaussian jitter, is not  
bounded and the peak-to-peak will continue to get larger as the  
sample size increases. Alternatively, peak-to-peak value of DJ is  
bounded and can easily be observed and predicted. Therefore, the  
peak to peak jitter for the random component must be added to the  
deterministic component. This is called total jitter (TJ).  
Total Jitter (peak-to-peak) = [RMS Multiplier * Random Jitter (RJ)]  
+ Deterministic Jitter (DJ)  
The total jitter equation is not specific to one type of jitter  
classification. It can be used to calculate BER on various types of  
RMS jitter. It is important that the user understands their jitter  
requirement to ensure they are calculating the correct BER for their  
jitter requirement.  
NOTE: Use RJ and DJ values from AC Characteristics Tables 7B and  
7C to calculate TJ.  
©2016 Integrated Device Technology, Inc.  
15  
Revison C, November 2, 2016  
8V41N012 Datasheet  
Wiring the Differential Input to Accept Single-Ended Levels  
Figure 1 shows how a differential input can be wired to accept single  
ended levels. The reference voltage V1= VDD/2 is generated by the  
bias resistors R1 and R2. The bypass capacitor (C1) is used to help  
filter noise on the DC bias. This bias circuit should be located as  
close to the input pin as possible. The ratio of R1 and R2 might need  
to be adjusted to position the V1in the center of the input voltage  
swing. For example, if the input clock is driven from a single-ended  
2.5V LVCMOS driver and the DC offset (or swing center) of this signal  
is 1.25V, the R1 and R2 values should be adjusted to set the V1 at  
1.25V. The values below are for when both the single ended swing  
and VDD are at the same voltage. This configuration requires that the  
sum of the output impedance of the driver (Ro) and the series  
resistance (Rs) equals the transmission line impedance. In addition,  
matched termination at the input will attenuate the signal in half. This  
can be done in one of two ways. First, R3 and R4 in parallel should  
equal the transmission line impedance. For most 50applications,  
R3 and R4 can be 100. The values of the resistors can be increased  
to reduce the loading for slower and weaker LVCMOS driver. When  
using single-ended signaling, the noise rejection benefits of  
differential signaling are reduced. Even though the differential input  
can handle full rail LVCMOS signaling, it is recommended that the  
amplitude be reduced while maintaining an edge rate faster than  
1V/ns. The datasheet specifies a lower differential amplitude,  
however this only applies to differential signals. For single-ended  
applications, the swing can be larger, however VIL cannot be less  
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some  
of the recommended components might not be used, the pads should  
be placed in the layout. They can be utilized for debugging purposes.  
The datasheet specifications are characterized and guaranteed by  
using a differential signal.  
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels  
©2016 Integrated Device Technology, Inc.  
16  
Revison C, November 2, 2016  
8V41N012 Datasheet  
Differential Clock Input Interface  
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other  
differential signals. Both VSWING and VOH must meet the VPP and  
VCMR input requirements. Figures 2A to 2E show interface examples  
for the CLK/nCLK input driven by the most common driver types. The  
input interfaces suggested here are examples only. Please consult  
with the vendor of the driver component to confirm the driver  
termination requirements. For example, in Figure 2A, the input  
termination applies for IDT open emitter LVHSTL drivers. If you are  
using an LVHSTL driver from another vendor, use their termination  
recommendation.  
3.3V  
1.8V  
Zo = 50  
CLK  
Zo = 50Ω  
nCLK  
Differential  
Input  
LVHSTL  
R1  
50Ω  
R2  
50Ω  
IDT  
LVHSTL Driver  
Figure 2A. CLK/nCLK Input Driven by an  
IDT Open Emitter LVHSTL Driver  
Figure 2B. CLK/nCLK Input Driven by a  
3.3V LVPECL Driver  
3.3V  
3.3V  
*R3  
*R4  
CLK  
nCLK  
Differential  
Input  
HCSL  
Figure 2C. CLK/nCLK Input Driven by a  
3.3V LVPECL Driver  
Figure 2D. CLK/nCLK Input Driven by a  
3.3V HCSL Driver  
Figure 2E. CLK/nCLK Input Driven by a 3.3V LVDS Driver  
©2016 Integrated Device Technology, Inc.  
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Revison C, November 2, 2016  
8V41N012 Datasheet  
Overdriving the XTAL Interface  
The XTAL_IN input can be overdriven by an LVCMOS driver or by  
one side of a differential driver through an AC coupling capacitor. The  
XTAL_OUT pin can be left floating. The amplitude of the input signal  
should be between 500mV and 1.8V and the slew rate should not be  
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be  
reduced from full swing to at least half the swing in order to prevent  
signal interference with the power rail and to reduce internal noise.  
Figure 3A shows an example of the interface diagram for a high  
speed 3.3V LVCMOS driver. This configuration requires that the sum  
of the output impedance of the driver (Ro) and the series resistance  
(Rs) equals the transmission line impedance. In addition, matched  
termination at the crystal input will attenuate the signal in half. This  
can be done in one of two ways. First, R1 and R2 in parallel should  
equal the transmission line impedance. For most 50applications,  
R1 and R2 can be 100. This can also be accomplished by removing  
R1 and changing R2 to 50. The values of the resistors can be  
increased to reduce the loading for a slower and weaker LVCMOS  
driver. Figure 3B shows an example of the interface diagram for an  
LVPECL driver. This is a standard LVPECL termination with one side  
of the driver feeding the XTAL_IN input. It is recommended that all  
components in the schematics be placed in the layout. Though some  
components might not be used, they can be utilized for debugging  
purposes. The datasheet specifications are characterized and  
guaranteed by using a quartz crystal as the input.  
VCC  
XTAL_OUT  
R1  
100  
C1  
Rs  
Zo = 50 ohms  
Ro  
XTAL_IN  
.1uf  
R2  
100  
Zo = Ro + Rs  
LVCMOS Driver  
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface  
XTAL_OUT  
C2  
Zo = 50 ohms  
XTAL_I N  
.1uf  
Zo = 50 ohms  
R1  
50  
R2  
50  
LVPECL Driver  
R3  
50  
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface  
©2016 Integrated Device Technology, Inc.  
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Revison C, November 2, 2016  
8V41N012 Datasheet  
Recommended Termination  
Figure 4A is the recommended source termination for applications  
where the driver and receiver will be on a separate PCBs. This  
termination is the standard for PCI Express™ and HCSL output  
types. All traces should be 50impedance single-ended or 100Ω  
differential.  
Rs  
0.5" Max  
L1  
0-0.2"  
L2  
1-14"  
L4  
0.5 - 3.5"  
L5  
22 to 33 +/-5%  
L1  
L2  
L4  
L5  
PCI Express  
Connector  
PCI Express  
Driver  
PCI Express  
Add-in Card  
0-0.2" L3  
L3  
49.9 +/- 5%  
Rt  
Figure 4A. Recommended Source Termination (where the driver and receiver will be on separate PCBs)  
Figure 4B is the recommended termination for applications where a  
point-to-point connection can be used. A point-to-point connection  
contains both the driver and the receiver on the same PCB. With a  
matched termination at the receiver, transmission-line reflections will  
be minimized. In addition, a series resistor (Rs) at the driver offers  
flexibility and can help dampen unwanted reflections. The optional  
resistor can range from 0to 33. All traces should be 50Ω  
impedance single-ended or 100differential.  
Rs  
0.5" Max  
L1  
0-18"  
L2  
0-0.2"  
L3  
0 to 33  
0 to 33  
L1  
L2  
L3  
PCI Express  
Driver  
49.9 +/- 5%  
Rt  
Figure 4B. Recommended Termination (where a point-to-point connection can be used)  
©2016 Integrated Device Technology, Inc.  
19  
Revison C, November 2, 2016  
8V41N012 Datasheet  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 5. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally/  
Electrically Enhance Leadframe Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
SOLDER  
SOLDER  
PIN  
PIN  
EXPOSED HEAT SLUG  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
Recommendations for Unused Input and Output Pins  
Inputs:  
Outputs:  
LVCMOS Control Pins  
LVCMOS Outputs  
All control pins have internal pullups or pulldowns; additional  
resistance is not required but can be added for additional protection.  
A 1kresistor can be used.  
All unused LVCMOS outputs can be left floating. There should be no  
trace attached.  
Differential Outputs  
Crystal Inputs  
All unused differential outputs can be left floating. We recommend  
that there is no trace attached. Both sides of the differential output  
pair should either be left floating or terminated.  
For applications not requiring the use of the crystal oscillator input,  
both XTAL_IN and XTAL_OUT can be left floating. Though not  
required, but for additional protection, a 1kresistor can be tied from  
XTAL_IN to ground.  
CLK/nCLK Inputs  
For applications not requiring the use of the differential input, both  
CLK and nCLK can be left floating. Though not required, but for  
additional protection, a 1kresistor can be tied from CLK to ground.  
©2016 Integrated Device Technology, Inc.  
20  
Revison C, November 2, 2016  
8V41N012 Datasheet  
PCI Express Application Note  
PCI Express jitter analysis methodology models the system  
response to reference clock jitter. The block diagram below shows  
the most frequently used Common Clock Architecture in which a  
copy of the reference clock is provided to both ends of the PCI  
Express Link.  
In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs  
are modeled as well as the phase interpolator in the receiver. These  
transfer functions are called H1, H2, and H3 respectively. The overall  
system transfer function at the receiver is:  
Hts= H3s  H1s– H2s  
The jitter spectrum seen by the receiver is the result of applying this  
system transfer function to the clock spectrum X(s) and is:  
Ys= Xs  H3s  H1s– H2s  
PCIe Gen 2A Magnitude of Transfer Function  
In order to generate time domain jitter numbers, an inverse Fourier  
Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].  
PCI Express Common Clock Architecture  
PCIe Gen 2B Magnitude of Transfer Function  
For PCI Express Gen 1, one transfer function is defined and the  
evaluation is performed over the entire spectrum: DC to Nyquist (e.g  
for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is  
reported in peak-peak.  
For PCI Express Gen 3, one transfer function is defined and the  
evaluation is performed over the entire spectrum. The transfer  
function parameters are different from Gen 1 and the jitter result is  
reported in RMS.  
PCIe Gen 1 Magnitude of Transfer Function  
PCIe Gen 3 Magnitude of Transfer Function  
For PCI Express Gen 2, two transfer functions are defined with 2  
evaluation ranges and the final jitter number is reported in RMS. The  
two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz  
(Low Band) and 1.5MHz – Nyquist (High Band). The plots show the  
individual transfer functions as well as the overall transfer function Ht.  
For a more thorough overview of PCI Express jitter analysis  
methodology, please refer to IDT Application Note PCI Express  
Reference Clock Requirements.  
©2016 Integrated Device Technology, Inc.  
21  
Revison C, November 2, 2016  
8V41N012 Datasheet  
Schematic Example  
Figure 6 (next page) shows an example of 8V41N012 application  
schematic. In this example, the device is operated at VDD = VDDA  
VDDO_Qx = 3.3V. The schematic example focuses on functional  
connections and is not configuration specific. Refer to the pin  
description and functional tables in the datasheet to ensure that the  
logic control inputs are properly set.  
As with any high speed analog circuitry, the power supply pins are  
vulnerable to random noise. To achieve optimum jitter performance,  
power supply isolation is required. The 8V41N012 provides separate  
power supplies to isolate any high switching noise from coupling into  
the internal PLL.  
=
In order to achieve the best possible filtering, it is recommended that  
the placement of the filter components be on the device side of the  
PCB as close to the power pins as possible. If space is limited, the  
0.1µF capacitor in each power pin filter should be placed on the  
device side. The other components can be on the opposite side of the  
PCB.  
A 12pF parallel resonant 25MHz crystal is used. For this device, the  
crystal load capacitors are required for proper operation. The load  
capacitance, C1 = C2 = 2pF, are recommended for frequency  
accuracy. Depending on the variation of the parasitic stray capacity  
of the printed circuit board traces between the crystal and the Xtal_In  
and Xtal_Out pins, the values of C1 and C2 might require a slight  
adjustment to optimize the frequency accuracy. Crystals with other  
load capacitance specifications can be used, but this will require  
adjusting C1 and C2. When designing the circuit board, return the  
capacitors to ground though a single point contact close to the  
package. Two Fox crystal options are shown in the schematic for  
design flexibility.  
Power supply filter recommendations are a general guideline to be  
used for reducing external noise from coupling into the devices. The  
filter performance is designed for a wide range of noise frequencies.  
This low-pass filter starts to attenuate noise at approximately 10kHz.  
If a specific frequency noise component is known, such as switching  
power supplies frequencies, it is recommended that component  
values be adjusted and if required, additional filtering be added.  
Additionally, good general design practices for power plane voltage  
stability suggests adding bulk capacitance in the local area of all  
devices.  
The ePAD provides a low thermal impedance connection between  
the internal device and the PCB. It also provides an electrical  
connection to the die and must be connected to ground.  
©2016 Integrated Device Technology, Inc.  
22  
Revison C, November 2, 2016  
8V41N012 Datasheet  
3.3V  
FB2  
2
1
Place each 0.1uF bypass cap directly adjacent  
to its corresponding VDD or VDDA pin.  
C11  
10uF  
BLM18BB221SN1  
C10  
0.1uF  
VDD  
C14  
0.1uF  
C21  
0.1uF  
C15  
0.1uF  
3.3V  
VDD  
R5  
5
FB1  
VDDA  
2
1
C9  
10uF  
BLM18BB221SN1  
C12  
0.1uF  
C13  
0.1uF  
C17  
10uF  
C18  
0.1uF  
U1  
FSEL_A0  
FSEL_A1  
13  
14  
24  
FSEL_A0  
FSEL_A1  
VDDO_QA  
VDDO_QB  
VDDO_QC  
VDDO_QD  
VDDO_QE  
VDDO_QF  
VDDO_QG  
VDDO_QREF  
31  
38  
46  
54  
19  
69  
2
C16  
0.1uF  
FSEL_B0  
FSEL_B1  
17  
18  
FSEL_B0  
FSEL_B1  
C3  
0.1uF  
FSEL_C0  
FSEL_C1  
61  
62  
C4  
0.1uF  
FSEL_C0  
FSEL_C1  
C5  
0.1uF  
FSEL_D0  
FSEL_D1  
65  
66  
FSEL_D0  
FSEL_D1  
C6  
0.1uF  
FSEL_E0  
FSEL_E1  
6
7
C7  
0.1uF  
FSEL_E0  
FSEL_E1  
C8  
0.1uF  
REF_SEL  
PLL_SEL  
nMR  
8
12  
68  
C20  
0.1uF  
REF_SEL  
PLL_SEL  
nMR  
C19  
0.1uF  
Place each 0.1uF bypass cap directly  
adjacent to the corresponding VDDO pin.  
OE_A  
OE_B  
OE_C  
OE_D  
OE_E  
OE_G  
OE_REF  
30  
37  
44  
52  
60  
72  
1
OE_A  
OE_B  
OE_C  
OE_D  
OE_E  
OE_G  
OE_REF  
25  
26  
QA0  
nQA0  
QA0  
nQA0  
27  
28  
QA1  
nQA1  
QA1  
nQA1  
0" to 18"  
FOX 603-25-173 crystal  
R7  
33  
33  
Zo = 50  
+
-
XTAL_IN  
32  
33  
QB0  
nQB0  
1
QB0  
nQB0  
C1  
2pF  
X1  
R6  
10  
11  
34  
35  
QB1  
nQB1  
Zo = 50  
2
4
25 MHz  
(12pF)  
XTAL_IN  
QB1  
nQB1  
Optional  
39  
40  
QC0  
nQC0  
HCSL_Receiver  
QC0  
nQC0  
3
XTAL_OUT  
R12  
50  
R9  
50  
XTAL_OUT  
C2  
2pF  
41  
42  
QC1  
nQC1  
PCI Express  
Point-to-Point  
Connection  
QC1  
nQC1  
47  
48  
QD0  
nQD0  
HCSL Termination  
QD0  
nQD0  
Zo = 50 Ohm  
Zo = 50 Ohm  
CLK  
15  
16  
49  
50  
QD1  
nQD1  
CLK  
QD1  
nQD1  
55  
56  
QE0  
nQE0  
QE0  
nQE0  
nCLK  
nCLK  
1" to 14"  
0.5" to 3.5"  
R10  
R13  
33  
33  
57  
58  
QE1  
nQE1  
Zo = 50  
Zo = 50  
QE1  
nQE1  
+
R1  
50  
R2  
50  
+3.3V PECL Driver  
20  
70  
3
QF  
QF  
QG  
Zo = 50  
Zo = 50  
-
QG  
53  
R3  
50  
IREF  
QREF0  
QREF1  
R11  
50  
R8  
50  
HCSL_Receiver  
QREF0  
QREF1  
R4  
475  
4
PCI Express Add-In Card  
R14  
Zo = 50  
Logic Control Input Examples  
33  
Set Logic  
Input to '1'  
Set Logic  
Input to '0'  
VDD  
VDD  
CMOS Source Termination  
LVCMOS Receiver  
RU1  
1k  
RU2  
Not Install  
R15  
33  
Zo = 50  
To Logic  
Input  
pins  
To Logic  
Input  
pins  
RD1  
Not Install  
RD2  
1k  
LVCMOS Receiver  
Figure 6. 8V41N012 Schematic Example  
©2016 Integrated Device Technology, Inc.  
23  
Revison C, November 2, 2016  
8V41N012 Datasheet  
Power Considerations  
This section provides information on power dissipation and junction temperature for the 8V41N012. Equations and example calculations are  
also provided.  
1. Power Dissipation.  
The total power dissipation for the 8V41N012 is the sum of the core power plus the analog power plus the power dissipated due to loading.  
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.  
Power (coreM) AX = VDD_MAX * (IDD + IDDA)= 3.465V * (235mA + 45mA) = 970.2mW  
Power (HCSLM) AX = (3.465V – 17mA * 50) 17mA = 44.5mW per output  
Total Power (HCSLM) AX = 44.5mW * 10 = 445mW  
LVCMOS Driver Power Dissipation  
Output Impedance ROUT Power Dissipation due to Loading 50to VDDO_Qx / 2  
Output Current IOUT = VDD_MAX / [2 * (50+ ROUT)] = 3.465V / [2 * (50+ 15)] = 26.65mA  
Power Dissipation on the ROUT per LVCMOS output  
Power (LVCMOS) = ROUT * (IOUT)2 = 15* (26.65mA)2 = 10.65mW per output  
Total Power Dissipation on the R  
OUT  
Total Power (ROUT) = 10.65mW * 4 = 42.6mW  
Total Power Dissipation  
Total Power  
= Power (core) + Total Power (HCSL) + Total Power (ROUT  
= 970.2mW + 445mW + 42.6mW  
= 1457.8mW  
)
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 26.6°C/W per Table 9 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 1.458W * 26.6°C/W = 123.8°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 9. Thermal Resistance for 72 Lead VFQFN, Forced Convection  
JA  
JA vs. Air Flow  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
26.6°C/W  
20°C/W  
17.9°C/W  
©2016 Integrated Device Technology, Inc.  
24  
Revison C, November 2, 2016  
8V41N012 Datasheet  
3. Calculations and Equations.  
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.  
HCSL output driver circuit and termination are shown in Figure 7.  
VDDO  
IOUT = 17mA  
VOUT  
RREF  
=
475  
± 1%  
RL  
50Ω  
IC  
Figure 7. HCSL Driver Circuit and Termination  
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,  
use the following equations which assume a 50load to ground.  
The highest power dissipation occurs when VDD  
_
.
MAX  
Power = (VDD_MAX – VOUT) * IOUT  
since VOUT = IOUT * RL  
Power = (VDD_MAX – IOUT * RL) * IOUT  
= (3.465V – 17mA * 50) * 17mA  
Total Power Dissipation per output pair = 44.5mW  
©2016 Integrated Device Technology, Inc.  
25  
Revison C, November 2, 2016  
8V41N012 Datasheet  
Reliability Information  
Table 10. vs. Air Flow Table for a 72 Lead VFQFN  
JA  
JA vs. Air Flow  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
26.6°C/W  
20°C/W  
17.9°C/W  
Transistor Count  
The transistor count for 8V41N012 is: 175,936  
©2016 Integrated Device Technology, Inc.  
26  
Revison C, November 2, 2016  
8V41N012 Datasheet  
Package Outline and Package Dimensions  
Package Outline - 72 Lead VFQFN  
©2016 Integrated Device Technology, Inc.  
27  
Revison C, November 2, 2016  
8V41N012 Datasheet  
Package Outline and Package Dimensions  
Package Outline - 72 Lead VFQFN  
©2016 Integrated Device Technology, Inc.  
28  
Revison C, November 2, 2016  
8V41N012 Datasheet  
Package Outline and Package Dimensions  
Package Outline - 72 Lead VFQFN  
©2016 Integrated Device Technology, Inc.  
29  
Revison C, November 2, 2016  
8V41N012 Datasheet  
Package Outline and Package Dimensions  
Package Outline - 72 Lead VFQFN  
©2016 Integrated Device Technology, Inc.  
30  
Revison C, November 2, 2016  
8V41N012 Datasheet  
Ordering Information  
Table 11. Ordering Information  
Part/Order Number  
Marking  
Package  
Shipping Packaging  
Tray  
Temperature  
-40C to 85C  
-40C to 85C  
8V41N012NLGI  
8V41N012NLGI8  
8V41N012NLGI  
8V41N012NLGI  
72 Lead VFQFN, Lead-Free  
72 Lead VFQFN, Lead-Free  
Tape & Reel  
Revision History Sheet  
Rev  
Table  
Page  
Description of Change  
Updated schematic with IDT crystal recommendation.  
Date  
23  
B
Deleted prefix/suffix from part number throughout the datasheet.  
Updated header/footer.  
7/22/15  
23  
Schematic - replaced IDT crystal recommendation with FOX crystal.  
Updated header/footer.  
C
11/2/16  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
www.IDT.com/go/support  
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance spec-  
ifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information  
contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied  
warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of  
IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-  
sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property  
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.  
©2016 Integrated Device Technology, Inc  
31  
Revison C, November 2, 2016  
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