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8V41N010NLGI8

型号:

8V41N010NLGI8

品牌:

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数:

26 页

PDF大小:

533 K

Clock Generator for Cavium Processors  
8V41N010  
DATA SHEET  
General Description  
Features  
The 8V41N010 is a PLL-based clock generator specifically designed  
for Cavium Networks Octeon II processors. This high performance  
device is optimized to generate the processor core reference clock,  
the PCI-Express, sRIO, XAUI, SerDes reference clocks and the  
clocks for both the Gigabit Ethernet MAC and PHY. The output fre-  
quencies are generated from a 25MHz external input source or an  
external 25MHz parallel resonant crystal. The industrial temperature  
range of the 8V41N010 supports telecommunication, networking,  
and storage requirements.  
Eight selectable 100MHz and 156.25MHz clocks for PCI Express,  
sRIO and GbE, HCSL interface levels  
One single-ended QF LVCMOS/LVTTL clock output at 50MHz  
Selectable external crystal or differential (single-ended)  
input source  
Crystal oscillator interface designed for 25MHz, parallel  
resonant crystal  
Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,  
LVHSTL, HCSL input levels  
Internal resistor bias on nCLK pin allows the user to drive CLK  
input with external single-ended (LVCMOS/ LVTTL) input levels  
Full 3.3V supply mode  
-40°C to 85°C ambient operating temperature  
Lead-free (RoHS 6) packaging  
Pin Assignment  
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
QE0  
nQE0  
QE1  
GND  
nc  
nc  
nQE1  
GND  
OE_E  
nc  
nQB0  
QB0  
VDDO_QB  
OE_A  
GND  
nQA1  
QA1  
FSEL_C1  
GND  
VDDA  
8V41N010  
nQA0  
QA0  
nc  
FSEL_D1  
VDD  
VDDO_QA  
GND  
VDD  
nMR  
VDDO  
nc  
GND  
QF  
GND  
nc  
VDDO_QF  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18  
NOTE: Exposed pad must always be connected to GND.  
NOTE: Pin 1 is located at bottom left corner as shown.  
72-pin, 10mm x 10mm VFQFN Package  
8V41N010 REVISION 1 06/30/15  
1
©2015 Integrated Device Technology, Inc.  
8V41N010 DATA SHEET  
Block Diagram  
Pulldown  
nMR  
Pullup  
OE_A  
QA0  
nQA0  
QA1  
0 = 100MHz  
1 = 156.25MHz  
nQA1  
Pullup  
Pullup  
OE_B  
OE_C  
Pulldown  
QB0  
FSEL_A1  
0 = 100MHz  
1 = 156.25MHz  
Pulldown  
nQB0  
FSEL_B1  
Clock  
Output  
Control  
Logic  
Pulldown  
FSEL_C1  
Pulldown  
FSEL_D1  
QC0  
Pulldown  
nQC0  
QC1  
0 = 100MHz  
1 = 156.25MHz  
FSEL_E1  
nQC1  
Pullup  
Pullup  
OE_D  
OE_E  
QD0  
Pullup  
0 = 100MHz  
1 = 156.25MHz  
PLL_SEL  
nQD0  
Pullup  
REF_SEL  
XTAL_IN  
QE0  
OSC  
nQE0  
QE1  
0 = 100MHz  
1 = 156.25MHz  
1
0
XTAL_OUT  
FemtoClock NG  
VCO  
1
0
nQE1  
Pulldown  
PU/PD  
CLK  
50MHz  
QF  
nCLK  
I_REF  
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
2
REVISION 1 06/30/15  
8V41N010 DATA SHEET  
Pin Descriptions and Characteristics  
Table 1. Pin Descriptions  
Number  
Name  
nc  
Type  
Description  
1
2
3
4
5
6
Unused  
Power  
No internal connection.  
VDDO  
nc  
Output supply.  
Unused  
Unused  
Power  
No internal connection.  
nc  
No internal connection.  
Power supply ground.  
No internal connection.  
GND  
nc  
Unused  
Selects the QEx, nQEx output frequency. LVCMOS/LVTTL interface levels.  
0 = 100MHz (default)  
1 = 156.25MHz  
7
8
FSEL_E1  
REF_SEL  
Input  
Pulldown  
Pullup  
Input source control pin. LVCMOS/LVTTL interface levels.  
0 = CLK, nCLK  
1 = XTAL (default)  
Input  
9
VDD  
Power  
Core supply.  
Crystal  
Input  
10  
XTAL_IN  
Parallel resonant crystal input.  
Crystal  
Output  
11  
XTAL_OUT  
Parallel resonant crystal output.  
PLL bypass control pin. LVCMOS/LVTTL interface levels.  
0 = Bypass mode  
1 = PLL mode (default)  
12  
13  
14  
PLL_SEL  
nc  
Input  
Unused  
Input  
Pullup  
No internal connection.  
Selects the QAx, nQAx output frequency. LVCMOS/LVTTL interface levels.  
0 = 100MHz (default)  
1 = 156.25MHz  
FSEL_A1  
Pulldown  
Pulldown  
15  
CLK  
Input  
Non-inverting differential clock input.  
Pullup/  
Pulldown  
16  
17  
nCLK  
nc  
Input  
Inverting differential clock input. Internal resistor bias to VDD/2.  
No internal connection.  
Unused  
Selects the QBx, nQBx output frequency. LVCMOS/LVTTL interface levels.  
0 = 100MHz (default)  
1 = 156.25MHz  
18  
FSEL_B1  
Input  
Pulldown  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
VDDO_QF  
QF  
Power  
Output  
Power  
Power  
Power  
Power  
Output  
Output  
Output  
Output  
Power  
QF output supply (LVCMOS/LVTTL).  
Single-ended output. 3.3V LVCMOS/LVTTL interface levels.  
Power supply ground.  
GND  
VDD  
Core supply.  
GND  
Power supply ground.  
VDDO_QA  
QA0  
Bank A (HCSL) output supply.  
Bank A differential output pair. HCSL interface levels.  
Bank A differential output pair. HCSL interface levels.  
Bank A differential output pair. HCSL interface levels.  
Bank A differential output pair. HCSL interface levels.  
Power supply ground.  
nQA0  
QA1  
nQA1  
GND  
Active HIGH output enable for Bank A outputs. LVCMOS/LVTTL interface levels.  
0 = Bank A outputs disabled/high impedance  
1 = Bank A outputs enabled (default)  
30  
OE_A  
Input  
Pullup  
REVISION 1 06/30/15  
3
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
8V41N010 DATA SHEET  
Table 1. Pin Descriptions, Continued  
Number  
31  
Name  
VDDO_QB  
QB0  
Type  
Description  
Power  
Output  
Output  
Unused  
Unused  
Power  
Bank B (HCSL) output supply.  
Bank B differential output pair. HCSL interface levels.  
Bank B differential output pair. HCSL interface levels.  
No internal connection.  
32  
33  
nQB0  
nc  
34  
35  
nc  
No internal connection.  
36  
GND  
Power supply ground.  
Active HIGH output enable for Bank B outputs. LVCMOS/LVTTL interface levels.  
0 = Bank B outputs disabled/high impedance  
37  
OE_B  
Input  
Pullup  
38  
39  
40  
41  
42  
43  
VDDO_QC  
QC0  
Power  
Output  
Output  
Output  
Output  
Power  
Bank C (HCSL) output supply.  
Bank C differential output pair. HCSL interface levels.  
Bank C differential output pair. HCSL interface levels.  
Bank C differential output pair. HCSL interface levels.  
nQC0  
QC1  
nQC1  
GND  
Bank C differential output pair. HCSL interface levels.  
Power supply ground.  
Active HIGH output enable for Bank C outputs. LVCMOS/LVTTL interface levels.  
0 = Bank C outputs disabled/high impedance  
1 = Bank C outputs enabled (default)  
44  
OE_C  
Input  
Pullup  
45  
46  
47  
48  
VDD  
VDDO_QD  
QD0  
Power  
Power  
Output  
Output  
Core supply.  
Bank D (HCSL) output supply.  
Bank D differential output pair. HCSL interface levels.  
Bank D differential output pair. HCSL interface levels.  
No internal connection.  
nQD0  
49  
50  
51  
nc  
nc  
Unused  
Unused  
Power  
No internal connection.  
Power supply ground.  
GND  
Active HIGH output enable for Bank D outputs. LVCMOS/LVTTL interface levels.  
0 = Bank D outputs disabled/high impedance  
52  
53  
OE_D  
IREF  
Input  
Input  
Pullup  
External fixed precision resistor (475) from this pin to ground provides a  
reference current used for differential current-mode.  
54  
55  
VDDO_QE  
QE0  
Power  
Output  
Bank E (HCSL) output supply.  
Bank E differential output pair. HCSL interface levels.  
56  
57  
58  
59  
nQE0  
QE1  
Output  
Output  
Output  
Power  
Bank E differential output pair. HCSL interface levels.  
Bank E differential output pair. HCSL interface levels.  
nQE1  
GND  
Bank E differential output pair. HCSL interface levels.  
Power supply ground.  
Active HIGH output enable for Bank E outputs. LVCMOS/LVTTL interface levels.  
0 = Bank E outputs disabled/high impedance  
1 = Bank E outputs enabled (default)  
60  
OE_E  
Input  
Pullup  
61  
62  
nc  
Unused  
Input  
No internal connection.  
Selects the QCx, nQCx output frequency. LVCMOS/LVTTL interface levels.  
0 = 100MHz (default)  
1 = 156.25MHz  
FSEL_C1  
Pulldown  
63  
64  
GND  
VDDA  
Power  
Power  
Power supply ground.  
Analog supply.  
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
4
REVISION 1 06/30/15  
8V41N010 DATA SHEET  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
65  
nc  
Unused  
Input  
No internal connection.  
Selects the QDx, nQDx output frequency. LVCMOS/LVTTL interface levels.  
66  
67  
FSEL_D1  
VDD  
Pulldown  
Pulldown  
0 = 100MHz (default)  
1 = 156.25MHz  
Core supply.  
Power  
Active LOW Master Reset. LVCMOS/LVTTL interface levels.  
0 = Reset. The internal dividers are reset causing the true outputs Qx to go low and  
the inverted outputs nQx to go high. (default)  
68  
nMR  
Input  
1 = Active. The internal dividers and the outputs are active.  
Output supply.  
69  
70  
VDDO  
nc  
Power  
Unused  
Power  
No internal connection.  
Power supply ground.  
No internal connection.  
71  
GND  
nc  
72  
Unused  
Power  
ePAD  
GND_EP  
Exposed pad of package. Connect to GND.  
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
2.5  
6
Maximum  
Units  
pF  
CLK, nCLK  
Control Pins  
Input  
Capacitance  
CIN  
pF  
RPULLUP  
Input Pullup Resistor  
50  
k  
RPULLDOWN  
Input Pulldown Resistor  
50  
k  
Output  
QF  
ROUT  
VDDO_QF = 3.465V  
15  
Impedance  
Function Tables  
Table 3A. FSEL_X Control Input Function Table  
Table 3C. REF_SEL Control Input Function Table  
Input  
Input  
FSEL_X1  
0 (default)  
1
Output Frequency  
Q[Ax:Ex], nQ[Ax:Ex]  
100MHz  
REF_SEL  
0
Clock Source  
CLK, nCLK  
156.25MHz  
1 (default)  
XTAL_IN, XTAL_OUT  
NOTE: FSEL_X denotes FSEL_A, _B, _C, _D, _E.  
NOTE: Any two outputs operated at the same frequency will be  
synchronous.  
Table 3B. PLL_SEL Control Input Function Table  
Input  
Table 3D. OE_[A:E] Control Input Function Table  
Input  
OE_[A:E]  
0
Outputs  
Q[Ax:Ex], nQ[Ax:Ex]  
High-Impedance  
Enabled  
PLL_SEL  
0
Operation  
PLL Bypass  
PLL Mode  
1 (default)  
1 (default)  
REVISION 1 06/30/15  
5
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
8V41N010 DATA SHEET  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress  
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC  
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VDD  
3.6V  
Inputs, VI  
XTAL_IN  
Other Inputs  
0V to 2V  
-0.5V to VDD + 0.5V  
Outputs, VO  
-0.5V to VDDO_QX 1+ 0.5V  
Maximum Junction Temperature, TJMAX  
Storage Temperature, TSTG  
125°C  
-65C to 150C  
NOTE 1. VDDO_QX denotes: VDDO_QA, VDDO_QB, VDDO_QC, VDDO_QD, VDDO_QE, VDDO_QF.  
DC Electrical Characteristics  
Table 4A. Power Supply DC Characteristics, V = 3.3V ꢀ5, V  
DD  
= V  
= 3.3V ꢀ5, T = -40°C to 8ꢀ°C  
DDO_Q[A:E]  
DDO_QF A  
Symbol  
VDD  
Parameter  
Test Conditions  
Minimum  
Typical  
3.3  
Maximum  
3.465  
3.465  
3.465  
235  
Units  
V
Core Supply Voltage  
Analog Supply Voltage  
Output Supply Voltage  
Power Supply Current  
Analog Supply Current  
Output Supply Current  
3.135  
3.135  
3.135  
VDDA  
VDDO_QX  
IDD  
3.3  
V
1
3.3  
V
193  
36  
mA  
mA  
mA  
IDDA  
47  
2
IDDO_QX  
No Load  
24  
30  
NOTE 1. VDDO_QX denotes VDDO_Q[A:E], VDDO_QF.  
NOTE 2. IDDO_QX denotes IDDO_Q[A:E] + IDDO_QF.  
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
6
REVISION 1 06/30/15  
8V41N010 DATA SHEET  
Table 4B. LVCMOS/LVTTL DC Characteristics, V = V  
DD  
= V  
= 3.3V ꢀ5, T = -40°C to 8ꢀ°C  
DDO_QF A  
DDO_Q[A:E]  
Symbol Parameter  
Test Conditions  
Minimum  
2.2  
Typical  
Maximum Units  
VIH  
VIL  
Input High Voltage  
Input Low Voltage  
VDD + 0.3  
0.8  
V
V
-0.3  
nMR, FSEL_A1,  
FSEL_B1, FSEL_C1,  
FSEL_D1, FSEL_E1  
VDD = VIN = 3.465V  
150  
10  
µA  
uA  
µA  
uA  
Input  
High  
Current  
IIH  
REF_SEL, PLL_SEL, OE_A,  
OE_B, OE_C, OE_D, OE_E  
VDD = VIN = 3.465V  
nMR, FSEL_A1,  
FSEL_B1, FSEL_C1,  
FSEL_D1, FSEL_E1  
VDD = 3.465V, VIN = 0V  
VDD = 3.465V, VIN = 0V  
-10  
Input  
Low  
Current  
IIL  
REF_SEL, PLL_SEL, OE_A,  
OE_B, OE_C, OE_D, OE_E  
-150  
2.6  
VOH  
VOL  
Output High Voltage  
Output Low Voltage  
VDDO_QF = 3.465V  
VDDO_QF = 3.465V  
V
V
0.6  
Table 4C. Differential DC Characteristics, V = 3.3V ꢀ5, T = -40°C to 8ꢀ°C  
DD A  
Symbol Parameter  
IIH Input High Current  
Test Conditions  
Minimum  
Typical  
Maximum Units  
CLK, nCLK  
VDD = VIN = 3.465V  
DD = 3.465V, VIN = 0V  
DD = 3.465V, VIN = 0V  
150  
µA  
µA  
µA  
V
CLK  
V
V
-5  
IIL  
Input Low Current  
nCLK  
-150  
0.15  
0.5  
VPP  
Peak-to-Peak Input Voltage1  
1.3  
VCMR  
Common Mode Input Voltage12  
VDD – 0.85  
V
NOTE 1. VIL should not be less than -0.3V.  
NOTE 2. Common mode voltage is defined as VIH.  
Table ꢀ. Table ꢀ. Crystal Characteristics  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum Units  
Mode of Oscillation  
Fundamental  
25  
Frequency  
MHz  
Equivalent Series Resistance (ESR)  
Load Capacitance (CL)  
Shunt Capacitance  
50  
7
12  
pF  
pF  
Table 6. Input Frequency Characteristics, V = V  
DD  
= V  
= 3.3V ꢀ5, T = -40°C to 8ꢀ°C  
DDO_QF A  
DDO_Q[A:E]  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
CLK, nCLK  
25  
MHz  
Input  
FIN  
XTAL_IN,  
XTAL_OUT  
Frequency  
25  
MHz  
REVISION 1 06/30/15  
7
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
8V41N010 DATA SHEET  
AC Electrical Characteristics  
1 2  
Table 7A. PCI Express Jitter Specifications, V = V  
DD  
= 3.3V 5%, T = -40°C to 85°C  
A
DDO_Q[A:E]  
PCIe Industry  
Maximum Specification Units  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
ƒ= 100MHz, 25MHz Crystal Input  
Evaluation Band: 0Hz - Nyquist  
(clock frequency/2)  
tj  
Phase Jitter  
Peak-to-Peak3 4  
6.97  
11.18  
86  
ps  
(PCIe Gen 1)  
ƒ= 100MHz, 25MHz Crystal Input  
High Band: 1.5MHz - Nyquist  
(clock frequency/2)  
tREFCLK_HF_RMS  
(PCIe Gen 2)  
Phase Jitter  
RMS3 5  
0.70  
0.03  
0.16  
1.84  
0.07  
0.49  
3.10  
3.0  
ps  
ps  
ps  
tREFCLK_LF_RMS  
(PCIe Gen 2)  
Phase Jitter  
RMS3 4  
ƒ= 100MHz, 25MHz Crystal Input  
Low Band: 10kHz - 1.5MHz  
ƒ= 100MHz, 25MHz Crystal Input  
Evaluation Band: 0Hz - Nyquist  
(clock frequency/2)  
tREFCLK_RMS  
(PCIe Gen 3)  
Phase Jitter  
RMS3 6  
0.8  
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the  
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after  
thermal equilibrium has been reached under these conditions. For additional information, refer to the PCI Express Application Note  
section in the datasheet.  
NOTE 2. Design Target Specifications.  
NOTE 3. Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express  
Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods.  
NOTE 4. This parameter is guaranteed by characterization. Not tested in production.  
NOTE 5. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and  
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_H-  
F_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).  
NOTE 6. RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Ex-  
press Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.  
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
8
REVISION 1 06/30/15  
8V41N010 DATA SHEET  
1 2 3  
Table 7B. HCSL AC Characteristics, V = V  
DD  
= V  
= 3.3V 5%, T = -40°C to 85°C  
DDO_QF A  
DDO_Q[A:E]  
Symbol Parameter  
Test Conditions  
FSEL_X1 = 0  
FSEL_X1 = 1  
Minimum  
Typical  
Maximum  
Units  
MHz  
MHz  
100  
Q[A:E],  
nQ[A:E]  
fOUT  
Output Frequency  
156.25  
Q[A:E],  
nQ[A:E]  
VRB  
Ring-Back Voltage Margin4 5  
Time before VRB is allowed1 2  
Absolute Max Output Voltage6 7  
Absolute Min Output Voltage3 8  
Absolute Crossing Voltage3 9 10  
-100  
500  
100  
mV  
ps  
Q[A:E],  
nQ[A:E]  
tSTABLE  
VMAX  
Q[A:E],  
nQ[A:E]  
1150  
mV  
mV  
mV  
mV  
V/ns  
V/ns  
%
Q[A:E],  
nQ[A:E]  
VMIN  
-300  
175  
Q[A:E],  
nQ[A:E]  
VCROSS  
VCROSS  
tSLEW+  
tSLEW-  
odc  
550  
140  
4.0  
Total Variation of VCROSS over  
All Edges3 6 11  
Q[A:E],  
nQ[A:E]  
Q[A:E],  
nQ[A:E]  
Rising Edge Rate1 12  
Falling Edge Rate1 9  
Output Duty Cycle  
0.6  
0.6  
48  
Q[A:E],  
nQ[A:E]  
4.0  
Q[A:E],  
nQ[A:E]  
50  
52  
100MHz, Integration Range:  
(12kHz to 20MHz)  
0.32  
0.30  
0.45  
0.45  
ps  
Q[A:E],  
nQ[A:E]  
tjit(Ø)  
RMS Phase Jitter, (Random)13  
156.25MHz, Integration Range:  
(12kHz to 20MHz)  
ps  
tjit(RMS) Jitter, RMS  
Jitter, (peak-to-peak)15  
Q[A:E], nQ[A:E] = 100MHz or  
156.25MHz, 25MHz XTAL,  
PLL Mode14  
2.6  
19  
ps  
ps  
tjit(p-p)  
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device  
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal  
equilibrium has been reached under these conditions.  
NOTE 2. All parameters measured at fOUT and in PLL mode unless noted otherwise.  
NOTE 3. Refer to applications section for information on peak-to-peak jitter calculations.  
NOTE 4. Measurement taken from differential waveform.  
NOTE 5.  
t
is the time the differential clock must maintain a minimum 150mV differential voltage after rising/falling edges before it is  
STABLE  
allowed to drop back into the VRB 100mV range. See Parameter Measurement Information Section.  
NOTE 6. Measurement taken from single-ended waveform.  
NOTE 7. Defined as the maximum instantaneous voltage including overshoot.  
NOTE 8. Defined as the minimum instantaneous voltage including undershoot.  
NOTE 9. Measured at the crossing point where the instantaneous voltage value of the rising edge of Q[Ax:Ex] equals the falling edge of  
nQ[Ax:Ex]  
NOTE 10. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all cross-  
ing points for this measurement.  
NOTE 11. Defined as the total variation of all crossing voltages of rising Q[Ax:Ex] and falling nQ[Ax:Ex]. This is the maximum allowed vari-  
ance in Vcross for any particular system.  
NOTE 12. Measured from -150mV to +150mV on the differential waveform (derived from Q[Ax:Ex] minus nQ[Ax:Ex]). The signal must be  
monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero  
crossing  
NOTE 13. Measurements taken with 25MHz XTAL as input source and spur off  
NOTE 14. All differential outputs are running at the same frequency.  
NOTE 15. tjit(p-p) is a calculated value given RMS multiplier = 7.438. For detailed description of algorithm, please refer to Section, “Ap-  
plications Information”, Peak-to-Peak Jitter Calculations.  
REVISION 1 06/30/15  
9
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
8V41N010 DATA SHEET  
1
Table 7C. LVCMOS AC Characteristics, V = V  
DD  
= V  
= 3.3V 5%, T = -40°C to 85°C  
DDO_QF A  
DDO_Q[A:E]  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum Units  
fOUT  
tr/tf  
Output Frequency  
Output Rise/Fall Time  
Output Duty Cycle  
QF  
QF  
QF  
50  
MHz  
20% to 80%  
180  
47  
700  
53  
ps  
%
odc  
50  
50MHz, Integration Range:  
(12kHz to 20MHz)  
tjit(Ø)  
tjit(RJ)  
tjit(DJ)  
RMS Phase Jitter, (Random)2  
Random Jitter, RMS3  
QF  
QF  
QF  
0.35  
0.45  
ps  
ps  
ps  
Q[A:E], nQ[A:E] = 156.25MHz,  
25MHz XTAL, PLL Mode  
2
3
Q[A:E], nQ[A:E] = 156.25MHz,  
25MHz XTAL, PLL Mode  
Deterministic Jitter, Pk-to-Pk4  
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the  
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after  
thermal equilibrium has been reached under these conditions.  
NOTE 2. Measurements taken with 25MHz XTAL as input source and spur off.  
NOTE 3. Measurements taken with Wavecrest SIA-3000 Analyzer.  
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
10  
REVISION 1 06/30/15  
8V41N010 DATA SHEET  
Typical Phase Noise at 1ꢀ6.2ꢀMHz  
Offset Frequency (Hz)  
REVISION 1 06/30/15  
11  
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
8V41N010 DATA SHEET  
Applications Information  
Peak-to-Peak Jitter Calculations  
A standard deviation of a statistical population or data set is the  
square root of its variance. A standard deviation is used to calculate  
the probability of an anomaly or to predict a failure. Many times, the  
term "root mean square" (RMS) is used synonymously for standard  
deviation. This is accurate when referring to the square root of the  
mean squared deviation of a signal from a given baseline and when  
the data set contains a Gaussian distribution with no deterministic  
components. A low standard deviation indicates that the data set is  
close to the mean with little variation. A large standard deviation  
indicates that the data set is spread out and has a large variation from  
the mean.  
Table 8. BER Table  
RMS Multiplier Data,  
RMS Multiplier Clock,  
“DTD = 1”  
BER  
“DTD = 0.ꢀ”  
10-3  
6.180  
6.582  
7.782  
10-4  
7.438  
10-5  
8.530  
8.834  
10-6  
9.507  
9.784  
10-7  
10.399  
11.224  
11.996  
12.723  
13.412  
14.069  
14.698  
15.301  
15.883  
10.654  
11.462  
12.218  
12.934  
13.614  
14.260  
14.882  
15.478  
16.028  
10-8  
A standard deviation is required when calculating peak-to-peak jitter.  
Since true peak-to-peak jitter is random and unbounded, it is  
important to always associate a bit error ratio (BER) when specifying  
a peak-to-peak jitter limit. Without it, the specification does not have  
a boundary and will continue get larger with sample size. Given that  
a BER is application specific, many frequency timing devices specify  
jitter as an RMS. This allows the peak-to-peak jitter to be calculated  
for the specific application and BER requirement. Because a  
standard deviation is the variation from the mean of the data set, it is  
important to always calculate the peak-to-peak jitter using the typical  
RMS value.  
10-9  
10-10  
10-11  
10-12  
10-13  
10-14  
10-15  
Table 8 shows the BER with its appropriate RMS Multiplier. There are  
two columns for the RMS multiplier, one should be used if your signal  
is data and the other should be used if the signal is a repetitive clock  
signal. The difference between the two is the data transition density  
(DTD). The DTD is the number of rising or falling transitions divided  
by the total number of bits. For a clock signal, they are equal, hence  
the DTD is 1. For Data, on average, most common encoding  
standards have a 0.5 DTD.  
Once the BER is chosen, there are two circumstances to consider. Is  
the data set purely Gaussian or does it contains any deterministic  
component? If it is Gaussian, then the peak to peak jitter can be  
calculated by simply multiplying the RMS multiplier with the typical  
RMS specification. For example, if a 10-12 BER is required for a clock  
signal, multiply 14.260 times the typical jitter specification.  
Jitter (peak-to-peak) = RMS Multiplier * RMS (typical)  
If the datasheet contains deterministic components, then the random  
jitter (RJ) and deterministic jitter (DJ) must be separated and  
analyzed separately. RJ, also known as Gaussian jitter, is not  
bounded and the peak-to-peak will continue to get larger as the  
sample size increases. Alternatively, peak-to-peak value of DJ is  
bounded and can easily be observed and predicted. Therefore, the  
peak to peak jitter for the random component must be added to the  
deterministic component. This is called total jitter (TJ).  
Total Jitter (peak-to-peak) = [RMS Multiplier * Random Jitter  
(RJ)] + Deterministic Jitter (DJ)  
The total jitter equation is not specific to one type of jitter  
classification. It can be used to calculate BER on various types of  
RMS jitter. It is important that the user understands their jitter  
requirement to ensure they are calculating the correct BER for their  
jitter requirement.  
NOTE: Use RJ and DJ values from AC Characteristics Tables 7B and  
7C to calculate TJ.  
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
12  
REVISION 1 06/30/15  
8V41N010 DATA SHEET  
Wiring the Differential Input to Accept Single-Ended Levels  
Figure 1 shows how a differential input can be wired to accept single  
ended levels. The reference voltage V1= VDD/2 is generated by the  
bias resistors R1 and R2. The bypass capacitor (C1) is used to help  
filter noise on the DC bias. This bias circuit should be located as close  
to the input pin as possible. The ratio of R1 and R2 might need to be  
adjusted to position the V1in the center of the input voltage swing. For  
example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2  
value should be adjusted to set V1 at 1.25V. The values below are for  
when both the single ended swing and VDD are at the same voltage.  
This configuration requires that the sum of the output impedance of  
the driver (Ro) and the series resistance (Rs) equals the transmission  
line impedance. In addition, matched termination at the input will  
attenuate the signal in half. This can be done in one of two ways.  
First, R3 and R4 in parallel should equal the transmission line  
impedance. For most 50applications, R3 and R4 can be 100. The  
values of the resistors can be increased to reduce the loading for  
slower and weaker LVCMOS driver. When using single-ended  
signaling, the noise rejection benefits of differential signaling are  
reduced. Even though the differential input can handle full rail  
LVCMOS signaling, it is recommended that the amplitude be  
reduced. The datasheet specifies a lower differential amplitude,  
however this only applies to differential signals. For single-ended  
applications, the swing can be larger, however VIL cannot be less  
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some  
of the recommended components might not be used, the pads  
should be placed in the layout. They can be utilized for debugging  
purposes. The datasheet specifications are characterized and  
guaranteed by using a differential signal.  
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels  
REVISION 1 06/30/15  
13  
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
8V41N010 DATA SHEET  
3.3V Differential Clock Input Interface  
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other  
differential signals. Both VSWING and VOH must meet the VPP and  
VCMR input requirements. Figures 2A to 2E show interface examples  
for the CLK/nCLK input driven by the most common driver types. The  
input interfaces suggested here are examples only. Please consult  
with the vendor of the driver component to confirm the driver  
termination requirements. For example, in Figure 2A, the input  
termination applies for IDT open emitter LVHSTL drivers. If you are  
using an LVHSTL driver from another vendor, use their termination  
recommendation.  
3.3V  
1.8V  
Zo = 50  
CLK  
Zo = 50Ω  
nCLK  
Differential  
LVHSTL  
IDT  
LVHSTL Driver  
Input  
R1  
50Ω  
R2  
50Ω  
Figure 2A. CLK/nCLK Input Driven by an  
IDT Open Emitter LVHSTL Driver  
Figure 2B. CLK/nCLK Input Driven by a  
3.3V LVPECL Driver  
3.3V  
3.3V  
*R3  
*R4  
CLK  
nCLK  
Differential  
Input  
HCSL  
Figure 2C. CLK/nCLK Input Driven by a  
3.3V LVPECL Driver  
Figure 2D. CLK/nCLK Input Driven by a  
3.3V HCSL Driver  
Figure 2E. CLK/nCLK Input Driven by a 3.3V LVDS Driver  
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
14  
REVISION 1 06/30/15  
8V41N010 DATA SHEET  
Overdriving the XTAL Interface  
The XTAL_IN input can be overdriven by an LVCMOS driver or by one  
side of a differential driver through an AC coupling capacitor. The  
XTAL_OUT pin can be left floating. The amplitude of the input signal  
should be between 500mV and 1.8V and the slew rate should not be  
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be  
reduced from full swing to at least half the swing in order to prevent  
signal interference with the power rail and to reduce internal noise.  
Figure 3A shows an example of the interface diagram for a high  
speed 3.3V LVCMOS driver. This configuration requires that the sum  
of the output impedance of the driver (Ro) and the series resistance  
(Rs) equals the transmission line impedance. In addition, matched  
termination at the crystal input will attenuate the signal in half. This  
can be done in one of two ways. First, R1 and R2 in parallel should  
equal the transmission line impedance. For most 50applications,  
R1 and R2 can be 100. This can also be accomplished by removing  
R1 and changing R2 to 50. The values of the resistors can be  
increased to reduce the loading for a slower and weaker LVCMOS  
driver. Figure 3B shows an example of the interface diagram for an  
LVPECL driver. This is a standard LVPECL termination with one side  
of the driver feeding the XTAL_IN input. It is recommended that all  
components in the schematics be placed in the layout. Though some  
components might not be used, they can be utilized for debugging  
purposes. The datasheet specifications are characterized and  
guaranteed by using a quartz crystal as the input.  
VCC  
XTAL_OUT  
R1  
100  
C1  
Rs  
Zo = 50 ohms  
Ro  
XTAL_IN  
.1uf  
R2  
100  
Zo = Ro + Rs  
LVCMOS Driver  
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface  
XTAL_OUT  
C2  
Zo = 50 ohms  
XTAL_I N  
.1uf  
Zo = 50 ohms  
R1  
50  
R2  
50  
LVPECL Driver  
R3  
50  
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface  
REVISION 1 06/30/15  
15  
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
8V41N010 DATA SHEET  
Recommended Termination  
Figure 4A is the recommended source termination for applications  
where the driver and receiver will be on a separate PCBs. This  
termination is the standard for PCI Express™and HCSL output types.  
All traces should be 50impedance single-ended or 100Ω  
differential.  
Rs  
0.5" Max  
L1  
0-0.2"  
L2  
1-14"  
L4  
0.5 - 3.5"  
L5  
22 to 33 +/-5%  
L1  
L2  
L4  
L5  
PCI Express  
Connector  
PCI Express  
Driver  
PCI Express  
Add-in Card  
0-0.2" L3  
L3  
49.9 +/- 5%  
Rt  
Figure 4A. Recommended Source Termination (where the driver and receiver will be on separate PCBs)  
Figure 4B is the recommended termination for applications where a  
point-to-point connection can be used. A point-to-point connection  
contains both the driver and the receiver on the same PCB. With a  
matched termination at the receiver, transmission-line reflections will  
be minimized. In addition, a series resistor (Rs) at the driver offers  
flexibility and can help dampen unwanted reflections. The optional  
resistor can range from 0to 33. All traces should be 50Ω  
impedance single-ended or 100differential.  
Rs  
0.5" Max  
L1  
0-18"  
L2  
0-0.2"  
L3  
0 to 33  
0 to 33  
L1  
L2  
L3  
PCI Express  
Driver  
49.9 +/- 5%  
Rt  
Figure 4B. Recommended Termination (where a point-to-point connection can be used)  
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
16  
REVISION 1 06/30/15  
8V41N010 DATA SHEET  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 5. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally/  
Electrically Enhance Leadframe Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
SOLDER  
SOLDER  
PIN  
PIN  
EXPOSED HEAT SLUG  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure ꢀ. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
Recommendations for Unused Input and Output Pins  
Inputs:  
Outputs:  
LVCMOS Control Pins  
LVCMOS Outputs  
All control pins have internal pullups or pulldowns; additional  
resistance is not required but can be added for additional protection.  
A 1kresistor can be used.  
All unused LVCMOS outputs can be left floating. There should be no  
trace attached.  
Differential Outputs  
Crystal Inputs  
All unused differential outputs can be left floating. We recommend  
that there is no trace attached. Both sides of the differential output  
pair should either be left floating or terminated.  
For applications not requiring the use of the crystal oscillator input,  
both XTAL_IN and XTAL_OUT can be left floating. Though not  
required, but for additional protection, a 1kresistor can be tied from  
XTAL_IN to ground.  
CLK/nCLK Inputs  
For applications not requiring the use of the differential input, both  
CLK and nCLK can be left floating. Though not required, but for  
additional protection, a 1kresistor can be tied from CLK to ground.  
REVISION 1 06/30/15  
17  
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
8V41N010 DATA SHEET  
PCI Express Application Note  
PCI Express jitter analysis methodology models the system  
response to reference clock jitter. The block diagram below shows the  
most frequently used Common Clock Architecture in which a copy of  
the reference clock is provided to both ends of the PCI Express Link.  
In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs  
are modeled as well as the phase interpolator in the receiver. These  
transfer functions are called H1, H2, and H3 respectively. The overall  
system transfer function at the receiver is:  
Hts= H3s  H1sH2s  
The jitter spectrum seen by the receiver is the result of applying this  
system transfer function to the clock spectrum X(s) and is:  
Ys= Xs  H3s  H1sH2s  
In order to generate time domain jitter numbers, an inverse Fourier  
Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].  
PCIe Gen 2A Magnitude of Transfer Function  
PCI Express Common Clock Architecture  
For PCI Express Gen 1, one transfer function is defined and the  
evaluation is performed over the entire spectrum: DC to Nyquist (e.g  
for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is  
reported in peak-peak.  
PCIe Gen 2B Magnitude of Transfer Function  
For PCI Express Gen 3, one transfer function is defined and the  
evaluation is performed over the entire spectrum. The transfer  
function parameters are different from Gen 1 and the jitter result is  
reported in RMS.  
PCIe Gen 1 Magnitude of Transfer Function  
For PCI Express Gen 2, two transfer functions are defined with 2  
evaluation ranges and the final jitter number is reported in RMS. The  
two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz  
(Low Band) and 1.5MHz – Nyquist (High Band). The plots show the  
individual transfer functions as well as the overall transfer function Ht.  
PCIe Gen 3 Magnitude of Transfer Function  
For a more thorough overview of PCI Express jitter analysis  
methodology, please refer to IDT Application Note PCI Express  
Reference Clock Requirements.  
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
18  
REVISION 1 06/30/15  
8V41N010 DATA SHEET  
Schematic Example  
Figure 8 (next page) shows an example of 8V41N010 application  
schematic. In this example, the device is operated at VDD = VDDA  
VDDO_Qx = 3.3V. The schematic example focuses on functional  
connections and is not configuration specific. Refer to the pin  
As with any high speed analog circuitry, the power supply pins are  
vulnerable to random noise. To achieve optimum jitter performance,  
power supply isolation is required. The 8V41N010 provides separate  
power supplies to isolate any high switching noise from coupling into  
the internal PLL.  
=
description and functional tables in the datasheet to ensure that the  
logic control inputs are properly set.  
In order to achieve the best possible filtering, it is recommended that  
the placement of the filter components be on the device side of the  
PCB as close to the power pins as possible. If space is limited, the  
0.1µF capacitor in each power pin filter should be placed on the  
device side. The other components can be on the opposite side of the  
PCB.  
A 12pF parallel resonant 25MHz crystal is used. For this device, the  
crystal load capacitors are required for proper operation. The load  
capacitance, C1 = C2 = 2pF, are recommended for frequency  
accuracy. Depending on the variation of the parasitic stray capacity  
of the printed circuit board traces between the crystal and the  
XTAL_IN and XTAL_OUT pins, the values of C1 and C2 might require  
a slight adjustment to optimize the frequency accuracy. Crystals with  
other load capacitance specifications can be used, but this will  
require adjusting C1 and C2. When designing the circuit board,  
return the capacitors to ground though a single point contact close to  
the package. Two Fox crystal options are shown in the schematic for  
design flexibility.  
Power supply filter recommendations are a general guideline to be  
used for reducing external noise from coupling into the devices. The  
filter performance is designed for a wide range of noise frequencies.  
This low-pass filter starts to attenuate noise at approximately 10kHz.  
If a specific frequency noise component is known, such as switching  
power supplies frequencies, it is recommended that component  
values be adjusted and if required, additional filtering be added.  
Additionally, good general design practices for power plane voltage  
stability suggests adding bulk capacitance in the local area of all  
devices.  
The ePAD provides a low thermal impedance connection between  
the internal device and the PCB. It also provides an electrical  
connection to the die and must be connected to ground.  
REVISION 1 06/30/15  
19  
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
8V41N010 DATA SHEET  
3.3V  
FB2  
2
1
Place each 0.1uF bypass cap directly adjacent  
to its corresponding VDD or VDDA pin.  
C11  
10uF  
BLM18BB221SN1  
C10  
0.1uF  
VDD  
C14  
0.1uF  
C21  
0.1uF  
C15  
0.1uF  
3.3V  
VDD  
R5  
5
FB1  
VDDA  
2
1
C9  
10uF  
BLM18BB221SN1  
C12  
0.1uF  
C13  
0.1uF  
C17  
10uF  
C18  
0.1uF  
U1  
24  
VDDO_QA  
VDDO_QB  
VDDO_QC  
VDDO_QD  
VDDO_QE  
VDDO_QF  
VDDO  
FSEL_A1  
14  
18  
62  
66  
7
FSEL_A1  
31  
38  
46  
54  
19  
69  
2
C16  
0.1uF  
FSEL_B1  
FSEL_C1  
FSEL_D1  
FSEL_E1  
C3  
0.1uF  
FSEL_B1  
FSEL_C1  
FSEL_D1  
FSEL_E1  
XTAL_IN  
C4  
0.1uF  
C5  
0.1uF  
4
C6  
0.1uF  
X2  
XTAL_OUT  
1
3
C7  
0.1uF  
C8  
0.1uF  
VDDO  
2
REF_SEL  
PLL_SEL  
8
12  
68  
C1  
2pF  
C2  
2pF  
C20  
0.1uF  
REF_SEL  
PLL_SEL  
nMR  
C19  
0.1uF  
nMR  
25MHz(12pf)  
Place each 0.1uF bypass cap directly  
adjacent to the corresponding VDDO pin.  
OE_A  
OE_B  
OE_C  
OE_D  
OE_E  
30  
37  
44  
52  
60  
OE_A  
OE_B  
OE_C  
OE_D  
OE_E  
25  
26  
QA0  
nQA0  
QA0  
nQA0  
Fox FX325BS  
alternate crystal  
27  
28  
QA1  
nQA1  
QA1  
nQA1  
0" to 18"  
R7  
33  
33  
Zo = 50  
+
-
32  
33  
QB0  
nQB0  
QB0  
nQB0  
R6  
Fox P/N: 277LF-25-99  
XTAL_IN  
10  
11  
Zo = 50  
XTAL_IN  
Optional  
X1  
39  
40  
QC0  
nQC0  
HCSL_Receiver  
QC0  
nQC0  
XTAL_OUT  
R12  
50  
R9  
50  
XTAL_OUT  
C1  
2pF  
41  
42  
QC1  
nQC1  
25MHz (12pF)  
Zo = 50 Ohm  
Zo = 50 Ohm  
C2  
2pF  
PCI Express  
Point-to-Point  
Connection  
QC1  
nQC1  
15  
47  
48  
QD0  
nQD0  
HCSL Termination  
CLK  
QD0  
nQD0  
CLK  
16  
53  
nCLK  
IREF  
nCLK  
55  
56  
QE0  
nQE0  
QE0  
nQE0  
1" to 14"  
0.5" to 3.5"  
R10  
R13  
33  
33  
57  
58  
QE1  
nQE1  
R1  
50  
R2  
50  
Zo = 50  
Zo = 50  
QE1  
nQE1  
+
1
3
4
+3.3V PECL Driver  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
20  
QF  
QF  
6
Zo = 50  
Zo = 50  
-
13  
17  
34  
35  
49  
50  
61  
65  
70  
72  
R3  
50  
R4  
475  
R11  
50  
R8  
50  
HCSL_Receiver  
PCI Express Add-In Card  
Logic Control Input Examples  
R14  
Set Logic  
Input to '1'  
Set Logic  
Input to '0'  
VDD  
VDD  
Zo = 50  
33  
RU1  
1K  
RU2  
Not Install  
CMOS Source Termination  
IDT8V41N010  
LVCMOS Receiver  
To Logic  
Input  
pins  
To Logic  
Input  
pins  
RD1  
Not Install  
RD2  
1K  
Figure 8. 8V41N010 Schematic Example  
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
20  
REVISION 1 06/30/15  
8V41N010 DATA SHEET  
Power Considerations  
This section provides information on power dissipation and junction temperature for the 8V41N010. Equations and example calculations are  
also provided.  
1. Power Dissipation.  
The total power dissipation for the 8V41N010 is the sum of the core power plus the analog power plus the power dissipated due to loading.  
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.  
Power (core)MAX = VDD_MAX * (IDD + IDDA)= 3.465V * (235mA + 47mA) = 977.13mW  
Power (HCSL)MAX = (3.465V – 17mA * 50) 17mA = 44.ꢀmW per output  
Total Power (HCSL)MAX = 44.5mW * 8 = 3ꢀ6mW  
Power (pre-driver)MAX = 3.465V * 30mA = 103.95mW  
LVCMOS Driver Power Dissipation  
Output Impedance ROUT Power Dissipation due to Loading 50to VDDO_Qx / 2  
Output Current IOUT = VDD_MAX / [2 * (50+ ROUT)] = 3.465V / [2 * (50+ 15)] = 26.6ꢀmA  
Power Dissipation on the ROUT per LVCMOS output  
Power (LVCMOS) = ROUT * (IOUT)2 = 15* (26.65mA)2 = 10.6ꢀmW per output  
Total Power Dissipation on the ROUT  
Total Power (ROUT) = 10.65mW * 1 = 10.6ꢀmW  
Total Power Dissipation  
Total Power  
= Power (core) + Total Power (HCSL) + Power (pre-driver) + Total Power (ROUT  
= 977.13mW + 356mW + 103.95mW + 10.65mW  
= 1447.73mW  
)
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 26.6°C/W per Table 9 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 1.448W * 26.6°C/W = 123.5°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 9. Thermal Resistance for 72 Lead VFQFN, Forced Convection  
JA  
JA vs. Air Flow  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
26.6°C/W  
20°C/W  
17.9°C/W  
REVISION 1 06/30/15  
21  
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
8V41N010 DATA SHEET  
3. Calculations and Equations.  
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.  
HCSL output driver circuit and termination are shown in Figure 7.  
VDDO  
IOUT = 17mA  
VOUT  
RREF  
4751%  
=
RL  
50Ω  
IC  
Figure 7. HCSL Driver Circuit and Termination  
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,  
use the following equations which assume a 50load to ground.  
The highest power dissipation occurs when VDD  
_
.
MAX  
Power = (VDD_MAX – VOUT) * IOUT  
since VOUT = IOUT * RL  
Power = (VDD_MAX – IOUT * RL) * IOUT  
= (3.465V – 17mA * 50) * 17mA  
Total Power Dissipation per output pair = 44.ꢀmW  
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
22  
REVISION 1 06/30/15  
8V41N010 DATA SHEET  
Reliability Information  
Table 10. vs. Air Flow Table for a 72 Lead VFQFN  
JA  
JA vs. Air Flow  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
26.6°C/W  
20°C/W  
17.9°C/W  
Transistor Count  
The transistor count for 8V41N010 is: 175,936  
REVISION 1 06/30/15  
23  
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
8V41N010 DATA SHEET  
72-Lead VFQFN (NL) Package Outline and Package Dimensions  
NOTE 1. The drawing and dimension data originates from IDT  
Package Outline Drawing PSC-4208, Rev 04.  
1
Table 8. Package Dimensions for 72-Lead Package  
All dimensions and tolerances conform to ANSI  
Y14.5-1944.  
All dimensions are in millimeters.  
DIMENSIONS  
SYMBOL  
MIN  
NOM  
MAX  
Index Area (Pin1 Identifier)  
D
10.00 BSC  
E
D2  
E2  
K
10.00 BSC  
5.90  
5.90  
-
5.80  
5.80  
0.20  
0.30  
0.80  
0.00  
6.00  
6.00  
-
L
0.40  
0.90  
0.02  
0.50  
1.00  
0.05  
1.00  
A
A1  
A2  
A3  
b
0.00  
0.65  
0.2 REF  
0.18  
0.25  
0.30  
e
0.50 BSC  
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
24  
REVISION 1 06/30/15  
8V41N010 DATA SHEET  
Ordering Information  
Table 11. Ordering Information  
Part/Order Number  
Marking  
Package  
Shipping Packaging  
Tray  
Temperature  
-40C to 85C  
-40C to 85C  
8V41N010NLGI  
8V41N010NLGI8  
IDT8V41N010NLGI  
IDT8V41N010NLGI  
72 Lead VFQFN, Lead-Free  
72 Lead VFQFN, Lead-Free  
Tape & Reel  
CLOCK GENERATOR FOR CAVIUM PROCESSORS  
25  
REVISION 1 06/30/15  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
Sales  
Tech Support  
email: clocks@idt.com  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in  
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined  
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether  
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This  
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or  
other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as  
those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any  
circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected  
names, logos and designs, are the property of IDT or their respective third party owners.  
Copyright ©2015 Integrated Device Technology, Inc. All rights reserved.  
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