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8V44S269NLGI

型号：

8V44S269NLGI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

28 页

PDF大小：

598 K

下载PDF手册
FemtoClock® Crystal-to-LVDS, LVCMOS  
10-Output Clock Synthesizer  
8V44S269  
Datasheet  
General Description  
Features  
The 8V44S269 is a ten LVDS/LVTTL output clock synthesizer  
designed for instrumentation and wireless applications. The device  
generates four copies of a 125MHz, two copies of a 100MHz  
differential LVDS clock and one 50MHz (LVCMOS) signal with  
excellent phase jitter performance. The PLL is optimized for a  
reference frequency of 25MHz. Both a crystal interface and a  
single-ended input are supported for the reference frequency. Three  
LVCMOS outputs duplicate the reference frequency and are  
provided for clock tree cascade purpose. Each of the four LVCMOS  
outputs can be supplied with either 3.3V, 2.5V or 1.8V, forming the  
respective LVCMOS output levels of 3.3V, 2.5V or 1.8V. The device  
uses IDT’s third generation FemtoClock® technology for an optimum  
of high clock frequency and low phase noise performance, combined  
with a low power consumption. The device supports a 3.3V voltage  
supply and is packaged in a small, lead-free (RoHS 6) 48-lead  
VFQFN package.  
• Third generation FemtoClock® technology  
• 125MHz, 100MHz and 50MHz output clocks synthesized from a  
25MHz reference clock or fundamental mode crystal  
• Six differential LVDS clock outputs  
• QA[0:3] outputs (125MHz) are LVDS compatible  
• QB[0:1] outputs (100MHz) are LVDS compatible  
• Four single-ended LVCMOS-compatible reference clock outputs  
• QC output (50MHz) is LVCMOS 3.3V, 2.5V or 1.8V compatible  
• QREF[0:2] (25MHz) are LVCMOS 3.3V, 2.5V or 1.8V compatible  
• Crystal interface designed for 25MHz XTAL  
• RMS phase jitter @ 125MHz, using a 25MHz crystal  
(12kHz - 20MHz): 0.57 (typical)  
• RMS phase jitter @ 100MHz, using a 25MHz crystal  
(12kHz - 20MHz): 0.58 (typical)  
• LVCMOS interface levels for the control input  
• I/O supply voltages for LVDS:  
Core/Output  
3.3V/2.5V  
• I/O supply voltages for LVCMOS:  
Core/Output  
3.3V/3.3V  
3.3V/2.5V  
3.3V/1.8V  
• Lead-free (RoHS 6) 48-lead VFQFN packaging  
• -55°C to 105°C ambient operating temperature  
©2016 Integrated Device Technology, Inc.  
1
May 9, 2016  
8V44S269 Datasheet  
Block Diagram  
Pull-down (4)  
nOEA[0:3]  
4
QA0  
Pull-down  
nQA0  
BYPASS  
QA1  
nQA1  
XTAL_IN  
OSC  
125 MHz  
f
= 25 MHz  
REF  
1
0
÷20  
÷25  
1
0
FemtoClock®  
VCO  
2500MHz  
QA2  
nQA2  
PFD  
&
LPF  
XTAL_OUT  
25 MHz  
Pull-down  
REF_CLK  
QA3  
nQA3  
Pull-down  
÷2  
REF_SEL  
100  
QB0  
100 MHz  
nQB0  
QB1  
nQB1  
Pull-down (2)  
nOEB[0:1]  
2
50 MHz  
25 MHz  
QC  
Pull-down  
nOEC  
QREF0  
QREF1  
QREF2  
Pull-down (2)  
nOER[0:1]  
2
©2016 Integrated Device Technology, Inc.  
2
May 9, 2016  
8V44S269 Datasheet  
Pin Assignment  
48 47 46 45 44 43 42 41 40 39 38 37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1
GND  
QA0  
nQA0  
QA1  
nQA1  
VDDOA  
QA2  
nQA2  
QA3  
nQA3  
GND  
nc  
REF_CLK  
GND  
2
3
VDDOC  
4
QC  
5
VDDOR2  
QREF2  
GND  
6
8V44S269  
7
8
VDDOR1  
QREF1  
VDDOR0  
QREF0  
GND  
9
10  
11  
12  
13 14 15 16 17 18 19 20 21 22 23 24  
Pin Description and Characteristic Tables  
1
Table 1. Pin Descriptions  
Number  
Name  
REF_CLK  
GND  
Type  
Description  
1
2
3
4
5
Input  
Power  
Power  
Output  
Power  
Pull-down  
Single-ended reference clock input. LVCMOS/LVTTL interface levels.  
Ground power supply (0V).  
VDDOC  
QC  
Output supply for the QC output.  
Single-ended clock output. LVCMOS/LVTTL interface levels.  
Output supply for the QREF2 output.  
VDDOR2  
Single-ended clock output (copy 2 of the reference clock).   
LVCMOS/LVTTL interface levels.  
6
QREF2  
Output  
7
8
GND  
Power  
Power  
Ground power supply (0V).  
VDDOR1  
Output supply for the QREF1 output.  
Single-ended clock output (copy 1 of the reference clock).   
LVCMOS/LVTTL interface levels.  
9
QREF1  
VDDOR0  
QREF0  
GND  
Output  
Power  
Output  
Power  
10  
11  
12  
Output supply for the QREF0 output.  
Single-ended clock output (copy 0 of the reference clock).  
LVCMOS/LVTTL interface levels.  
Ground power supply (0V).  
©2016 Integrated Device Technology, Inc.  
3
May 9, 2016  
8V44S269 Datasheet  
1
Table 1. Pin Descriptions  
Number  
Name  
nOEC  
VDD  
Type  
Description  
Output enable inputs for the individual QC output. See Table 3E on page 6  
for function. LVCMOS/LVTTL interface levels.  
13  
Input  
Power  
Input  
Pull-down  
14  
Core supply.  
Output enable inputs for the QREF2 output. See Table 3F on page 6 for  
function. LVCMOS/LVTTL interface levels.  
15  
nOER1  
Pull-down  
Pull-down  
Pull-down  
Pull-down  
Output enable inputs for the QREF[0:1] outputs. See Table 3F on page 6  
for function. LVCMOS/LVTTL interface levels.  
16  
17  
18  
nOER0  
nOEB1  
nOEB0  
Input  
Input  
Input  
Output enable inputs for the QB1 output. See Table 3D on page 6 for  
function. LVCMOS/LVTTL interface levels.  
Output enable inputs for the QB0 output. See Table 3D on page 6 function.  
LVCMOS/LVTTL interface levels.  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
VDDOB  
nQB1  
QB1  
Power  
Output  
Output  
Output  
Output  
Unused  
Unused  
Power  
Output  
Output  
Output  
Output  
Power  
Output  
Output  
Output  
Output  
Power  
Power  
Power  
Power  
Output supply for the Bank B outputs.  
Inverted differential clock output pair. LVDS interface levels.  
Non-inverted Differential clock output pair. LVDS interface levels.  
Inverted differential clock output pair. LVDS interface levels.  
Non-inverted Differential clock output pair. LVDS interface levels.  
No internal connection.  
nQB0  
QB0  
nc  
nc  
No internal connection.  
GND  
nQA3  
QA3  
Ground power supply (0V).  
Inverted differential clock output pair. LVDS interface levels.  
Non-inverted Differential clock output pair. LVDS interface levels.  
Inverted differential clock output pair. LVDS interface levels.  
Non-inverted Differential clock output pair. LVDS interface levels.  
Output supply for the Bank A outputs.  
nQA2  
QA2  
VDDOA  
nQA1  
QA1  
Inverted differential clock output pair. LVDS interface levels.  
Non-inverted Differential clock output pair. LVDS interface levels.  
Inverted differential clock output pair. LVDS interface levels.  
Non-inverted Differential clock output pair. LVDS interface levels.  
Ground power supply (0V).  
nQA0  
QA0  
GND  
GND  
VDD  
Ground power supply (0V).  
Core supply.  
VDDA  
Analog power supply.  
Output enable inputs for the QA3 output. See Table 3C on page 6 for  
function. LVCMOS/LVTTL interface levels.  
40  
41  
nOEA3  
nOEA2  
Input  
Input  
Pull-down  
Pull-down  
Output enable inputs for the QA2 output. See Table 3C on page 6 for  
function. LVCMOS/LVTTL interface levels.  
©2016 Integrated Device Technology, Inc.  
4
May 9, 2016  
8V44S269 Datasheet  
1
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
Output enable inputs for the QA1 output. See Table 3C on page 6 for  
function. LVCMOS/LVTTL interface levels.  
42  
nOEA1  
Input  
Input  
Input  
Pull-down  
Pull-down  
Pull-down  
Pull-down  
Output enable inputs for the QA0 output. See Table 3C on page 6 for  
function. LVCMOS/LVTTL interface levels.  
43  
44  
45  
nOEA0  
REF_SEL  
BYPASS  
Reference select. See Table 3A on page 6 for function.  
LVCMOS/LVTTL interface levels.  
PLL bypass mode select. See Table 3B on page 6 for function.  
LVCMOS/LVTTL interface levels.  
Input  
46  
47  
48  
—
GND  
Power  
Ground power supply (0V).  
Crystal  
Output  
XTAL_OUT  
XTAL_IN  
Crystal Output. Crystal oscillator interface.  
Crystal Input. Crystal oscillator interface.  
Crystal Input  
Ground  
Ground power supply (0V). The exposed pad is a ground return path of the  
circuit and requires a connection to 0V.  
Exposed Pad  
NOTE 1. Pull-down refers to internal input resistors. See Table 2, “Pin Characteristics”.  
1
Table 2. Pin Characteristics  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
REF_CLK,  
nOEA[0:3],  
nOEB[0:1],   
nOEC,  
nOER[0:1],  
REF_SEL,  
BYPASS  
Input  
Capacitance  
CIN  
2
pF  
RPULLDOWN  
Input Pull-down Resistor  
51  
18  
23  
35  
k  
QREF[0:2], QC, VDDOn = 3.3V  
QREF[0:2], QC, VDDOn = 2.5V  
QREF[0:2], QC, VDDOn = 1.8V  
ROUT  
Output Impedance  
NOTE 1. VDDOn denotes VDDOC, VDDOR0, VDDOR1, VDDOR2.  
©2016 Integrated Device Technology, Inc.  
5
May 9, 2016  
8V44S269 Datasheet  
Function Tables  
1
1
Table 3A. PLL Reference Clock Select Function Table  
Input  
Table 3D. Outputs QB[0:1] Enable Function Table  
Input  
REF_SEL  
Operation  
nOEBn  
0 (default)  
Operation  
0 (default)  
The REF_CLK input is selected as reference clock  
Outputs QBn, nQBn are enabled  
The crystal interface is selected as reference  
clock  
Outputs QBn, nQBn are disabled in  
high-impedance state  
1
1
NOTE 1. REF_SEL is an asynchronous control input.  
NOTE 1. n = 0 to 1.   
Each QBn, nQBn output is individually controlled by the  
corresponding nOEBn input. nOEBn are synchronous  
control inputs.  
1
1
Table 3B. PLL Bypass Select Function Table  
Input  
Table 3E. Outputs QC Enable Function Table  
Input  
BYPASS  
Operation  
nOEC  
0 (default)  
1
Operation  
0 (default)  
PLL mode  
Output QC is enabled  
PLL bypass mode. The reference clock is routed  
to the output dividers.   
AC specifications do not apply in PLL bypass  
Output QC is disabled in high-impedance state  
1
NOTE 1. nOEC is an asynchronous control input.  
mode.  
NOTE 1. BYPASS is an asynchronous control input.  
1
Table 3C. Outputs QA[0:3] Enable Function Table  
Input  
nOEAn  
Operation  
0 (default)  
Output QAn, nQAn is enabled  
Output QAn, nQAn is disabled in high-impedance  
state  
1
NOTE 1. n = 0 to 3.   
Each QAn, nQAn output is individually controlled by the  
corresponding nOEAn input. nOEAn are asynchronous  
control inputs.  
1
Table 3F. Outputs QREF[0:2] Enable Function Table  
Input  
nOER1  
Operation  
nOER0  
Outputs QREF[0:1]  
Enabled  
Output QREF2  
0 (default)  
0 (default)  
Enabled  
0
1
1
1
0
1
Enabled  
Disabled in high-impedance state  
Enabled  
Disabled in high-impedance state  
Disabled in high-impedance state  
Disabled in high-impedance state  
NOTE 1. nOER[0:1] are asynchronous control inputs.  
©2016 Integrated Device Technology, Inc.  
6
May 9, 2016  
8V44S269 Datasheet  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress  
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or  
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.  
Table 4. Absolute Maximum Ratings  
Item  
Rating  
Supply Voltage, VDD  
4.6V  
Inputs, VI  
XTAL_IN  
Other Inputs  
0V to 2V  
-0.5V to VDD + 0.5V  
Outputs, VO (LVCMOS)  
-0.5V to VDDOn1 + 0.5V  
Outputs, IO (LVDS)  
Continuous Current  
Surge Current  
10mA  
15mA  
Storage Temperature, TSTG  
-65C to 150C  
125C  
Junction Temperature, TJ  
NOTE 1. VDDOn denotes VDDOC, VDDOR0, VDDOR1, VDDOR2.  
DC Electrical Characteristics  
Table 5A. Power Supply DC Characteristics,  
1
V
= 3.3V 5ꢀ, V  
= V  
= 2.5V 5ꢀ, V  
V
= (2.5V to 3.3V) 5ꢀ, 1.8V 0.2V, T = -55°C to 105°C  
DDOC A  
DD  
DDOA  
DDOB  
DDORn,  
Symbol  
VDD  
Parameter  
Test Conditions  
Minimum  
3.135  
Typical  
3.3  
Maximum  
3.465  
Units  
Core Supply Voltage  
V
V
VDDA  
Analog Supply Voltage  
VDD – 0.16  
3.3  
VDD  
LVDS  
Output Supply Voltage  
VDDOA, B  
2.375  
2.5  
2.625  
V
1.6  
1.8  
2.5  
3.3  
80  
2.0  
2.625  
3.465  
91  
V
V
V
DDOR0, VDDOR1,LVCMOS   
2.375  
3.135  
VDDOR2, VDDOC  
Output Supply Voltage2  
V
IDD  
Core Supply Current  
mA  
mA  
IDDA  
Analog Supply Current  
12  
16  
LVDS  
Output Supply Current  
IDDOA + DDOB  
I
122  
2
137  
3
mA  
mA  
LVCMOS  
Output Power Current  
QC, QREF[0:2];  
No External Load  
3
IDDORn + IDDOC  
NOTE 1. VDDOn denotes VDDOR0, VDDOR1, VDDOR2.  
NOTE 2. Each VDDORn (n = 0 to 2) and VDDOC voltage may be left open, connected to GND or supplied by 1.8V, 2.5V or 3.3V.  
NOTE 3. IDDORn denotes IDDOR0, DDOR1, DDOR2.  
I
I
©2016 Integrated Device Technology, Inc.  
7
May 9, 2016  
8V44S269 Datasheet  
Table 5B. LVCMOS/LVTTL DC Characteristics,   
1
V
= 3.3V 5ꢀ, V  
, VDD = (2.5V to 3.3V) 5ꢀ, 1.8V 0.2V, T = -55°C to 105°C  
DD  
DDORn OC A  
Symbol  
VIH  
Parameter  
Test Conditions  
VDD = 3.3V  
Minimum  
2.2  
Typical  
Maximum  
VDD + 0.3  
0.8  
Units  
Input High Voltage2  
V
V
VIL  
Input Low Voltage  
VDD = 3.3V  
-0.3  
REF_SEL,  
nOEA[0:3],  
nOEB[0:1],  
Input  
IIH  
VDD = VIN = 3.465V  
150  
µA  
µA  
High Current nOER[0:1],  
BYPASS,  
REF_CLK  
REF_SEL,  
nOEA[0:3],  
nOEB[0:1],  
nOER[0:1],  
BYPASS,  
REF_CLK  
Input  
Low Current  
IIL  
VDD = 3.465V, VIN = 0V  
-5  
VDDOn4 = 3.465V  
VDDOn4 = 2.625V  
VDDOn4 = 2V  
2.6  
1.8  
1.5  
V
V
V
V
V
V
Output  
High  
QC,  
QREF[0:2]  
VOH  
Voltage3  
VDDOn4 = 3.465V  
VDDOn4 = 2.625V  
VDDOn4 = 2V  
0.5  
0.5  
0.4  
Output  
QC,  
VOL  
Low Voltage3 QREF[0:2]  
NOTE 1. VDDORn denotes VDDOR0, VDDOR1, VDDOR2.  
NOTE 2. nOEA[0:3], nOEB[0:1], nOER[0:1], nOEC, BYPASS and REF_CLK inputs are 3.3V tolerant.  
NOTE 3. Output terminated with 50to VDD/ 2. See Section, “Parameter Measurement Information”.  
NOTE 4. VDDOn denotes VDDOC, VDDOR0, VDDOR1, VDDOR2.  
Table 5C. LVDS DC Characteristics, VDD = 3.3V 5ꢀ, VDDOA = VDDOB = 2.5V 5ꢀ, T = -55°C to 105°C  
A
Symbol  
VOD  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
mV  
mV  
V
Differential Output Voltage  
VOD Magnitude Change  
Offset Voltage  
247  
488  
VOD  
VOS  
50  
0.975  
1.375  
VOS  
VOS Magnitude Change  
50  
mV  
Table 6. Crystal Characteristics  
Parameter  
Test Conditions  
Minimum  
Typical  
Fundamental  
25  
Maximum  
Units  
Mode of Oscillation  
Frequency  
MHz  
Equivalent Series Resistance (ESR)  
Shunt Capacitance  
80  
7
pF  
Capacitive Loading (CL)  
12  
pF  
©2016 Integrated Device Technology, Inc.  
8
May 9, 2016  
8V44S269 Datasheet  
AC Electrical Characteristics  
Table 7. AC Characteristics,   
1
2, 3  
V
= 3.3V 5ꢀ, V  
= V  
= 2.5V 5ꢀ, V  
VDD = (2.5V to 3.3V) 5ꢀ, 1.8V 0.2V, T = -55°C to 105°C  
DDORn, OC A  
DD  
DDOA  
DDOB  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
fVCO  
VCO Frequency  
BYPASS = 0  
2500  
125  
100  
50  
Output Frequency, QA[0:3]  
Output Frequency, QB[0:1]  
Output Frequency, QC  
fOUT  
Output Frequency, QREF[0:2]  
Reference Frequency  
25  
fREF  
25  
fOUT = 125MHz,  
Integration Range: 12kHz – 20MHz  
QA[0:3]  
0.57  
0.58  
0.78  
0.85  
0.8  
0.8  
ps  
ps  
ps  
ps  
f
OUT = 100MHz,  
QB[0:1]  
Integration Range: 12kHz – 20MHz  
RMS Phase  
Jitter (Random)  
tjit(Ø)  
fOUT = 50MHz,  
Integration Range: 12kHz – 20MHz  
QC  
1.20  
1.32  
fOUT = 25MHz,  
Integration Range: 12kHz – 5MHz  
QREF[0:2]  
N(1k)  
1kHz Offset from Carrier  
10kHz Offset from Carrier  
100kHz Offset from Carrier  
1MHz Offset from Carrier  
-126  
-132  
-130  
-141  
-119  
-126.9  
-127.4  
-138  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
N(10k)  
N(100k)  
N(1M)  
Single-side Band Phase Noise  
100MHz Output Frequency  
10MHz Offset from Carrier and  
Noise Floor  
N(10M)  
-153  
-150  
dBc/Hz  
N(1k)  
1kHz Offset from Carrier  
10kHz Offset from Carrier  
100kHz Offset from Carrier  
1MHz Offset from Carrier  
-124  
-129  
-128  
-139  
-116  
-124.9  
-125.4  
-137  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
N(10k)  
N(100k)  
N(1M)  
Single-side Band Phase Noise  
125MHz Output Frequency  
10MHz Offset from Carrier and  
Noise Floor  
N(10M)  
-151  
-150  
dBc/Hz  
QA[0:3]  
QB[0:1]  
fOUT = 125MHz  
fOUT = 100MHz  
3.0  
3.2  
6
8.1  
7.4  
28  
ps  
ps  
ps  
ps  
ps  
ps  
fOUT = 50MHz, VDDOC = 3.3V  
Period Jitter,  
Peak-to-Peak  
tjit(per)  
QC  
f
OUT = 50MHz, VDDOC = 2.5V  
7
33  
fOUT = 50MHz, VDDOC = 1.8V  
fOUT = 25MHz  
11  
2.4  
39  
QREF[0:2]  
4.0  
©2016 Integrated Device Technology, Inc.  
9
May 9, 2016  
8V44S269 Datasheet  
Table 7. AC Characteristics, (Continued)  
1
2, 3  
V
= 3.3V 5ꢀ, V  
= V  
= 2.5V 5ꢀ, V  
VDD = (2.5V to 3.3V) 5ꢀ, 1.8V 0.2V, T = -55°C to 105°C  
DDORn, OC A  
DD  
DDOA  
DDOB  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
9
Maximum  
Units  
ps  
QA[0:3]  
QB[0:1]  
fOUT = 125MHz  
16  
20  
27  
41  
113  
33  
25  
30  
65  
f
OUT = 100MHz  
OUT = 50MHz, VDDOC = 3.3V  
fOUT = 50MHz, VDDOC = 2.5V  
11  
ps  
f
12  
ps  
Cycle-to-Cycle  
Jitter  
tjit(cc)  
QC  
13  
ps  
f
OUT = 50MHz, VDDOC = 1.8V  
fOUT = 25MHz  
44  
ps  
QREF[0:2]  
QA[0:3]  
19  
ps  
ps  
tsk(b)  
tR / tF  
Bank Skew4, 5 QB[0:1]  
ps  
QREF[0:2]  
ps  
Differential  
Outputs  
20ꢀ to 80ꢀ  
20ꢀ to 80ꢀ  
150  
375  
250  
750  
ps  
ps  
Output  
Rise/Fall Time  
Single-ended  
Outputs  
tLOCK  
PLL Lock Time  
73  
50  
50  
50  
ms  
ꢀ
QA[0:3]  
QB[0:1]  
QC  
fOUT = 125MHz  
48  
48  
48  
52  
52  
52  
Output  
Duty Cycle  
odc  
f
OUT = 100MHz  
fOUT = 50MHz  
ꢀ
ꢀ
NOTE 1. VDDORn denotes VDDOR0, VDDOR1, VDDOR2.  
NOTE 2. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device  
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal  
equilibrium has been reached under these conditions.  
NOTE 3. fREF = 25MHz.  
NOTE 4. Defined as skew within a bank of outputs at the same voltage and with equal load conditions.  
NOTE 5. This parameter is defined in accordance with JEDEC Standard 65.  
©2016 Integrated Device Technology, Inc.  
10  
May 9, 2016  
8V44S269 Datasheet  
Typical Phase Noise at 125MHz, 2.5V (QA Outputs)  
Offset Frequency (Hz)  
©2016 Integrated Device Technology, Inc.  
11  
May 9, 2016  
8V44S269 Datasheet  
Typical Phase Noise at 100MHz, 2.5V (QB Outputs)  
Offset Frequency (Hz)  
©2016 Integrated Device Technology, Inc.  
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May 9, 2016  
8V44S269 Datasheet  
Parameter Measurement Information  
1.65V 5ꢀ  
3.3V 5ꢀ  
2.5V 5ꢀ  
1.65V 5ꢀ  
SCOPE  
V
SCOPE  
DD  
V
V
V
DD,  
Qx  
V
DDA  
DDOC,  
+ +  
POWER  
SUPPLY  
Float GND  
–
V
V
DDOA,  
DDOB  
DDOR[0:2]  
V
Qx  
DDA  
nQx  
GND  
-1.65V 5ꢀ  
LVDS 3.3V Core/2.5V Output Load AC Test Circuit  
LVCMOS 3.3V Core/3.3V Output Load AC Test Circuit  
2.4V 0.065V  
0.9V 0.1V  
2.05V 5ꢀ  
1.25V 5ꢀ  
2.05V 5ꢀ  
2.4V 0.065V  
V
V
DD  
SCOPE  
DD  
SCOPE  
V
V
DDOC,  
V
V
DDOC,  
DDOR[0:2]  
DDOR[0:2]  
Qx  
Qx  
V
DDA  
V
DDA  
GND  
GND  
-0.9V 0.1V  
-1.25V 5ꢀ  
LVCMOS 3.3V Core/2.5V Output Load AC Test Circuit  
LVCMOS 3.3V Core/1.8V Output Load AC Test Circuit  
VOH  
VREF  
VOL  
t jit (pk-pk)  
Histogram  
Reference Point  
(Trigger Edge)  
Mean Period  
(First edge after trigger)  
10,000 cycles  
Period Jitter  
RMS Phase Jitter  
©2016 Integrated Device Technology, Inc.  
13  
May 9, 2016  
8V44S269 Datasheet  
Parameter Measurement Information, continued  
nQA[0:3],  
nQB[0:1]  
VDDOX  
2
VDDOX  
2
VDDOX  
2
QC,  
QREF[0:2]  
QA[0:3],  
QB[0:1]  
➤
➤
tcycle n  
tcycle n+1  
tcycle n  
tcycle n+1  
➤
➤
tjit(cc) = tcycle n – tcycle n+1  
|
|
tjit(cc) = tcycle n – tcycle n+1  
|
|
1000 Cycles  
1000 Cycles  
LVDS Cycle-to-Cycle Jitter  
LVCMOS Cycle-to-Cycle Jitter  
nQXx  
QXx  
VDDO  
QREFx  
QREFy  
2
nQXy  
VDDO  
2
QXy  
tsk(o)  
tsk(b)  
X = Bank A or Bank B  
LVDS Bank Skew  
LVCMOS Bank Skew  
nQA[0:3],  
nQB[0:1]  
80ꢀ  
tF  
80ꢀ  
tF  
80ꢀ  
tR  
80ꢀ  
VOD  
20ꢀ  
20ꢀ  
20ꢀ  
QC,  
QREF[0:2]  
20ꢀ  
QA[0:3],  
QB[0:1]  
tR  
LVDS Output Rise/Fall Time  
LVCMOS Output Rise/Fall Time  
©2016 Integrated Device Technology, Inc.  
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May 9, 2016  
8V44S269 Datasheet  
Parameter Measurement Information, continued  
nQA[0:3],  
nQB[0:1]  
VDDO  
2
QA[0:3],  
QB[0:1]  
QC,  
QREF[0:2]  
tPW  
tPERIOD  
tPW  
x 100ꢀ  
odc =  
tPERIOD  
LVDS Output Duty Cycle/Pulse Width/Period  
LVCMOS Output Duty Cycle/Pulse Width/Period  
PLL Lock Time  
Offset Voltage Setup  
Differential Offset Voltage Setup  
©2016 Integrated Device Technology, Inc.  
15  
May 9, 2016  
8V44S269 Datasheet  
Applications Information  
Recommendations for Unused Input and Output Pins  
Inputs:  
Outputs:  
LVCMOS Outputs  
REF_CLK  
All unused LVCMOS outputs can be left floating We recommend that  
there is no trace attached.  
For applications not requiring the use of the reference clock, it can be  
left floating. Though not required, but for additional protection, a 1k  
resistor can be tied from the REF_CLK to ground.  
LVDS Outputs  
Crystal Inputs  
All unused LVDS output pairs can be either left floating or terminated  
with 100across. If they are left floating there should be no trace  
attached.  
For applications not requiring the use of the crystal oscillator input,  
both XTAL_IN and XTAL_OUT can be left floating. Though not  
required, but for additional protection, a 1kresistor can be tied from  
XTAL_IN to ground.  
LVCMOS Control Pins  
All control pins have internal pull-down resistors; additional  
resistance is not required but can be added for additional protection.  
A 1kresistor can be used.  
©2016 Integrated Device Technology, Inc.  
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May 9, 2016  
8V44S269 Datasheet  
Overdriving the XTAL Interface  
The XTAL_INinputcan be overdriven by an LVCMOS driver orby one  
side of a differential driver through an AC coupling capacitor. The  
XTAL_OUT output can be left floating. The amplitude of the input  
signal should be between 500mV and 1.8V and the slew rate should  
not be less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude  
must be reduced from full swing to at least half the swing in order to  
prevent signal interference with the power rail and to reduce internal  
noise. Figure 1A shows an example of the interface diagram for a  
high speed 3.3V LVCMOS driver. This configuration requires that the  
sum of the output impedance of the driver (Ro) and the series  
resistance (Rs) equals the transmission line impedance. In addition,  
matched termination at the crystal input will attenuate the signal in  
half. This can be done in one of two ways. First, R1 and R2 in parallel  
should equal the transmission line impedance. For most 50  
applications, R1 and R2 can be 100. This can also be accomplished  
by removing R1 and changing R2 to 50. The values of the resistors  
can be increased to reduce the loading for a slower and weaker  
LVCMOS driver. Figure 1B shows an example of the interface  
diagram for an LVPECL driver. This is a standard LVPECL  
termination with one side of the driver feeding the XTAL_IN input. It  
is recommended that all components in the schematics be placed in  
the layout. Though some components might not be used, they can be  
utilized for debugging purposes. The datasheet specifications are  
characterized and guaranteed by using a quartz crystal as the input.  
VCC  
XTAL_OUT  
R1  
100  
C1  
Rs  
Zo = 50 ohms  
Ro  
XTAL_IN  
.1uf  
R2  
100  
Zo = Ro + Rs  
LVCMOS Driver  
Figure 1A. Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface  
XTAL_OUT  
C2  
Zo = 50 ohms  
XTAL_I N  
.1uf  
Zo = 50 ohms  
R1  
50  
R2  
50  
LVPECL Driver  
R3  
50  
Figure 1B. Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface  
©2016 Integrated Device Technology, Inc.  
17  
May 9, 2016  
8V44S269 Datasheet  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 2. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally/  
Electrically Enhance Leadframe Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
SOLDER  
SOLDER  
PIN  
PIN  
EXPOSED HEAT SLUG  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 2. Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
©2016 Integrated Device Technology, Inc.  
18  
May 9, 2016  
8V44S269 Datasheet  
LVDS Driver Termination  
For a general LVDS interface, the recommended value for the  
termination impedance (ZT) is between 90and 132. The actual  
value should be selected to match the differential impedance (Z0) of  
your transmission line. A typical point-to-point LVDS design uses a  
100parallel resistor at the receiver and a 100differential  
transmission-line environment. In order to avoid any  
transmission-line reflection issues, the components should be  
surface mounted and must be placed as close to the receiver as  
possible. IDT offers a full line of LVDS compliant devices with two  
types of output structures: current source and voltage source. The  
standard termination schematic as shown in Figure 3A can be used  
with either type of output structure. Figure 3B, which can also be  
used with both output types, is an optional termination with center tap  
capacitance to help filter common mode noise. The capacitor value  
should be approximately 50pF. If using a non-standard termination, it  
is recommended to contact IDT and confirm if the output structure is  
current source or voltage source type. In addition, since these  
outputs are LVDS compatible, the input receiver’s amplitude and  
common-mode input range should be verified for compatibility with  
the output.  
ZO ZT  
LVDS  
Driver  
LVDS  
ZT  
Receiver  
Figure 3A. Standard LVDS Termination  
ZT  
2
ZO ZT  
LVDS  
Driver  
LVDS  
Receiver  
C
ZT  
2
Figure 3B. Optional LVDS Termination  
©2016 Integrated Device Technology, Inc.  
19  
May 9, 2016  
8V44S269 Datasheet  
Schematic Layout  
Figure 4 (next page) shows an example 8V44S269 application  
schematic in which the device is operated at VDD = VDDOR0 = VDDOR1  
= VDDOR2 = 3.3V and VDDOA = VDDOB = 2.5V.  
In order to achieve the best possible filtering, it is recommended that  
the placement of the filter components be on the device side of the  
PCB as close to the power pins as possible. If space is limited, the 10  
ohm VCCA resistor and the 0.1uF capacitor in each power pin filter  
should be placed on the device side. The other components can be  
on the opposite side of the PCB. Pull-up and pull-down resistors to  
set configuration pins can all be placed on the PCB side opposite the  
device side to free up device side area if necessary.  
This example focuses on functional connections and is not  
configuration specific. Refer to the pin description and functional  
tables in the datasheet to ensure that the logic control inputs are  
properly set for the application.  
Two different differential terminations are depicted. QA0 is the  
standard LVDS termination. QA3 is an example demonstrating how  
the IDT LVDS outputs can be directly AC coupled to IDT CLK, nCLK  
clock receiver inputs where the internal bias resistors of the receiver  
guarantee that the AC coupled LVDS clock is within the common  
mode range of the receiver.  
Power supply filter recommendations are a general guideline to be  
used for reducing external noise from coupling into the devices. The  
filter performance is designed for a wide range of noise frequencies.  
This low-pass filter starts to attenuate noise at approximately 10kHz.  
If a specific frequency noise component is known, such as switching  
power supplies frequencies, it is recommended that component  
values be adjusted and if required, additional filtering be added.  
Additionally, good general design practices for power plane voltage  
stability suggests adding bulk capacitance in the local area of all  
devices.  
As with any high speed analog circuitry, the power supply pins are  
vulnerable to random noise. To achieve optimum jitter performance,  
power supply isolation is required. The 8V44S269 provides separate  
power supplies to isolate any high switching noise from coupling into  
the internal PLL. The Murata BLM18BB221SN1B ferrite bead shown  
in the schematic was selected for the flat frequency response  
realized with the associated filter capacitors. The rated current for this  
bead is 450mA which will accommodate the maximum current for  
each power filter.  
For additional layout recommendations and guidelines, contact  
clocks@idt.com.  
©2016 Integrated Device Technology, Inc.  
20  
May 9, 2016  
8V44S269 Datasheet  
3.3V  
2.5V  
FB1  
FB3  
1
2
VDD  
2
1
2.5V  
FB5  
1
BLM18BB221SN1  
BLM18BB221SN1  
C20  
C7  
0.1uF  
C8  
10uF  
C29  
0.1uF  
C30  
0.1uF  
U24  
14  
2
31  
19  
3
C32  
0.1uF  
C21  
10uF  
0.1uF  
VDDOA  
VDDOB  
VDDOC  
BLM18BB221SN1  
VDD  
VDD  
38  
C41  
0.1uF  
C40  
10uF  
C39  
0.1uF  
FB6  
3.3V  
1
R20  
10  
2
Place 0.1uF bypass cap  
directly adjacent to the  
corresponding VDDO pin.  
VDD  
39  
BLM18BB221SN1  
VDDA  
C42  
0.1uF  
C10  
0.1uF  
C31  
0.1uF  
C44  
0.1uF  
C43  
10uF  
3.3V  
XTAL_IN  
48  
47  
FB4  
XTAL_IN  
10  
8
2
1
VDDOR0  
VDDOR1  
VDDOR2  
XTAL_OUT  
3.3V  
BLM18BB221SN1  
XTAL_OUT  
Q2  
C38  
0.1uF  
C36  
10uF  
C35  
C34  
0.1uF  
0.1uF  
Ro  
Ro+Rz=Zo  
R19  
Zo = 50 Ohm  
5
REF_CLK  
1
44  
43  
42  
REF_CLK  
REF_SEL  
nOEA0  
Rz  
C37  
0.1uF  
Place 0.1uF bypass cap  
directly adjacent to the  
LVCMOS Driver  
corresponding VDDO pin.  
REF_SEL  
Zo = 50 Ohm  
+
35  
34  
QA0  
R2  
QA0  
100  
nOEA0  
nOEA1  
nQA0  
Zo = 50 Ohm  
nQA0  
-
33  
32  
QA1  
LVDS Receiver  
1
QA1  
nQA1  
25 MHz  
(12pF)  
nOEA1  
nQA1  
XTAL_IN  
2
4
LVDS Termination  
X2  
IDT  
30  
29  
QA2  
603-25-173  
crystal  
QA2  
3
XTAL_OUT  
C1  
15pF  
C2  
15pF  
nOEA2  
nOEA3  
nOEB0  
41  
40  
18  
nQA2  
nOEA2  
nOEA3  
nOEB0  
nQA2  
Zo = 50 Ohm  
C45  
+
28  
27  
QA3  
0.1u  
C46  
R16  
100  
QA3  
nQA3  
Zo = 50 Ohm  
nQA3  
-
0.1u  
IDT Clk/nCLK Receiver  
23  
22  
QB0  
QB0  
LVDS Termination  
nQB0  
nQB0  
Zo = 50 Ohm  
+
21  
20  
QB1  
R17  
100  
QB1  
nOEB  
nOEC  
17  
13  
nQB1  
Zo = 50 Ohm  
nOEB1  
nOEC  
nQB1  
-
LVDS Receiver  
Logic Control Input Examples  
R1  
33  
Zo = 50 Ohm  
4
QC  
QC  
QREF0  
QREF1  
QREF2  
Set Logic  
Input to '1'  
Set Logic  
Input to '0'  
VDD  
VDD  
nOER0  
nOER1  
16  
15  
LVCMOS Receiver  
LVCMOS Termination  
nOER0  
nOER1  
RU1  
1k  
RU2  
Not Install  
11  
9
QREF0  
To Logic  
Input  
pins  
To Logic  
Input  
pins  
BYPASS  
45  
2
QREF1  
QREF2  
BYPASS  
GND  
RD1  
Not Install  
RD2  
1k  
7
GND  
R18  
33  
Zo = 50 Ohm  
12  
26  
36  
37  
46  
6
GND  
GND  
LVCMOS Termination  
GND  
LVCMOS Receiver  
GND  
24  
25  
nc  
nc  
GND  
49  
ePAD  
IDT8V44S269I  
Figure 4. 8V44S269 Application Schematic  
©2016 Integrated Device Technology, Inc.  
21  
May 9, 2016  
8V44S269 Datasheet  
Power Considerations  
The 8V44S269 device was designed and characterized to operate within the ambient extended temperature range of -55°C to 105°C.  
The ambient temperature represents the temperature around the device, not the junction temperature. Extreme care must be taken to avoid  
exceeding the 125°C junction temperature, potentially damaging the device.  
Equations and example calculations are also provided below.  
1. Power Dissipation.  
The power dissipation for the 8V44S269 is the product of supply voltage and total IDD.   
The following is the power dissipation for VDD = 3.3V + 5ꢀ = 3.465V at ambient temperature of 105°C, QREFn = 25MHz, QC = 50MHz,  
QAn = 125MHz, QBn = 100MHz.  
IDD_MAX = 91mA  
IDDA_MAX = 16mA  
IDDOA_MAX + IDD0B_MAX + IDDOC_MAX + IDDORn_MAX = 141mA  
•
•
•
Power(core)_max = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (91mA + 16mA) = 370.76mW  
LVDS and LVCMOS Outputs Power(output)_max = 3.465V * 141mA = 488.57mW  
Total Power_max (3.465V, with all outputs switching) = 370.76mW + 488.57mW = 859.33mW  
2. Junction Temperature.  
Junction temperature, Tj, signifies the hottest point on the device and exceeding the specified limit could cause device reliability issues.   
The maximum recommended junction temperature is 125°C.  
For devices like this and in systems where most heat escapes from the bottom exposed pad of the package, JB is the primary thermal  
resistance of interest.  
The equation to calculate Tj using JB is: Tj = JB * PD + TB  
Tj = Junction Temperature  
JB = Junction-to-Board Thermal Resistance  
PD = Device Power Dissipation (example calculation is in section 1 above)  
TB = Board Temperature  
In order to calculate junction temperature, the appropriate junction-to-board thermal resistance JB must be used. Assuming a 2-ground plane  
board, the appropriate value of JB is 1.93°C/W per Table 8 below.  
Therefore, Tj for a PCB maintained at 115°C with the outputs switching is:  
115°C + 0.859W * 1.93°C/W = 116.7°C which is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, heat transfer  
method, the type of board (multi-layer) and the actual maintained board temperature. The below table is for two ground planes. The thermal  
resistance will change as the number of layers in the board changes or if the board size change and other changes in other factors impacts  
heat dissipation in the system.  
1, 2, 3  
Table 8. Thermal Resistances for a 48-Lead VFQFN Package  
Meters per Second  
Theta JB  
0
1
2
1.93°C/W  
26.11°C/W  
18.8°C/W  
1.93°C/W  
22.53°C/W  
18.8°C/W  
1.93°C/W  
21.04°C/W  
18.8°C/W  
Theta JA  
Theta JC  
NOTE 1. Applicable to PCBs with two ground planes.  
NOTE 2. ePAD size is 5.65mm x 5.65mm and connected to ground plane in PCB through 5 x5 Thermal Via Array.  
NOTE 3. In devices where most of the heat exits through the bottom ePAD, JB is commonly used for thermal calculations.  
©2016 Integrated Device Technology, Inc.  
22  
May 9, 2016  
8V44S269 Datasheet  
Reliability Information  
Table 9. Thermal Resistances for a 48 Lead VFQFN Package  
Meters per Second  
Theta JB  
0
1
2
1.93°C/W  
26.11°C/W  
18.8°C/W  
1.93°C/W  
22.53°C/W  
18.8°C/W  
1.93°C/W  
21.04°C/W  
18.8°C/W  
Theta JA  
Theta JC  
Transistor Count  
8V44S269 transistor count: 11,242  
©2016 Integrated Device Technology, Inc.  
23  
May 9, 2016  
8V44S269 Datasheet  
48 Lead VFQFN Package Information  
©2016 Integrated Device Technology, Inc.  
24  
May 9, 2016  
8V44S269 Datasheet  
48 Lead VFQFN Package Information  
©2016 Integrated Device Technology, Inc.  
25  
May 9, 2016  
8V44S269 Datasheet  
Ordering Information  
Table 10. Ordering Information  
Part/Order Number  
Marking  
Package  
Shipping Packaging  
Tray  
Temperature  
-55°C to 105°C  
-55°C to 105°C  
8V44S269NLGI  
8V44S269NLGI8  
IDT8V44S269NLGI  
IDT8V44S269NLGI  
48 Lead VFQFN, Lead-Free  
48 Lead VFQFN, Lead-Free  
Tape & Reel  
©2016 Integrated Device Technology, Inc.  
26  
May 9, 2016  
8V44S269 Datasheet  
Revision History Sheet  
Table  
Page  
Description of Change  
Date  
5/9/2016  
1
Corrected datasheet title head.  
©2016 Integrated Device Technology, Inc.  
27  
May 9, 2016  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
Sales  
Tech Support  
email: clocks@idt.com  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in  
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