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8V43042PGG8

型号:

8V43042PGG8

品牌:

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数:

19 页

PDF大小:

397 K

®
FemtoClock Crystal-to-3.3V LVPECL Frequency  
Synthesizer  
8V43042  
Datasheet  
General Description  
Features  
The 8V43042 is a two output LVPECL synthesizer optimized to  
generate low jitter reference clock sources. Using a 25MHz or  
24MHz, 12pF parallel resonant crystal, it can generate 156.25MHz  
or 150MHz, The 8V43042 uses 8V43042’s 3rd generation low phase  
noise VCO technology and can achieve 1ps or lower typical RMS  
phase jitter, easily meeting Ethernet jitter requirements. The  
8V43042 is packaged in a small 20-pin TSSOP package.  
Two 3.3V differential LVPECL output pairs  
Selectable crystal oscillator interface or LVCMOS/LVTTL  
single-ended clock input  
Supports the following output frequencies: 156.25MHz, 150MHz  
RMS phase jitter @ 156.25MHz, using a 25MHz crystal  
(1.875MHz – 20MHz): 0.437ps (typical)  
Full 3.3V supply modes  
0°C to 70°C ambient operating temperature  
Lead-free (RoHS 6) packaging  
Block Diagram  
Pin Assignment  
1
2
3
4
5
6
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
nc  
VCCO  
Q0  
V
CCO  
Pulldown  
nPLL_SEL  
Q1  
nQ1  
VEE  
Q0  
nQ0  
1
MR  
V
CC  
nQ0  
nPLL_SEL  
nc  
nXTAL_SEL  
TEST_CLK  
XTAL_IN  
XTAL_OUT  
nc  
Pulldown  
N = 4  
(fixed)  
TEST_CLK  
XTAL_IN  
1
7
8
Q1  
Phase  
VCCA  
nc  
VCO  
0
Detector  
nQ1  
9
10  
0
VCC  
OSC  
XTAL_OUT  
8V43042  
M = 25  
(fixed)  
20-Lead 4.4mm x 6.5mm TSSOP  
Pulldown  
Pulldown  
nXTAL_SEL  
MR  
©2016 Integrated Device Technology, Inc.  
1
Revison C, November 3, 2016  
8V43042 Datasheet  
Pin Descriptions and Characteristics  
Table 1. Pin Descriptions  
Number  
1, 7, 9, 11  
2, 20  
Name  
Type  
Description  
Unused  
Power  
Output  
No connect  
nc  
VCCO  
Output supply pins.  
3, 4  
Differential output pair. LVPECL interface levels.  
Q0, nQ0  
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset  
causing the true outputs Qx to go low and the inverted outputs nQx to go  
high. When logic LOW, the internal dividers and the outputs are enabled.  
LVCMOS/LVTTL interface levels.  
5
6
MR  
Input  
Pulldown  
Pulldown  
Selects either the PLL or the active input reference to be routed to the  
output dividers. When LOW, selects PLL (PLL Enable). When HIGH,  
selects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels.  
nPLL_SEL  
Input  
8
VCCA  
VCC  
Power  
Power  
Analog supply pin.  
Core supply pins.  
10, 16  
XTAL_OUT,  
XTAL_IN  
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the  
input.  
12, 13  
Input  
17  
14  
VEE  
Power  
Input  
Negative supply pins.  
TEST_CLK  
Pulldown  
Pulldown  
Single-ended clock input. LVCMOS/LVTTL interface levels.  
Selects between the single-ended TEST_CLK or crystal interface as the  
PLL reference source. When HIGH, selects TEST_CLK. When LOW,  
selects XTAL inputs. LVCMOS/LVTTL interface levels.  
15  
nXTAL_SEL  
nQ1, Q1  
Input  
18, 19  
Output  
Differential output pair. LVPECL interface levels.  
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
Parameter  
Test Conditions  
nPLL_SEL, nXTAL_SEL, MR  
TEST_CLK  
Minimum  
Typical  
Maximum  
Units  
pF  
4
2
CIN  
Input Capacitance  
Input Pulldown Resistor  
pF  
RPULLDOWN  
51  
k  
©2016 Integrated Device Technology, Inc.  
2
Revison C, November 3, 2016  
8V43042 Datasheet  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress  
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC  
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VCC  
4.6V  
Inputs, VI  
XTAL_IN  
0V to VCC  
Other Inputs  
-0.5V to VCC + 0.5V  
Outputs, IO (LVPECL)  
Continuous Current  
Surge Current  
50mA  
100mA  
Package Thermal Impedance, JA  
86.7C/W (0 mps)  
-65C to 150C  
Storage Temperature, TSTG  
DC Electrical Characteristics  
Table 3A. Power Supply DC Characteristics, V = V  
= 3.3V ± 5%, V = 0V, T = 0°C to 70°C  
EE A  
CC  
CCO  
Symbol  
VCC  
Parameter  
Test Conditions  
Minimum  
Typical  
3.3  
Maximum  
3.465  
3.465  
3.465  
135  
Units  
V
Core Supply Voltage  
Analog Supply Voltage  
Output Supply Voltage  
Power Supply Current  
Analog Supply Current  
3.135  
VCC - 0.15  
3.135  
VCCA  
VCCO  
IEE  
3.3  
V
3.3  
V
mA  
mA  
ICCA  
Included in IEE  
15  
Table 3B. LVCMOS/LVTTL DC Characteristics, V = V  
= 3.3V ± 5%, V = 0V, T = 0°C to 70°C  
EE A  
CC  
CCO  
Symbol  
VIH  
Parameter  
Test Conditions  
VCC = 3.3V ± 5%  
VCC = 3.3V ± 5%  
Minimum  
Typical  
Maximum  
VCC + 0.3  
0.8  
Units  
Input High Voltage  
Input Low Voltage  
2
V
V
VIL  
-0.3  
Input  
TEST_CLK, MR,  
IIH  
High  
Current  
nPLL_SEL,  
nXTAL_SEL  
VCC = VIN = 3.465V  
150  
µA  
µA  
Input  
Low  
TEST_CLK, MR,  
nPLL_SEL,  
IIL  
VCC = 3.465V, VIN = 0V  
-5  
Current  
nXTAL_SEL  
©2016 Integrated Device Technology, Inc.  
3
Revison C, November 3, 2016  
8V43042 Datasheet  
Table 3C. LVPECL DC Characteristics, V = V  
= 3.3V ± 5%, V = 0V, T = 0°C to 70°C  
CC  
CCO  
EE  
A
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Output High Voltage;  
NOTE 1  
VOH  
V
CCO – 1.4  
VCCO – 2.0  
0.6  
VCCO – 0.9  
V
Output Low Voltage;  
NOTE 1  
VOL  
VCCO – 1.7  
1.0  
V
V
Peak-to-Peak Output  
Voltage Swing  
VSWING  
NOTE 1: Outputs termination with 50to VCCO – 2V.  
Table 4. Crystal Characteristics  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Mode of Oscillation  
Fundamental  
Frequency  
24  
25  
50  
7
MHz  
Equivalent Series Resistance (ESR)  
Shunt Capacitance  
pF  
Load Capacitance (CL)  
12  
18  
pF  
©2016 Integrated Device Technology, Inc.  
4
Revison C, November 3, 2016  
8V43042 Datasheet  
AC Electrical Characteristics  
Table 5. AC Characteristics, V = V  
= 3.3V ± 5%, V = 0V, T = 0°C to 70°C  
EE A  
CC  
CCO  
Symbol  
fOUT  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
156.25  
40  
Units  
MHz  
ps  
Output Frequency Range  
Output Skew; NOTE 1, 2  
150  
tsk(o)  
156.25MHz, (1.875MHz – 20MHz)  
150MHz, (1.875MHz – 20MHz)  
20% to 80%  
0.437  
0.436  
ps  
RMS Phase Jitter,  
(Random); NOTE 3  
tjit(Ø)  
ps  
tR / tF  
odc  
Output Rise/Fall Time  
Output Duty Cycle  
300  
48  
650  
52  
ps  
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device  
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal  
equilibrium has been reached under these conditions  
NOTE: Characterized using an 18pF parallel resonant crystal.  
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint.  
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.  
NOTE 3: Please refer to the Phase Noise Plots.  
©2016 Integrated Device Technology, Inc.  
5
Revison C, November 3, 2016  
8V43042 Datasheet  
Typical Phase Noise at 156.25MHz  
Offset Frequency (Hz)  
©2016 Integrated Device Technology, Inc.  
6
Revison C, November 3, 2016  
8V43042 Datasheet  
Typical Phase Noise at 150MHz  
Offset Frequency (Hz)  
©2016 Integrated Device Technology, Inc.  
7
Revison C, November 3, 2016  
8V43042 Datasheet  
Parameter Measurement Information  
2V  
2V  
nQx  
Qx  
V
CC,  
V
CCO  
V
CCA,  
nQy  
Qy  
-1.3V ± 0.165V  
3.3V LVPECL Output Load Test Circuit  
Output Skew  
nQ[0:1]  
Q[0:1]  
RMS Phase Jitter  
Output Rise/Fall Time  
nQ[0:1]  
Q[0:1]  
Output Duty Cycle/Pulse Width/Period  
©2016 Integrated Device Technology, Inc.  
8
Revison C, November 3, 2016  
8V43042 Datasheet  
Applications Information  
Recommendations for Unused Input and Output Pins  
Inputs:  
Outputs:  
Crystal Inputs  
LVPECL Outputs  
For applications not requiring the use of the crystal oscillator input,  
both XTAL_IN and XTAL_OUT can be left floating. Though not  
required, but for additional protection, a 1kresistor can be tied from  
XTAL_IN to ground.  
All unused LVPECL outputs can be left floating. We recommend that  
there is no trace attached. Both sides of the differential output pair  
should either be left floating or terminated.  
TEST_CLK Input  
For applications not requiring the use of the clock, it can be left  
floating. Though not required, but for additional protection, a 1k  
resistor can be tied from the TEST_CLK to ground.  
LVCMOS Control Pins  
All control pins have internal pulldowns; additional resistance is not  
required but can be added for additional protection. A 1kresistor  
can be used.  
Termination for 3.3V LVPECL Outputs  
The clock layout topology shown below is a typical termination for  
LVPECL outputs. The two different layouts mentioned are  
recommended only as guidelines.  
transmission lines. Matched impedance techniques should be used  
to maximize operating frequency and minimize signal distortion.  
Figures 1A and 1B show two different layouts which are  
recommended only as guidelines. Other suitable clock layouts may  
exist and it would be recommended that the board designers  
simulate to guarantee compatibility across all printed circuit and clock  
component process variations.  
The differential outputs are low impedance follower outputs that  
generate ECL/LVPECL compatible outputs. Therefore, terminating  
resistors (DC current path to ground) or current sources must be  
used for functionality. These outputs are designed to drive 50  
3.3V  
R3  
R4  
125  
125  
3.3V  
3.3V  
Zo = 50  
+
_
Input  
Zo = 50  
R1  
84  
R2  
84  
Figure 1A. 3.3V LVPECL Output Termination  
Figure 1B. 3.3V LVPECL Output Termination  
©2016 Integrated Device Technology, Inc.  
9
Revison C, November 3, 2016  
8V43042 Datasheet  
Overdriving the XTAL Interface  
The XTAL_IN input can be overdriven by an LVCMOS driver or by  
one side of a differential driver through an AC coupling capacitor. The  
XTAL_OUT pin can be left floating. The amplitude of the input signal  
should be between 500mV and 1.8V and the slew rate should not be  
less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be  
reduced from full swing to at least half the swing in order to prevent  
signal interference with the power rail and to reduce internal noise.  
Figure 2A shows an example of the interface diagram for a high  
speed 3.3V LVCMOS driver. This configuration requires that the sum  
of the output impedance of the driver (Ro) and the series resistance  
(Rs) equals the transmission line impedance. In addition, matched  
termination at the crystal input will attenuate the signal in half. This  
can be done in one of two ways. First, R1 and R2 in parallel should  
equal the transmission line impedance. For most 50applications,  
R1 and R2 can be 100. This can also be accomplished by removing  
R1 and changing R2 to 50. The values of the resistors can be  
increased to reduce the loading for a slower and weaker LVCMOS  
driver. Figure 2B shows an example of the interface diagram for an  
LVPECL driver. This is a standard LVPECL termination with one side  
of the driver feeding the XTAL_IN input. It is recommended that all  
components in the schematics be placed in the layout. Though some  
components might not be used, they can be utilized for debugging  
purposes. The datasheet specifications are characterized and  
guaranteed by using a quartz crystal as the input.  
VCC  
XTAL_OUT  
R1  
100  
C1  
Rs  
Zo = 50 ohms  
Ro  
XTAL_IN  
.1uf  
R2  
100  
Zo = Ro + Rs  
LVCMOS Driver  
Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface  
XTAL_OUT  
C2  
Zo = 50 ohms  
XTAL_I N  
.1uf  
Zo = 50 ohms  
R1  
50  
R2  
50  
LVPECL Driver  
R3  
50  
Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface  
©2016 Integrated Device Technology, Inc.  
10  
Revison C, November 3, 2016  
8V43042 Datasheet  
Schematic Example  
Figure 3 shows an example of 8V43042 application schematic. In this  
example, the device is operated at VCC = VCCA = VCCO = 3.3V. The  
schematic example focuses on functional connections and is not  
configuration specific. Refer to the pin description and functional  
tables in the datasheet to ensure that the logic control inputs are  
properly set.  
In order to achieve the best possible filtering, it is recommended that  
the placement of the filter components be on the device side of the  
PCB as close to the power pins as possible. If space is limited, the  
0.1µF capacitor in each power pin filter should be placed on the  
device side. The other components can be on the opposite side of the  
PCB.  
A 12pF parallel resonant 25MHz crystal is used. For this device, the  
crystal load capacitors are required for proper operation. The load  
capacitance, C1 = C2 = 10pF, are recommended for frequency  
accuracy. Depending on the variation of the parasitic stray capacity  
of the printed circuit board traces between the crystal and the  
XXTAL_IN and XXTAL_OUT pins, the values of C1 and C2 might  
require a slight adjustment to optimize the frequency accuracy.  
Crystals with other load capacitance specifications can be used, but  
this will require adjusting C1 and C2. When designing the circuit  
board, return the capacitors to ground though a single point contact  
close to the package. Two Fox crystal options are shown in the  
schematic for design flexibility.  
Power supply filter recommendations are a general guideline to be  
used for reducing external noise from coupling into the devices. The  
filter performance is designed for a wide range of noise frequencies.  
This low-pass filter starts to attenuate noise at approximately 10kHz.  
If a specific frequency noise component is known, such as switching  
power supplies frequencies, it is recommended that component  
values be adjusted and if required, additional filtering be added.  
Additionally, good general design practices for power plane voltage  
stability suggests adding bulk capacitance in the local area of all  
devices.  
As with any high speed analog circuitry, the power supply pins are  
vulnerable to random noise. To achieve optimum jitter performance,  
power supply isolation is required. The 8V43042 provides separate  
power supplies to isolate any high switching noise from coupling into  
the internal PLL.  
©2016 Integrated Device Technology, Inc.  
11  
Revison C, November 3, 2016  
8V43042 Datasheet  
3.3V  
Place each 0.1uF bypass cap directly adjacent to its  
corresponding VCC, VCCA or VCCO pin.  
FB1  
2
1
VCC  
C11  
C5  
BLM18BB221SN1  
C4  
0.1uF  
0.1uF  
R2 10  
10uF  
VCCA  
C6  
0.1uF  
C7  
0.1uF  
C3  
U1  
10uF  
3.3V  
FB2  
5
2
2
1
MR  
VCCO  
C12  
0.1uF  
MR  
VCCO  
VCCO  
nPLL_SEL  
nXTAL_SEL  
6
C9  
10uF  
BLM18BB221SN1  
nPLL_SEL  
C8  
0.1uF  
15  
20  
nXTAL_SEL  
C10  
0.1uF  
FOX 603-25-173 crystal  
XTAL_IN  
1
13  
12  
XTAL_IN  
Zo = 50 Ohm  
Zo = 50 Ohm  
25 MHz  
(12pF)  
3
4
X2  
Q0  
Q0  
+
-
2
4
XTAL_OUT  
nQ0  
nQ0  
XTAL_OUT  
3
C1  
C2  
2pF  
2pF  
R8  
50  
R6  
50  
+3.3V LVPECL Receiver  
R7  
50  
Zo = 50 Ohm  
19  
18  
Q1  
Q1  
+
-
R3  
100  
3.3V  
nQ1  
nQ1  
Zo = 50 Ohm  
Ro  
=7 Ohm  
R1  
43  
Zo = 50 Ohm  
14  
R5  
150  
R4  
150  
+3.3V LVPECL Receiver  
TEST_CLK  
Logic Control Input Examples  
1
7
9
11  
LVCMOS Driver  
nc  
nc  
nc  
nc  
Set Logic  
Input to '1'  
Set Logic  
Input to '0'  
VCC  
VCC  
RU1  
1k  
RU2  
Not Install  
To Logic  
Input  
pins  
To Logic  
Input  
pins  
RD1  
Not Install  
RD2  
1k  
Figure 3. 8V43042 Schematic Example  
©2016 Integrated Device Technology, Inc.  
12  
Revison C, November 3, 2016  
8V43042 Datasheet  
Power Considerations  
This section provides information on power dissipation and junction temperature for the 8V43042.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the 8V43042 is the sum of the core power plus the power dissipated in the load(s).  
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.  
Power (coreM) AX = VCC_MAX * IEE_MAX = 3.465V * 135mA = 467.775mW  
Power (outputsM) AX = 30mW/Loaded Output pair  
If all outputs are loaded, the total power is 2 * 30mW = 60mW  
Total Power_MAX (3.465V, with all outputs switching) = 467.775mW + 60mW = 527.775mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air  
flow of 1 meter per second and a multi-layer board, the appropriate value is 86.7°C/W per Table 6 below.  
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:  
70°C + 0.528W * 86.7°C/W = 115.8°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 6. Thermal Resistance for 20 Lead TSSOP, Forced Convection  
JA  
JA vs. Air Flow  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
86.7°C/W  
82.4°C/W  
80.2°C/W  
©2016 Integrated Device Technology, Inc.  
13  
Revison C, November 3, 2016  
8V43042 Datasheet  
3. Calculations and Equations.  
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.  
LVPECL output driver circuit and termination are shown in Figure 4.  
VCCO  
Q1  
VOUT  
RL  
50  
VCCO - 2V  
Figure 4. LVPECL Driver Circuit and Termination  
To calculate worst case power dissipation into the load, use the following equations which assume a 50load, and a termination voltage of  
VCCO – 2V.  
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V  
(VCCO_MAX – VOH_MAX) = 0.9V  
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V  
(VCCO_MAX – VOL_MAX) = 1.7V  
Pd_H is power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX  
)
= [(2V – 0.9V)/50] * 0.9V = 19.8mW  
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX  
)
= [(2V – 1.7V)/50] * 1.7V = 10.2mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW  
©2016 Integrated Device Technology, Inc.  
14  
Revison C, November 3, 2016  
8V43042 Datasheet  
Reliability Information  
Table 7. vs. Air Flow Table for a 20 Lead TSSOP  
JA  
JA vs. Air Flow  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
86.7°C/W  
82.4°C/W  
80.2°C/W  
Transistor Count  
The transistor count for 8V43042 is: 2,967  
©2016 Integrated Device Technology, Inc.  
15  
Revison C, November 3, 2016  
8V43042 Datasheet  
20 Lead TSSOP Package Outline and Package Dimensions  
©2016 Integrated Device Technology, Inc.  
16  
Revison C, November 3, 2016  
8V43042 Datasheet  
20 Lead TSSOP Package Outline and Package Dimensions  
©2016 Integrated Device Technology, Inc.  
17  
Revison C, November 3, 2016  
8V43042 Datasheet  
20 Lead TSSOP Package Outline and Package Dimensions  
©2016 Integrated Device Technology, Inc.  
18  
Revison C, November 3, 2016  
8V43042 Datasheet  
Ordering Information  
Table 8. Ordering Information  
Part/Order Number  
Marking  
Package  
Shipping Packaging  
Tube  
Temperature  
0C to 70C  
0C to 70C  
8V43042PGG  
8V43042PGG8  
IDT8V43042PGG  
IDT8V43042PGG  
20 Lead TSSOP, Lead-Free  
20 Lead TSSOP, Lead-Free  
Tape & Reel  
Revision History Sheet  
Rev  
Table  
Page  
Description of Change  
Updated schematic with IDT crystal recommendation.  
Date  
12  
B
Deleted prefix/suffix from part number throughout the datasheet.  
Updated header/footer.  
7/24/15  
11/3/16  
C
12  
Schematic - replaced IDT crystal recommendation with FOX.  
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DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance spec-  
ifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information  
contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied  
warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of  
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sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
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of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.  
©2016 Integrated Device Technology, Inc.  
19  
Revison C, November 3, 2016  
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