8V49N231 Datasheet
Schematic Layout
Figure 5 shows an example 8V49N231 application schematic. The
schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set. Input and output terminations shown are intended as examples
only and may not represent the exact user configuration.
under the crystal, then void enough power and signal planes to
minimize the coupling capacity. Ensure that the ground under the
crystal is the same ground as used for the tuning caps and the
oscillator.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 8V49N231 provides separate
The schematic example shows two different HCSL output
terminations; the standard termination for the case in which the
HCSL receiver is on the same PCB as the 8V49N231 as well as the
termination for an attached PCIe add-in card.
V
V
DD, VDDD, VDDA, VDD_XTAL and VDDO_REF, VDDO_A, VDDO_B
DDO_C, and VDDO_C5 pins to isolate any high speed switching noise
,
at the outputs from coupling into the internal PLL.
In this example a 12pF parallel resonant 25MHz crystal is used with
load caps C1 = C2 = 10pF. Crystals with other load capacitance
specifications can be used, for example, a CL=18pF crystal can be
used with two 22pF tuning capacitors. Depending on the parasitics of
the printed circuit board layout, the values of C1 and C2 might require
a slight adjustment to optimize the frequency accuracy. For this
device, the crystal tuning capacitors are required for proper
operation.
In order to achieve the best possible filtering, it is highly
recommended that the 0.1µF capacitors be placed on the 8V49N231
side of the PCB as close to the power pins as possible. This is
represented by the placement of these capacitors in the schematic.
If space is limited, the ferrite beads, 10µf capacitors and the 0.1µF
capacitors connected directly to 3.3V can be placed on the opposite
side of the PCB. If space permits, place all filter components on the
device side of the board.
Crystal layout is very important to minimize capacitive coupling
between the crystal pads and leads and other metal in the circuit
board. Capacitive coupling to other conductors has two adverse
effects. The first is that it reduces the oscillator frequency, leaving
less tuning margin. Second, noise on power planes and logic
transitions on signal traces can pull the phase of voltages on the
XTAL_IN and XTAL_OUT pins of the oscillator.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10 kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
Using a crystal on the top layer as an example, void all signal and
power layers under the crystal, XTAL_IN, XTAL_OUT and the input
pins of the 8V49N231 between the top layer and the ground plane for
the 8V49N231. If the ground plane for the 8V49N231 is the first layer
©2016 Integrated Device Technology, Inc.
22
Revison C, November 2, 2016
