8V49N211 DATA SHEET
Schematic Layout
Figure 5 shows an example 8V49N211 application schematic. The
schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set. Input and output terminations shown are intended as examples
only and may not represent the exact user configuration.
reached. The ground connection of the tuning capacitors should first
be made between the capacitors on the top layer, then a single
ground via is dropped to connect the tuning cap ground to the ground
plane as close to the 8V49N211 as possible as shown in the
schematic.
The schematic example shows two different HCSL output
terminations; the standard termination for the case in which the
HCSL receiver is on the same PCB as the 8V49N211 as well as the
termination for an attached PCIe add-in card.
In this example a 12pF parallel resonant 25MHz crystal (IDT/ FOX
Part #603-25-173) is used with the recommended load caps C1 = C2
= 2pF. Use a single point ground connection for the two load caps as
shown in the schematic. The load caps are recommended for
frequency accuracy, but these may be adjusted for different board
layouts. Crystals with different load capacities may be used, but the
load capacitors will have to be changed accordingly. If different
crystal types are used, please consult IDT for recommendations.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 8V49N211 provides separate
VDD, VDDD, VDDA, VDD_XTAL and VDDO_REF, VDDO_A, VDDO_B,
VDDO_C, and VDDO_C5 pins to isolate any high speed switching noise
at the outputs from coupling into the internal PLL.
Crystal layout is very important to minimize capacitive coupling
between the crystal pads and leads and other metal in the circuit
board. Capacitive coupling to other conductors has two adverse
effects; it reduces the oscillator frequency leaving less tuning margin
and noise coupling from power planes and logic transitions on signal
traces can pull the phase of the crystal resonance, inducing jitter.
Routing I2C under the crystal is a very common layout error, based
on the assumption that it is a low frequency signal and will not affect
the crystal oscillation. In fact, I2C transition times are short enough to
capacitively couple into the crystal if they are routed close enough to
the crystal traces.
In order to achieve the best possible filtering, it is highly
recommended that the 0.1µF capacitors be placed on the 8V49N211
side of the PCB as close to the power pins as possible. This is
represented by the placement of these capacitors in the schematic.
If space is limited, the ferrite beads, 10µF capacitors and the 0.1µF
capacitors connected directly to 3.3V can be placed on the opposite
side of the PCB. If space permits, place all filter components on the
device side of the board.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
In layout, all capacitive coupling to the crystal from any signal trace is
to be minimized, that is to the XTAL_IN and XTAL_OUT pins, traces
to the crystal pads, the crystal pads and the tuning capacitors. Using
a crystal on the top layer as an example, void all signal and power
layers under the crystal connections between the top layer and the
ground plane used by the 8V49N211. Then calculate the parasitic
capacity to the ground and determine if it is large enough to preclude
tuning the oscillator. If the coupling is excessive, particularly if the first
layer under the crystal is a ground plane, a layout option is to void the
ground plane and all deeper layers until the next ground plane is
REVISION B 05/29/15
23
CLOCK GENERATOR FOR BROADCOM PROCESSOR
