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8SLVP1212ANLGI/W

型号：

8SLVP1212ANLGI/W

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

25 页

PDF大小：

881 K

下载PDF手册
Low Phase Noise, 1-to-12, 3.3V, 2.5V  
LVPECL Output Fanout Buffer  
IDT8SLVP1212I  
DATASHEET  
General Description  
Features  
The IDT8SLVP1212I is a high-performance, 12 output differential  
LVPECL fanout buffer. The device is designed for the fanout of  
high-frequency, very low additive phase-noise clock and data signals.  
The IDT8SLVP1212I is characterized to operate from a 3.3V and  
2.5V power supply. Guaranteed output-to-output and part-to-part  
skew characteristics make the IDT8SLVP1212I ideal for those clock  
distribution applications demanding well-defined performance and  
repeatability. Two selectable differential inputs and twelve low skew  
outputs are available. The integrated bias voltage generators enables  
easy interfacing of single-ended signals to the device inputs. The  
device is optimized for low power consumption and low additive  
phase noise.  
• Twelve low skew, low additive jitter LVPECL outputs  
• Two selectable, differential clock inputs  
• Differential pairs can accept the following differential input  
levels: LVDS, LVPECL, CML  
• Maximum input clock frequency: 2GHz  
• LVCMOS interface levels for the control input (input select)  
• Output skew: 33ps (maximum)  
• Propagation delay: 550ps (maximum)  
• Low additive phase jitter, RMS at fREF = 156.25MHz, VPP = 1V,  
12kHz-20MHz: 60fs (maximum)  
• Full 3.3V and 2.5V supply voltage  
• Device current consumption (IEE): 131mA (maximum)  
• Available in Lead-free (RoHS 6), 40-Lead VFQFN package  
• -40°C to 85°C ambient operating temperature  
• Differential PCLK0, nPCLK0 and PCLK1, nPCLK1 pairs can also  
accept single-ended LVCMOS levels. See Applications section  
Wiring the Differential Input Levels to Accept Single-ended Levels  
(Figure 1A and Figure 1B)  
Block Diagram  
Q0  
nQ0  
Q1  
nQ1  
Pin Assignment  
Q2  
nQ2  
30 29 28 27 26 25 24 23 22 21  
V
CC  
V
31  
20  
V
CC  
CC  
Q3  
nQ3  
Q8 32  
nQ8 33  
Q9 34  
19 nQ3  
18 Q3  
17 nQ2  
16 Q2  
15 nQ1  
14 Q1  
13 nQ0  
12 Q0  
PCLK0  
nPCLK0  
Q4  
nQ4  
nQ9 35  
Q10 36  
nQ10 37  
Q11 38  
nQ11 39  
Q5  
nQ5  
fREF  
V
Q6  
nQ6  
CC  
V
40  
11  
V
CC  
CC  
1
2
3
4
5
6
7 8 9 10  
Q7  
nQ7  
PCLK1  
nPCLK1  
Q8  
nQ8  
Q9  
SEL  
IDT8SLVP1212I  
40-lead VFQFN  
6mm x 6mm x 0.925mm package body,  
2.9mm x 2.9mm E-Pad size  
NL Package, Top View  
nQ9  
Q10  
nQ10  
Voltage  
Reference  
VREF  
Q11  
nQ11  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
1
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
Reference select control. See Table 3A for function.  
LVCMOS/LVTTL interface levels.  
1
SEL  
Input  
Pulldown  
Pulldown  
2
3
PCLK1  
nPCLK1  
nc  
Input  
Input  
Non-inverting LVPECL differential clock/data input.  
Inverting LVPECL differential clock/data input.  
Do not connect.  
Pulldown/Pullup  
4, 10  
Unused  
5, 6, 11, 20,  
31, 40  
VCC  
Power  
Power supply pins.  
7
VREF  
nPCLK0  
PCLK0  
Output  
Input  
Bias voltage reference.  
8
Pulldown/Pullup  
Pulldown  
Inverting LVPECL differential clock/data input.  
Non-inverting LVPECL differential clock/data input.  
Differential output pair 0. LVPECL interface levels.  
Differential output pair 1. LVPECL interface levels.  
Differential output pair 2. LVPECL interface levels.  
Differential output pair 3. LVPECL interface levels.  
Negative power supply pins.  
9
Input  
12, 13  
14, 15  
16, 17  
18, 19  
21, 30  
22, 23  
24, 25  
26, 27  
28, 29  
32, 33  
34, 35  
36, 37  
38, 39  
Q0, nQ0  
Q1, nQ1  
Q2, nQ2  
Q3, nQ3  
VEE  
Output  
Output  
Output  
Output  
Power  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Q4, nQ4  
Q5, nQ5  
Q6, nQ6  
Q7, nQ7  
Q8, nQ8  
Q9, nQ9  
Q10, nQ10  
Q11, nQ11  
Differential output pair 4. LVPECL interface levels.  
Differential output pair 5. LVPECL interface levels.  
Differential output pair 6. LVPECL interface levels.  
Differential output pair 7. LVPECL interface levels.  
Differential output pair 8. LVPECL interface levels.  
Differential output pair 9. LVPECL interface levels.  
Differential output pair 10. LVPECL interface levels.  
Differential output pair 11. LVPECL interface levels.  
NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
pF  
CIN  
Input Capacitance  
Input Pulldown Resistor  
Input Pullup Resistor  
2
RPULLDOWN  
RPULLUP  
51  
51  
k  
k  
Function Table  
Table 3. SEL Input Section Function Table  
Input  
SEL  
0 (default)  
1
Operation  
PCLK0, nPCLK0 is the selected differential clock input  
PCLK1, nPCLK1 is the selected differential clock input  
NOTE: SEL is an asynchronous control.  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
2
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress  
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or  
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VCC  
Inputs, VI  
4.6V  
-0.5V to VCC + 0.5V  
Outputs, IO (LVPECL)  
Continuous Current  
Surge Current  
50mA  
100mA  
Maximum Junction Temperature, TJ,MAX  
Storage Temperature, TSTG  
125 C  
-65C to 150C  
2000V  
ESD - Human Body Model (NOTE 1)  
ESD - Charged Device Model (NOTE 1)  
500V  
NOTE 1: According to JEDEC/JESD 22-A114/22-C101. ESD ratings are target specifications.  
DC Electrical Characteristics  
Table 4A. Power Supply DC Characteristics, V = 3.3V 5%, V = 0V, T = -40°C to 85°C  
CC  
EE  
A
Symbol  
VCC  
Parameter  
Test Conditions  
Minimum  
Typical  
3.3V  
Maximum  
3.465  
Units  
V
Power Supply Voltage  
Power Supply Current  
3.135  
IEE  
110  
131  
mA  
Q[0:11] terminated 501% to  
CC – 2V  
ICC  
Power Supply Current  
490  
550  
mA  
V
Table 4B. Power Supply DC Characteristics, V = 2.5V 5%, V = 0V, T = -40°C to 85°C  
CC  
EE  
A
Symbol  
VCC  
Parameter  
Test Conditions  
Minimum  
Typical  
2.5V  
Maximum  
2.625  
Units  
V
Power Supply Voltage  
Power Supply Current  
2.375  
IEE  
104  
124  
mA  
Q[0:11] terminated 501% to  
CC – 2V  
ICC  
Power Supply Current  
490  
550  
mA  
V
Table 4C. LVCMOS/LVTTL DC Characteristics, V = 3.3V 5% or 2.5V 5%, V = 0V, T = -40°C to 85°C  
CC  
EE  
A
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
VCC + 0.3  
VCC + 0.3  
0.8  
Units  
V
VCC = 3.465V  
VCC = 2.625V  
2.2  
1.7  
VIH  
Input High Voltage  
V
VCC = 3.465V  
-0.3  
-0.3  
V
VIL  
Input Low Voltage  
VCC = 2.625V  
0.7  
V
IIH  
IIL  
Input High Current  
Input Low Current  
SEL  
SEL  
VCC = VIN = 3.465V or 2.625V  
VCC = 3.465V or 2.625V, VIN = 0V  
150  
µA  
µA  
-10  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
3
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
Table 4D. LVPECL DC Characteristics, V = 3.3V 5%, V = 0V, T = -40°C to 85°C  
CC  
EE  
A
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Input High PCLK0, nPCLK0  
IIH  
VCC = VIN = 3.465V  
150  
µA  
Current  
PCLK1, nPCLK1  
PCLK0, PCLK1  
V
CC = 3.465V, VIN = 0V  
-10  
µA  
µA  
Input Low  
Current  
IIL  
nPCLK0, nPCLK1  
VCC = 3.465V, VIN = 0V  
REF = 2mA  
-150  
Reference Voltage for Input  
Bias; NOTE 1  
VREF  
I
VCC – 1.6  
VCC – 1.26  
VCC – 1.1  
V
VOH  
VOL  
Output High Voltage; NOTE 2  
Output Low Voltage; NOTE 2  
VCC – 1.26  
VCC – 1.7  
VCC – 0.84  
VCC – 1.5  
VCC – 0.6  
V
V
VCC – 1.28  
NOTE: Input and output parameters vary 1:1 with VCC  
.
NOTE 1: VREF is for 3.3V 5% VCC only. To obtain a bias voltage for VCC = 2.5V 5% application, an external voltage supply is recommended.  
NOTE 2: Outputs terminated with 50to VCC – 2V.  
Table 4E. LVPECL DC Characteristics, V = 2.5V 5%, V = 0V, T = -40°C to 85°C  
CC  
EE  
A
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Input High PCLK0, nPCLK0  
IIH  
VCC = VIN = 2.625V  
150  
µA  
Current  
PCLK1, nPCLK1  
PCLK0, PCLK1  
V
CC = 2.625V, VIN = 0V  
-10  
µA  
µA  
Input Low  
Current  
IIL  
nPCLK0, nPCLK1  
VCC = 2.625V, VIN = 0V  
REF = 2mA  
-150  
Reference Voltage for Input  
Bias; NOTE 1  
VREF  
I
VCC – 1.6  
VCC – 1.26  
VCC – 1.1  
V
VOH  
VOL  
Output High Voltage; NOTE 2  
Output Low Voltage; NOTE 2  
VCC – 1.26  
VCC – 1.7  
VCC – 0.84  
VCC – 1.47  
VCC – 0.6  
V
V
VCC – 1.28  
NOTE: Input and output parameters vary 1:1 with VCC  
.
NOTE 1: VREF is for 3.3V 5% VCC only. To obtain a bias voltage for VCC = 2.5V 5% application, an external voltage supply is recommended.  
NOTE 2: Outputs terminated with 50to VCC – 2V.  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
4
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
AC Electrical Characteristics  
Table 5. AC Electrical Characteristics, V = 3.3V 5% or 2.5V 5%, V = 0V, T = -40°C to 85°C  
CC  
EE  
A
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum Units  
Input  
PCLK[0:1],  
fREF  
2
GHz  
V/ns  
ps  
Frequency nPCLK[0:1]  
Input PCLK[0:1],  
Edge Rate nPCLK[0:1]  
V/t  
1.5  
PCLKx, nPCLKx to any Qx, nQx  
for VPP = 0.1V or 0.3V  
tPD  
Propagation Delay; NOTE 1  
230  
360  
550  
MUX_ISOLATION MUX Isolation  
fREF = 100MHz  
70  
17  
10  
dB  
ps  
ps  
ps  
tsk(o)  
tsk(p)  
tsk(pp)  
Output Skew; NOTE 2, 3  
33  
50  
Pulse Skew  
fREF = 100MHz  
Part-to-Part Skew; NOTE 3, 4  
150  
fREF = 122.88MHz,  
Square Wave, VPP = 0.8V,  
Integration Range: 1kHz– 40MHz  
90  
60  
55  
61  
45  
45  
60  
45  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fREF = 122.88MHz,  
Square Wave, VPP = 0.8V, Integration  
Range: 10kHz – 20MHz  
fREF = 122.88MHz,  
Square Wave, VPP = 0.8V, Integration  
Range: 12kHz – 20MHz  
fREF = 156.25MHz,  
Square Wave, VPP = 1V, Integration  
Range: 1kHz– 40MHz  
76  
60  
60  
90  
80  
80  
Buffer Additive Phase Jitter,  
RMS; refer to Additive Phase  
Jitter Section  
fREF = 156.25MHz,  
Square Wave, VPP = 1V, Integration  
Range: 10kHz – 20MHz  
tJIT  
fREF = 156.25MHz,  
Square Wave, VPP = 1V, Integration  
Range: 12kHz – 20MHz  
fREF = 156.25MHz  
Square Wave, VPP = 0.5V, Integration  
Range: 1kHz– 40MHz  
fREF = 156.25MHz,  
Square Wave, VPP = 0.5V, Integration  
Range: 10kHz – 20MHz  
fREF = 156.25MHz,  
Square Wave, VPP = 0.5V, Integration  
Range: 12kHz – 20MHz  
45  
tR / tF  
VPP  
Output Rise/ Fall Time  
20% to 80%  
f < 1.5GHz  
f > 1.5GHz  
70  
0.1  
0.2  
110  
170  
1.5  
1.5  
ps  
V
Differential Input Voltage;  
NOTE 5, 7  
V
Common Mode Input  
Voltage; NOTE 5, 6, 7  
VCMR  
1.0  
V
CC – 0.3  
V
VCC = 3.3V 5%, fREF 2GHz  
VCC = 2.5V 5%, fREF 2GHz  
VCC = 3.3V 5%, fREF 2GHz  
VCC = 2.5V 5%, fREF 2GHz  
0.45  
0.45  
0.9  
0.68  
0.68  
1.36  
1.36  
0.90  
0.90  
1.8  
V
V
V
V
Output Voltage Swing,  
Peak-to-Peak  
VO(pp)  
Differential Output Voltage  
Swing, Peak-to-Peak  
VDIFF_OUT  
0.9  
1.8  
NOTES on next page.  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
5
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE 1: Measured from the differential input crosspoint to the differential output crosspoint.  
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints.  
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.  
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and  
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints.  
NOTE 5: V should not be less than -0.3V. V should not be higher than V .  
IL  
IH  
CC  
NOTE 6: Common mode input voltage is defined at the crosspoint.  
NOTE 7: For single-ended LVCMOS input applications, please refer to the Applications Information, Wiring the Differential Input to accept  
single-ended levels, Figures 1A and 1B.  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
6
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
Additive Phase Jitter (3.3V at 122.88MHz)  
The spectral purity in a band at a specific offset from the fundamental  
compared to the power of the fundamental is called the dBc Phase  
Noise. This value is normally expressed using a Phase noise plot  
and is most often the specified plot in many applications. Phase noise  
is defined as the ratio of the noise power present in a 1Hz band at a  
specified offset from the fundamental frequency to the power value of  
the fundamental. This ratio is expressed in decibels (dBm) or a ratio  
of the power in the 1Hz band to the power in the fundamental. When  
the required offset is specified, the phase noise is called a dBc value,  
which simply means dBm at a specified offset from the fundamental.  
By investigating jitter in the frequency domain, we get a better  
understanding of its effects on the desired application over the entire  
time record of the signal. It is mathematically possible to calculate an  
expected bit error rate given a phase noise plot.  
Offset from Carrier Frequency (Hz)  
As with most timing specifications, phase noise measurements have  
issues relating to the limitations of the measurement equipment. The  
noise floor of the equipment can be higher or lower than the noise  
floor of the device. Additive phase noise is dependent on both the  
noise floor of the input source and measurement equipment.  
Measured using a Wenzel 122.88MHz Oscillator as the input source.  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
7
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
Additive Phase Jitter (3.3V at 156.25MHz)  
The spectral purity in a band at a specific offset from the fundamental  
compared to the power of the fundamental is called the dBc Phase  
Noise. This value is normally expressed using a Phase noise plot  
and is most often the specified plot in many applications. Phase noise  
is defined as the ratio of the noise power present in a 1Hz band at a  
specified offset from the fundamental frequency to the power value of  
the fundamental. This ratio is expressed in decibels (dBm) or a ratio  
of the power in the 1Hz band to the power in the fundamental. When  
the required offset is specified, the phase noise is called a dBc value,  
which simply means dBm at a specified offset from the fundamental.  
By investigating jitter in the frequency domain, we get a better  
understanding of its effects on the desired application over the entire  
time record of the signal. It is mathematically possible to calculate an  
expected bit error rate given a phase noise plot.  
Offset from Carrier Frequency (Hz)  
As with most timing specifications, phase noise measurements have  
issues relating to the limitations of the measurement equipment. The  
noise floor of the equipment can be higher or lower than the noise  
floor of the device. Additive phase noise is dependent on both the  
noise floor of the input source and measurement equipment.  
Measured using a Wenzel 156.25MHz Oscillator as the input source.  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
8
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
Parameter Measurement Information  
2V  
2V  
SCOPE  
SCOPE  
Qx  
VCC  
VCC  
Qx  
nQx  
nQx  
VEE  
VEE  
-1.3V 1.65V  
-0.5V 0.125V  
3.3V LVPECL Output Load AC Test Circuit  
2.5V LVPECL Output Load AC Test Circuit  
V
CC  
nQx  
Qx  
nPCLK[0, 1]  
PCLK[0, 1]  
nQy  
Qy  
V
EE  
Differential Input Level  
Output Skew  
nQx  
Qx  
Part 1  
nQx  
Qx  
nQy  
Qy  
Part 2  
nQy  
tPLH  
tPHL  
Qy  
tsk(pp)  
tsk(p)= tPHL - tPLH  
Part-to-Part Skew  
Pulse Skew  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
9
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
Parameter Measurement Information, continued  
nPCLK[1, 0]  
nQ[0:11]  
Q[0:11]  
PCLK[1, 0]  
nQ[0:11]  
Q[0:11]  
tPD  
Output Rise/Fall Time  
Propagation Delay  
Spectrum of Output Signal Q  
MUX selects active  
input clock signal  
A0  
Q
VDIFF_OUT  
VO(pp)  
MUX_ISOL = A0 – A1  
L or H  
SEL  
MUX selects static input  
A1  
Differential Voltage Swing = 2 x Single-ended VO(pp)  
Frequency  
(fundamental)  
Output Voltage Swing  
MUX Isolation  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
10  
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
Applications Information  
Wiring the Differential Input to Accept Single-Ended Levels  
The IDT8SLVP1212I inputs can be interfaced to LVPECL, LVDS,  
CML or LVCMOS drivers. Figure 1A illustrates how to dc couple a  
single LVCMOS input to the IDT8SLVP1212I. The value of the series  
resistance RS is calculated as the difference between the  
transmission line impedance and the driver output impedance. This  
resistor should be placed close to the LVCMOS driver. To avoid  
cross-coupling of single-ended LVCMOS signals, apply the LVCMOS  
signals to no more than one PCLK input.  
A practical method to implement Vth is shown in Figure 1B below.  
The reference voltage Vth = V1 = VCC/2, is generated by the bias  
resistors R1 and R2. The bypass capacitor (C1) is used to help filter  
noise on the DC bias. This bias circuit should be located as close to  
the input pin as possible.  
The ratio of R1 and R2 might need to be adjusted to position the V1  
in the center of the input voltage swing. For example, if the input clock  
swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted  
to set V1 at 1.25V. The values below apply when both the  
single-ended swing and VCC are at the same voltage.  
Figure 1A. DC-Coupling a Single LVCMOS Input to the  
IDT8SLVP1212I  
When using single-ended signaling, the noise rejection benefits of  
differential signaling are reduced. Even though the differential input  
can handle full rail LVCMOS signaling, it is recommended that the  
amplitude be reduced, particularly if both input references are  
LVCMOS to minimize cross talk. The datasheet specifies a lower  
differential amplitude, however this only applies to differential signals.  
For single-ended applications, the swing can be larger, however VIL  
load. This configuration requires that the sum of the output  
impedance of the driver (Ro) and the series resistance (Rs) equals  
the transmission line impedance. R3 and R4 in parallel should equal  
the transmission line impedance; for most 50applications, R3 and  
R4 will be 100. The values of the resistors can be increased to  
reduce the loading for slower and weaker LVCMOS driver.  
Though some of the recommended components of Figure 1B might  
not be used, the pads should be placed in the layout so that they can  
be utilized for debugging purposes. The datasheet specifications are  
characterized and guaranteed by using a differential signal.  
cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V.  
Figure 1B shows a way to attenuate the PCLK input level by a factor  
of two as well as matching the transmission line between the  
LVCMOS driver and the IDT8SLVP1212I at both the source and the  
Figure 1B. Alternative DC Coupling a Single LVCMOS Input to the IDT8SLVP1212I  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
11  
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
Recommendations for Unused Input and Output Pins  
Inputs:  
Outputs:  
PCLKx/nPCLKx Inputs  
LVPECL Outputs  
For applications not requiring the use of a differential input, both the  
PCLKx and nPCLKx pins can be left floating. Though not required,  
but for additional protection, a 1kresistor can be tied from PCLKx  
to ground. For applications  
All unused LVPECL outputs can be left floating. We recommend that  
there is no trace attached. Both sides of the differential output pair  
should either be left floating or terminated.  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
12  
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
3.3V LVPECL Clock Input Interface  
The PCLK /nPCLK accepts LVPECL, LVDS, CML and other  
differential signals. Both differential outputs must meet the VPP and  
The input interfaces suggested here are examples only. If the driver  
is from another vendor, use their termination recommendation.  
Please consult with the vendor of the driver component to confirm the  
driver termination requirements.  
VCMR input requirements. Figures 2A to 2E show interface examples  
for the PCLK/ nPCLK input driven by the most common driver types.  
3.3V  
3.3V  
3.3V  
3.3V  
o
o
= 50Ω  
= 50Ω  
3.3V  
PCLK  
PCLK  
R1  
100Ω  
nPCLK  
nPCLK  
LVPECL  
Input  
LVPECL  
Input  
CML  
CML Built-In Pullup  
Figure 2A. PCLK/nPCLK Input Driven by a CML Driver  
Figure 2B. PCLK/nPCLK Input Driven by a  
Built-In Pullup CML Driver  
3.3V  
3.3V  
3.3V  
R3  
R4  
125Ω  
125Ω  
o = 50Ω  
o = 50Ω  
PCLK  
nPCLK  
LVPECL  
Input  
LVPECL  
R1  
R2  
84Ω  
84Ω  
Figure 2C. PCLK/nPCLK Input Driven by a  
3.3V LVPECL Driver  
Figure 2D. PCLK/nPCLK Input Driven by a  
3.3V LVPECL Driver with AC Couple  
R
E
Figure 2E. PCLK/nPCLK Input Driven by a  
3.3V LVDS Driver  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
13  
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
2.5V LVPECL Clock Input Interface  
The PCLK /nPCLK accepts LVPECL, LVDS, CML and other  
differential signals. Both differential outputs must meet the VPP and  
The input interfaces suggested here are examples only. If the driver  
is from another vendor, use their termination recommendation.  
Please consult with the vendor of the driver component to confirm the  
driver termination requirements.  
VCMR input requirements. Figures 3A to 3E show interface examples  
for the PCLK/ nPCLK input driven by the most common driver types.  
2.5V  
2.5V  
2.5V  
2.5V  
2.5V  
PCLK  
PCLK  
nPCLK  
nPCLK  
LVPECL  
CML Built-In Pullup  
LVPECL  
CML  
Input  
Input  
Figure 3A. PCLK/nPCLK Input Driven by a CML Driver  
Figure 3B. PCLK/nPCLK Input Driven by a  
Built-In Pullup CML Driver  
2.5V  
2.5V  
2.5V  
PCLK  
nPCLK  
LVPECL  
Input  
LVPECL  
Figure 3C. PCLK/nPCLK Input Driven by a  
2.5V LVPECL Driver  
Figure 3D. PCLK/nPCLK Input Driven by a  
2.5V LVPECL Driver with AC Couple  
PCLK  
nPCLK  
Figure 3E. PCLK/nPCLK Input Driven by a  
2.5V LVDS Driver  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
14  
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 4. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally/  
Electrically Enhance Leadframe Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
SOLDER  
SOLDER  
PIN  
PIN  
EXPOSED HEAT SLUG  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
15  
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
Termination for 3.3V LVPECL Outputs  
The clock layout topology shown below is a typical termination for  
LVPECL outputs. The two different layouts mentioned are  
recommended only as guidelines.  
transmission lines. Matched impedance techniques should be used  
to maximize operating frequency and minimize signal distortion.  
Figures 5A and 5B show two different layouts which are  
recommended only as guidelines. Other suitable clock layouts may  
exist and it would be recommended that the board designers  
simulate to guarantee compatibility across all printed circuit and clock  
component process variations.  
The differential outputs are a low impedance follower output that  
generate ECL/LVPECL compatible outputs. Therefore, terminating  
resistors (DC current path to ground) or current sources must be  
used for functionality. These outputs are designed to drive 50  
3.3V  
R3  
R4  
125  
125  
3.3V  
3.3V  
o = 50  
+
_
LVPECL  
Input  
o = 50  
R1  
84  
R2  
84  
Figure 5A. 3.3V LVPECL Output Termination  
Figure 5B. 3.3V LVPECL Output Termination  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
16  
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
Termination for 2.5V LVPECL Outputs  
Figure 6A and Figure 6B show examples of termination for 2.5V  
LVPECL driver.These terminations are equivalent to terminating 50  
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground  
level. The R3 in Figure 6B can be eliminated and the termination is  
shown in Figure 6C.  
2.5V  
VCC = 2.5V  
2.5V  
2.5V  
VCC = 2.5V  
R1  
R3  
50Ω  
250Ω  
250Ω  
+
50Ω  
50Ω  
+
–
50Ω  
–
2.5V LVPECL Driver  
R1  
R2  
50Ω  
50Ω  
2.5V LVPECL Driver  
R2  
R4  
62.5Ω  
62.5Ω  
R3  
18Ω  
Figure 6A. 2.5V LVPECL Driver Termination Example  
Figure 6B. 2.5V LVPECL Driver Termination Example  
2.5V  
VCC = 2.5V  
50Ω  
+
50Ω  
–
2.5V LVPECL Driver  
R1  
R2  
50Ω  
50Ω  
Figure 6C. 2.5V LVPECL Driver Termination Example  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
17  
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
Power Considerations  
This section provides information on power dissipation and junction temperature for the IDT8SLVP1212I.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the IDT8SLVP1212I is the sum of the core power plus the power dissipation in the load(s).  
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.  
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 131mA = 453.9mW  
Power (outputs)MAX = 35.2mW/Loaded Output pair  
If all outputs are loaded, the total power is 12 * 35.2mW = 422.4mW  
Total Power_MAX (3.465V, with all outputs switching) = 453.9mW + 422.4mW = 876.3mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 38.1°C/W per Table 6 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.876W * 38.1°C/W = 118.4°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 6. Thermal Resistance for a 40-Lead VFQFN  
JA  
JA at 0 Air Flow  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
38.1°C/W  
32.0°C/W  
29.9°C/W  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
18  
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
3. Calculations and Equations.  
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.  
The LVPECL output driver circuit and termination are shown in Figure 7.  
VCC  
Q1  
VOUT  
RL  
VCC - 2V  
Figure 7. LVPECL Driver Circuit and Termination  
To calculate power dissipation per output pair due to loading, use the following equations which assume a 50load,  
and a termination voltage of VCC – 2V.  
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.6V  
(VCC_MAX – VOH_MAX) = 0.6V  
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.28V  
(VCC_MAX – VOL_MAX) = 1.28V  
Pd_H is power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V - (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =  
[(2V – 0.6V)/50] * 0.6V = 16.8mW  
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =  
[(2V – 1.28V)/50] * 1.28V = 18.4mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 35.2mW  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
19  
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
Reliability Information  
Table 7. vs. Air Flow Table for a 40-Lead VFQFN  
JA  
JA at 0 Air Flow  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
38.1°C/W  
32.0°C/W  
29.9°C/W  
Transistor Count  
The transistor count for the IDT8SLVP1212I is: 7748  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
20  
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
40-Lead VFQFN Package Outline and Package Dimensions  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
21  
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
40-Lead VFQFN Package Outline and Package Dimensions, continued  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
22  
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
Ordering Information  
Table 8. Ordering Information  
Part/Order Number  
8SLVP1212ANLGI  
Marking  
IDT8SLVP1212ANLGI  
Package  
“Lead-Free” 40-Lead VFQFN  
Shipping Packaging  
Tray  
Temperature  
-40°C to 85°C  
Tape & Reel,  
pin 1 orientation: EIA-481-C  
Tape & Reel,  
pin 1 orientation: EIA-481-D  
8SLVP1212ANLGI8  
IDT8SLVP1212ANLGI  
“Lead-Free” 40-Lead VFQFN  
“Lead-Free” 40-Lead VFQFN  
-40°C to 85°C  
-40°C to 85°C  
8SLVP1212ANLGI/W IDT8SLVP1212ANLGI  
Table 9. Pin 1 Orientation in Tape and Reel Packaging  
Part Number Suffix  
Pin 1 Orientation  
Illustration  
8
Quadrant 1 (EIA-481-C)  
/W  
Quadrant 2 (EIA-481-D)  
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
23  
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
Revision History Sheet  
Rev  
Table  
Page  
Description of Change  
Date  
Added Features Bullet: Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs  
can also accept single-ended LVCMOS levels.  
Added NOTE 7 to VPP, VCMR.  
1
1/30/2013  
1/28/2014  
A
T5  
T5  
5, 6  
11  
Updated the “Wiring the Differential Input to Accept Single-Ended Levels” note.  
Changed Note 5 to read “VIL should not be less than -0.3V. VIH should not be  
higher than VCC.”  
A
6
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014  
24  
©2014 Integrated Device Technology, Inc.  
IDT8SLVP1212I Data Sheet  
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER  
We’ve Got Your Timing Solution  
6024 Silver Creek Valley Road Sales  
Technical Support Sales  
800-345-7015 (inside USA)  
netcom@idt.com  
San Jose, California 95138  
+408-284-8200 (outside USA) +480-763-2056  
Fax: 408-284-2775  
www.IDT.com/go/contactIDT  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,  
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not  
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the  
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any  
license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi-  
cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third  
party owners.  
Copyright 2014. All rights reserved.  
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