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8SLVP1204ANLGI

型号：

8SLVP1204ANLGI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

24 页

PDF大小：

580 K

下载PDF手册
Low Phase Noise, 2:4, 3.3V, 2.5V  
LVPECL Output Fanout Buffer  
8SLVP1204  
DATASHEET  
Description  
Features  
The 8SLVP1204 is a high-performance differential LVPECL fanout  
buffer. The device is designed for the fanout of high-frequency, very  
low additive phase-noise clock and data signals. The 8SLVP1204 is  
characterized to operate from a 3.3V or 2.5V power supply.  
• Four low skew, low additive jitter LVPECL output pairs  
• Two selectable, differential clock input pairs  
• Differential PCLKx pairs can accept the following differential input  
levels: LVDS, LVPECL, CML  
Guaranteed output-to-output and part-to-part skew characteristics  
make the 8SLVP1204 ideal for clock distribution applications that  
demand well-defined performance and repeatability. Two selectable  
differential inputs and four low skew outputs are available. The  
integrated bias voltage reference enables easy interfacing of  
single-ended signals to the device inputs. The device is optimized for  
low power consumption and low additive phase noise.  
• Differential PCLKx pairs can also accept single-ended LVCMOS  
levels. See Applications Information, “Wiring the Differential Input  
to Accept Single-Ended Levels” (Figures 1A and 1B)  
• Maximum input clock frequency: 2GHz  
• LVCMOS interface levels for the control input, (input select)  
• Output skew: 5ps (typical), at 3.63V  
• Propagation delay: 200ps (typical), at 3.63V  
• Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,  
12kHz - 20MHz: 40fs (maximum), at 3.63V  
• Maximum device current consumption (IEE): 60mA (maximum),  
at 3.63V  
• Full 3.3V±5%, 3.3V±10% or 2.5V±5% supply  
• Lead-free (RoHS 6), 16-Lead VFQFPN packaging  
• -40°C to 85°C ambient operating temperature  
• Supports case temperature 105°C operations  
Block Diagram  
Pin Assignment  
V
CC  
16 15 14 13  
1
2
3
VEE  
SEL  
12  
11  
10  
nQ1  
Q1  
Pulldown  
Q0  
nQ0  
PCLK0  
Pullup/Pulldown  
nPCLK0  
PCLK1  
nPCLK1  
nQ0  
Q0  
Q1  
nQ1  
0
1
fREF  
4
9
5
6
7
8
Q2  
V
CC  
nQ2  
Pulldown  
PCLK1  
Q3  
Pullup/Pulldown  
nPCLK1  
nQ3  
8SLVP1204  
16-Lead, 3mm x 3mm VFQFPN Package  
Pulldown  
SEL  
Voltage  
Reference  
VREF  
IDT8SLVP1204 SEPTEMBER 13, 2018  
1
©2018 Integrated Device Technology, Inc.  
8SLVP1204 DATASHEET  
Pin Descriptions and Characteristics  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
1
VEE  
Power  
Input  
Input  
Input  
Negative supply pin.  
Reference select control pin. See Table 3 for function. LVCMOS/LVTTL interface  
levels.  
2
3
4
SEL  
Pulldown  
PCLK1  
nPCLK1  
Pulldown  
Non-inverting differential LVPECL clock/data input.  
Pullup/  
Pulldown  
Inverting differential LVPECL clock/data input. VCC/2 default when left floating.  
5
6
VCC  
Power  
Input  
Power supply pins.  
PCLK0  
Pulldown  
Non-inverting differential LVPECL clock/data input.  
Pullup/  
Pulldown  
7
nPCLK0  
Input  
Inverting differential LVPECL clock/data input. VCC/2 default when left floating.  
8
VREF  
Output  
Output  
Output  
Output  
Output  
Bias voltage reference for the PCLK inputs.  
9, 10  
11, 12  
13, 14  
15, 16  
Q0, nQ0  
Q1, nQ1  
Q2, nQ2  
Q3, nQ3  
Differential output pair 0. LVPECL interface levels.  
Differential output pair 1. LVPECL interface levels.  
Differential output pair 2. LVPECL interface levels.  
Differential output pair 3. LVPECL interface levels.  
NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
pF  
Input Capacitance  
Input Pulldown Resistor  
Input Pullup Resistor  
2
RPULLDOWN  
RPULLUP  
51  
51  
k  
k  
Function Table  
Table 3. SEL Input Selection Function Table  
Input  
SEL  
0 (default)  
1
Operation  
PCLK0, nPCLK0 is the selected differential clock input.  
PCLK1, nPCLK1 is the selected differential clock input.  
NOTE: SEL is an asynchronous control.  
IDT8SLVP1204 SEPTEMBER 13, 2018  
2
©2018 Integrated Device Technology, Inc.  
 
8SLVP1204 DATASHEET  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress  
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or  
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VCC  
Inputs, VI  
4.6V  
-0.5V to VCC + 0.5V  
Outputs, IO (LVPECL)  
Continuous Current  
Surge Current  
50mA  
100mA  
Input Sink/Source, IREF  
±2mA  
Maximum Junction Temperature, TJ,MAX  
Storage Temperature, TSTG  
125°C  
-65°C to 150°C  
2000V  
ESD - Human Body Model, NOTE 1  
ESD - Charged Device Model, NOTE 1  
1500V  
NOTE 1: According to JEDEC/JESD 22-A114/22-C101.  
DC Electrical Characteristics  
Table 4A. Power Supply DC Characteristics, V = 3.3V ±10%, V = 0V, T = -40°C to 85°C  
CC  
EE  
A
Symbol Parameter  
VCC Power Supply Voltage  
IEE  
Test Conditions  
Minimum  
Typical  
3.3V  
53  
Maximum  
3.63  
Units  
V
2.97  
Power Supply Current  
Power Supply Current  
60  
mA  
mA  
ICC  
Q0 to Q3 terminated 50to VCC – 2V  
170  
204  
Table 4B. Power Supply DC Characteristics, V = 3.3V ±5%, V = 0V, T = -40°C to 85°C  
CC  
EE  
A
Symbol Parameter  
VCC Power Supply Voltage  
IEE  
Test Conditions  
Minimum  
3.135  
Typical  
3.3V  
53  
Maximum  
3.465  
60  
Units  
V
Power Supply Current  
Power Supply Current  
mA  
mA  
ICC  
Q0 to Q3 terminated 50to VCC – 2V  
170  
204  
Table 4C. Power Supply DC Characteristics, VCC = 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C  
Symbol Parameter  
VCC Power Supply Voltage  
IEE  
Test Conditions  
Minimum  
Typical  
2.5V  
49  
Maximum  
2.625  
55  
Units  
V
2.375  
Power Supply Current  
Power Supply Current  
mA  
mA  
ICC  
Q0 to Q3 terminated 50to VCC – 2V  
170  
199  
IDT8SLVP1204 SEPTEMBER 13, 2018  
3
©2018 Integrated Device Technology, Inc.  
8SLVP1204 DATASHEET  
Table 4D. LVCMOS/LVTTL DC Characteristics, V = 3.3V ±10%, V = 0V, T = -40°C to 85°C  
CC  
EE  
A
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
VCC + 0.3  
VCC + 0.3  
0.8  
Units  
V
V
CC = 3.63V  
VCC = 2.625V  
CC = 3.63V  
VCC = 2.625V  
2.2  
1.7  
VIH Input High Voltage  
V
V
-0.3  
-0.3  
V
VIL  
Input Low Voltage  
0.7  
V
IIH  
IIL  
Input High Current  
Input Low Current  
SEL  
SEL  
VCC = VIN = 3.465V or 2.625V  
150  
µA  
µA  
VCC = 3.465V or 2.625V, VIN = 0V  
-10  
Table 4E. LVCMOS/LVTTL DC Characteristics, V = 3.3V ±5% or 2.5V ±5%, V = 0V, T = -40°C to 85°C  
CC  
EE  
A
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
VCC + 0.3  
VCC + 0.3  
0.8  
Units  
V
VCC = 3.465V  
2.2  
1.7  
VIH Input High Voltage  
VCC = 2.625V  
VCC = 3.465V  
V
-0.3  
-0.3  
V
VIL  
Input Low Voltage  
VCC = 2.625V  
0.7  
V
IIH  
IIL  
Input High Current  
Input Low Current  
SEL  
SEL  
VCC = VIN = 3.465V or 2.625V  
VCC = 3.465V or 2.625V, VIN = 0V  
150  
µA  
µA  
-10  
IDT8SLVP1204 SEPTEMBER 13, 2018  
4
©2018 Integrated Device Technology, Inc.  
8SLVP1204 DATASHEET  
Table 4F. LVPECL DC Characteristics, V = 3.3V ±10%, V = 0V, T = -40°C to 85°C  
CC  
EE  
A
Symbol Parameter  
IIH Input High Current  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
PCLK0, nPCLK0  
PCLK1, nPCLK1  
VCC = VIN = 3.63V  
150  
µA  
PCLK0, PCLK1  
VCC = 3.63V, VIN = 0V  
VCC = 3.63V, VIN = 0V  
IREF = ±1mA  
-10  
µA  
µA  
V
IIL  
Input Low Current  
nPCLK0, nPCLK1  
-150  
VREF  
VOH  
VOL  
Reference Voltage for Input Bias  
Output High Voltage1  
VCC – 1.6  
VCC – 1.1  
VCC – 2.0  
VCC – 1.3  
VCC – 0.9  
VCC – 1.65  
VCC – 1.1  
VCC – 0.7  
VCC – 1.5  
V
Output Low Voltage1  
V
NOTE 1. Outputs terminated with 50to VCC – 2V.  
Table 4G. LVPECL DC Characteristics, V = 3.3V ±5%, V = 0V, T = -40°C to 85°C  
CC  
EE  
A
Symbol Parameter  
IIH Input High Current  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
PCLK0, nPCLK0  
PCLK1, nPCLK1  
VCC = VIN = 3.465V  
150  
µA  
PCLK0, PCLK1  
V
CC = 3.465V, VIN = 0V  
-10  
µA  
µA  
V
IIL  
Input Low Current  
nPCLK0, nPCLK1  
VCC = 3.465V, VIN = 0V  
IREF = ±1mA  
-150  
VREF  
VOH  
VOL  
Reference Voltage for Input Bias  
Output High Voltage1  
VCC – 1.6  
VCC – 1.1  
VCC – 2.0  
VCC – 1.3  
VCC – 0.9  
VCC – 1.65  
VCC – 1.1  
VCC – 0.7  
VCC – 1.5  
V
Output Low Voltage1  
V
NOTE 1. Outputs terminated with 50to VCC – 2V.  
Table 4H. LVPECL DC Characteristics, V = 2.5V ±5%, V = 0V, T = -40°C to 85°C  
CC  
EE  
A
Symbol Parameter  
IIH Input High Current  
Test Conditions  
VCC = VIN = 2.625V  
CC = 2.625V, VIN = 0V  
Minimum  
Typical  
Maximum  
Units  
PCLK0, nPCLK0  
PCLK1, nPCLK1  
150  
µA  
PCLK0, PCLK1  
V
-10  
µA  
µA  
V
IIL  
Input Low Current  
nPCLK0, nPCLK1  
VCC = 2.625V, VIN = 0V  
IREF = ±1mA  
-150  
VREF  
VOH  
VOL  
Reference Voltage for Input Bias  
Output High Voltage1  
VCC – 1.6  
VCC – 1.1  
VCC – 2.0  
VCC – 1.3  
VCC – 0.9  
VCC – 1.6  
VCC – 1.1  
VCC – 0.7  
VCC – 1.5  
V
Output Low Voltage1  
V
NOTE 1. Outputs terminated with 50to VCC – 2V.  
IDT8SLVP1204 SEPTEMBER 13, 2018  
5
©2018 Integrated Device Technology, Inc.  
8SLVP1204 DATASHEET  
AC Electrical Characteristics  
Table 5A. AC Electrical Characteristics, VCC = 3.3V ± 5% or 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C1  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Input  
PCLK[0:1],  
fREF  
2
GHz  
Frequency nPCLK[0:1]  
Input PCLK[0:1],  
V/t  
1.5  
V/ns  
ps  
Edge Rate nPCLK[0:1]  
Propagation Delay2  
PCKx, nPCLKx to any Qx, nQx  
for VPP = 0.1V or 0.3V  
tPD  
120  
200  
320  
tsk(o)  
tsk(i)  
Output Skew3 4  
Input Skew4  
5
5
25  
50  
ps  
ps  
ps  
ps  
tsk(p)  
tsk(pp)  
Pulse Skew  
Part-to-Part Skew4 5  
fREF = 100MHz  
5
20  
100  
200  
fREF = 122.88MHz Sine Wave, VPP = 1V,  
Integration Range: 1kHz – 40MHz  
170  
114  
114  
fs  
fs  
fs  
fREF = 122.88MHz Sine Wave, VPP = 1V,  
Integration Range: 10kHz – 20MHz  
fREF = 122.88MHz Sine Wave, VPP = 1V,  
Integration Range: 12kHz – 20MHz  
fREF = 156.25MHz Square Wave,  
VPP = 1V, Integration Range:  
1kHz – 40MHz  
42  
32  
32  
51  
38  
38  
51  
40  
40  
71  
52  
fs  
fs  
fs  
fs  
fs  
fs  
fREF = 156.25MHz Square Wave,  
VPP = 1V, Integration Range:  
10kHz – 20MHz  
Buffer Additive Phase  
Jitter, RMS; refer to  
Additive Phase Jitter  
Section  
tJIT  
fREF = 156.25MHz Square Wave,  
VPP = 1V, Integration Range:  
12kHz – 20MHz  
f
REF = 156.25MHz Square Wave,  
VPP = 0.5V, Integration Range:  
1kHz – 40MHz  
fREF = 156.25MHz Square Wave,  
VPP = 0.5V, Integration Range:  
10kHz – 20MHz  
fREF = 156.25MHz Square Wave,  
VPP = 0.5V, Integration Range:  
12kHz – 20MHz  
52  
tR / tF  
Output Rise/ Fall Time  
20% to 80%  
fREF = 100MHz  
fREF < 1.5 GHz  
fREF > 1.5 GHz  
35  
90  
77  
180  
ps  
dB  
V
MUXISOLATION Mux Isolation6  
0.1  
0.2  
1.0  
0.8  
0.45  
0.4  
0.9  
1.5  
1.5  
Peak-to-Peak Input  
Voltage7  
VPP  
V
VCC – 0.6  
VCC – 0.6  
1.0  
V
Common Mode Input  
Voltage7 8 9  
VCMR  
VO(pp)  
VPP = > 247mV  
V
VCC = 3.3V, fREF 2GHz  
VCC = 2.5V, fREF 2GHz  
VCC = 3.3V, fREF 2GHz  
0.75  
0.65  
1.5  
V
Output Voltage Swing,  
Peak-to-Peak  
1.0  
V
Differential Output  
Voltage Swing,  
Peak-to-Peak  
2.0  
V
VDIFF_OUT  
V
CC = 2.5V, fREF 2GHz  
0.8  
1.3  
2.0  
V
IDT8SLVP1204 SEPTEMBER 13, 2018  
6
©2018 Integrated Device Technology, Inc.  
8SLVP1204 DATASHEET  
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the  
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications  
after thermal equilibrium has been reached under these conditions.  
NOTE 2. Measured from the differential input crossing point to the differential output crosspoint.  
NOTE 3. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross  
point.  
NOTE 4. This parameter is defined in accordance with JEDEC Standard 65.  
NOTE 5. Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature  
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross  
point.  
NOTE 6. Qx, nQx outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information section.  
NOTE 7. For single-ended LVCMOS input applications, refer to the Applications section Wiring the Differential Input Levels to Accept Sin-  
gle-ended Levels (Figures 1 and 2).  
NOTE 8. VIL should not be less than -0.3V. VIH should not be higher than VCC  
NOTE 9. Common mode input voltage is defined as the crosspoint.  
.
1
Table 5B. AC Electrical Characteristics, V = 3.3V ±10%, V = 0V, T = -40°C to 85°C  
CC  
EE  
A
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum Units  
Input  
PCLK[0:1],  
fREF  
2
GHz  
V/ns  
ps  
Frequency nPCLK[0:1]  
Input2  
PCLK[0:1],  
V/t  
1.5  
Edge Rate nPCLK[0:1]  
PCKx, nPCLKx to any Qx, nQx  
for VPP = 0.1V or 0.3V  
tPD  
Propagation Delay3  
120  
230  
325  
tsk(o)  
tsk(i)  
Output Skew4 5  
Input Skew4  
6
6
7
30  
55  
ps  
ps  
ps  
ps  
ps  
dB  
V
tsk(p)  
tsk(pp)  
tR / tF  
Pulse Skew  
Part-to-Part Skew4 6  
fREF = 100MHz  
25  
200  
200  
Output Rise/ Fall Time  
20% to 80%  
fREF = 100MHz  
fREF < 1.5 GHz  
fREF > 1.5 GHz  
35  
MUXISOLATION Mux Isolation7  
77  
0.1  
0.2  
1.0  
0.8  
0.45  
0.4  
0.9  
1.5  
1.5  
Peak-to-Peak Input  
Voltage8  
VPP  
V
VCC – 0.6  
VCC – 0.6  
1.0  
V
Common Mode Input  
Voltage7 9 10  
VCMR  
VO(pp)  
VPP = > 247mV  
V
V
CC = 3.3V, fREF 2GHz  
VCC = 2.5V, fREF 2GHz  
CC = 3.3V, fREF 2GHz  
VCC = 2.5V, fREF 2GHz  
0.75  
0.65  
1.5  
V
Output Voltage Swing,  
Peak-to-Peak  
1.0  
V
Differential Output  
Voltage Swing,  
Peak-to-Peak  
V
2.0  
V
VDIFF_OUT  
0.8  
1.3  
2.0  
V
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the  
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications  
after thermal equilibrium has been reached under these conditions.  
NOTE 2. Input Edge Rate is the slope of Δv/Δt at the crosspoint of the differential pair signals. Δt is measured with ΔV = 300mV on one  
of the single-ended input pair signals.  
NOTE 3. Measured from the differential input crossing point to the differential output crosspoint.  
NOTE 4. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross  
point.  
NOTE 5. This parameter is defined in accordance with JEDEC Standard 65  
IDT8SLVP1204 SEPTEMBER 13, 2018  
7
©2018 Integrated Device Technology, Inc.  
8SLVP1204 DATASHEET  
NOTE 6. Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature  
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cros-  
spoint.  
NOTE 7. Qx, nQx outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information section.  
NOTE 8. For single-ended LVCMOS input applications, refer to the Applications section Wiring the Differential Input Levels to Accept Sin-  
gle-ended Levels (Figures 1 and 2).  
NOTE 9. VIL should not be less than -0.3V. VIH should not be higher than VCC  
NOTE 10. Common mode input voltage is defined as the crosspoint.  
.
IDT8SLVP1204 SEPTEMBER 13, 2018  
8
©2018 Integrated Device Technology, Inc.  
8SLVP1204 DATASHEET  
Additive Phase Jitter  
The spectral purity in a band at a specific offset from the fundamental  
compared to the power of the fundamental is called the dBc Phase  
Noise. This value is normally expressed using a Phase noise plot  
and is most often the specified plot in many applications. Phase noise  
is defined as the ratio of the noise power present in a 1Hz band at a  
specified offset from the fundamental frequency to the power value of  
the fundamental. This ratio is expressed in decibels (dBm) or a ratio  
of the power in the 1Hz band to the power in the fundamental. When  
the required offset is specified, the phase noise is called a dBc value,  
which simply means dBm at a specified offset from the fundamental.  
By investigating jitter in the frequency domain, we get a better  
understanding of its effects on the desired application over the entire  
time record of the signal. It is mathematically possible to calculate an  
expected bit error rate given a phase noise plot.  
Offset from Carrier Frequency (Hz)  
As with most timing specifications, phase noise measurements has  
issues relating to the limitations of the equipment. Often the noise  
floor of the equipment is higher than the noise floor of the device. This  
is illustrated above. The device meets the noise floor of what is  
shown, but can actually be lower. The phase noise is dependent on  
the input source and measurement equipment.  
Measured using a Wenzel 156.25MHz Oscillator as the input source.  
IDT8SLVP1204 SEPTEMBER 13, 2018  
9
©2018 Integrated Device Technology, Inc.  
8SLVP1204 DATASHEET  
Parameter Measurement Information  
2V  
2V  
SCOPE  
SCOPE  
V
V
CC  
Qx  
Qx  
CC  
nQx  
nQx  
VEE  
VEE  
-1.3V±0.165V  
-1.3V±0.33V  
3.3V ±10% LVPECL Output Load Test Circuit  
3.3V ±5% LVPECL Output Load Test Circuit  
2V  
V
CC  
SCOPE  
V
CC  
Qx  
nPCLK[0:1]  
PCLK[0:1]  
nQx  
VEE  
V
EE  
-0.5V±0.125V  
2.5V LVPECL Output Load Test Circuit  
Differential Input Level  
nPCLK[0:1]  
PCLK[0:1]  
Part 1  
nQx  
Qx  
nQy  
Qy  
Part 2  
nQy  
tPLH  
tPHL  
Qy  
tsk(pp)  
tsk(p)= |tPHL - tPLH  
|
Part-to-Part Skew  
Pulse Skew  
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Parameter Measurement Information, continued  
nPCLK0  
Spectrum of Output Signal Q  
PCLK0  
MUX selects active  
input clock signal  
A0  
nPCLK1  
PCLK1  
MUX_ISOLATION = A0 – A1  
nQ[0:3]  
MUX selects other input  
A1  
Q[0:3]  
tPD2  
tPD1  
ƒ
Frequency  
tsk(i)  
(fundamental)  
tsk(i) = |tPD1 - tPD2  
|
Input Skew  
MUX Isolation  
nQx  
Qx  
nPCLK[0:1]  
PCLK[0:1]  
nQ[0:3]  
Q[0:3]  
nQy  
Qy  
tPD  
Output Skew  
Propagation Delay  
nQ[0:3]  
80%  
80%  
tR  
VO(PP)  
20%  
20%  
Q[0:3]  
tF  
Output Rise/Fall Time  
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Applications Information  
Wiring the Differential Input to Accept Single-Ended Levels  
The 8SLVP1204 inputs can be interfaced to LVPECL, LVDS, CML or  
LVCMOS drivers. Figure 1A illustrates how to DC couple a single  
LVCMOS input to the 8SLVP1204. The value of the series resistance  
RS is calculated as the difference between the transmission line  
impedance and the driver output impedance. This resistor should be  
placed close to the LVCMOS driver. To avoid cross-coupling of  
single-ended LVCMOS signals, apply the LVCMOS signals to no  
more than one PCLK input.  
A practical method to implement Vth is shown in Figure 1B below.  
The reference voltage Vth = V1 = VCC/2, is generated by the bias  
resistors R1 and R2. The bypass capacitor (C1) is used to help filter  
noise on the DC bias. This bias circuit should be located as close to  
the input pin as possible.  
The ratio of R1 and R2 might need to be adjusted to position the V1  
in the center of the input voltage swing. For example, if the input clock  
swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted  
to set V1 at 1.25V. The values below apply when both the  
single-ended swing and VCC are at the same voltage.  
Figure 1A. DC-Coupling a Single LVCMOS Input to the  
8SLVP1204  
When using single-ended signaling, the noise rejection benefits of  
differential signaling are reduced. Even though the differential input  
can handle full rail LVCMOS signaling, it is recommended that the  
amplitude be reduced, particularly if both input references are  
LVCMOS to minimize cross talk. The datasheet specifies a lower  
differential amplitude, however this only applies to differential signals.  
For single-ended applications, the swing can be larger, however VIL  
This configuration requires that the sum of the output impedance of  
the driver (Ro) and the series resistance (Rs) equals the transmission  
line impedance. R3 and R4 in parallel should equal the transmission  
line impedance; for most 50applications, R3 and R4 will be 100.  
The values of the resistors can be increased to reduce the loading for  
slower and weaker LVCMOS driver.  
Though some of the recommended components of Figure 1B might  
not be used, the pads should be placed in the layout so that they can  
be utilized for debugging purposes. The datasheet specifications are  
characterized and guaranteed by using a differential signal.  
cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V.  
Figure 1B shows a way to attenuate the PCLK input level by a factor  
of two as well as matching the transmission line between the  
LVCMOS driver and the 8SLVP1204 at both the source and the load.  
VC C  
VC C  
VCC  
VCC  
R3  
100  
R1  
1K  
Ro  
RS  
Zo = 50 Ohm  
+
Receiv er  
Driver  
V1  
R4  
-
100  
R2  
1K  
Ro +Rs = Zo  
C1  
0.1uF  
Figure 1B. Alternative DC Coupling a Single LVCMOS Input to the 8SLVP1204  
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3.3V LVPECL Clock Input Interface  
The PCLK /nPCLK accepts LVPECL, LVDS, CML and other  
differential signals. Both signals must meet the VPP and VCMR input  
requirements. Figures 2A to 2E show interface examples for the  
PCLK/ nPCLK input driven by the most common driver types. The  
input interfaces suggested here are examples only. If the driver is  
from another vendor, use their termination recommendation. Please  
consult with the vendor of the driver component to confirm the driver  
termination requirements.  
3.3V  
3.3V  
3.3V  
3.3V  
Zo = 50Ω  
3.3V  
PCLK  
PCLK  
R1  
100Ω  
nPCLK  
Zo = 50Ω  
nPCLK  
LVPECL  
LVPECL  
Input  
CML  
CML Built-In Pullup  
Input  
Figure 2A. PCLK/nPCLK Input Driven by a CML Driver  
Figure 2B. PCLK/nPCLK Input Driven by a  
Built-In Pullup CML Driver  
3.3V  
3.3V  
3.3V  
R3  
R4  
125Ω  
125Ω  
Zo = 50Ω  
Zo = 50Ω  
PCLK  
nPCLK  
LVPECL  
Input  
LVPECL  
R1  
R2  
84Ω  
84Ω  
Figure 2C. PCLK/nPCLK Input Driven by a  
3.3V LVPECL Driver  
Figure 2D. PCLK/nPCLK Input Driven by a  
3.3V LVPECL Driver with AC Couple  
3.3V  
3.3V  
Zo = 50฀  
PCLK  
R1  
100฀  
nPCLK  
Zo = 50฀  
LVPECL  
Input  
LVDS  
Figure 2E. PCLK/nPCLK Input Driven by a  
3.3V LVDS Driver  
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2.5V LVPECL Clock Input Interface  
The PCLK /nPCLK accepts LVPECL, LVDS, CML and other  
differential signals. Both signals must meet the VPP and VCMR input  
requirements. Figures 3A to 3E show interface examples for the  
PCLK/ nPCLK input driven by the most common driver types. The  
input interfaces suggested here are examples only. If the driver is  
from another vendor, use their termination recommendation. Please  
consult with the vendor of the driver component to confirm the driver  
termination requirements.  
2.5V  
2.5V  
2.5V  
2.5V  
2.5V  
PCLK  
PCLK  
nPCLK  
nPCLK  
LVPECL  
CML Built-In Pullup  
LVPECL  
Input  
CML  
Input  
Figure 3A. PCLK/nPCLK Input Driven by a CML Driver  
Figure 3B. PCLK/nPCLK Input Driven by a  
Built-In Pullup CML Driver  
2.5V  
2.5V  
2.5V  
PCLK  
nPCLK  
LVPECL  
Input  
LVPECL  
Figure 3C. PCLK/nPCLK Input Driven by a  
2.5V LVPECL Driver  
Figure 3D. PCLK/nPCLK Input Driven by a  
2.5V LVPECL Driver with AC Couple  
PCLK  
nPCLK  
Figure 3E. PCLK/nPCLK Input Driven by a  
2.5V LVDS Driver  
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Recommendations for Unused Input and Output Pins  
Inputs:  
Outputs:  
PCLK/nPCLK Inputs  
LVPECL Outputs  
For applications not requiring the use of a differential input, both the  
PCLK and nPCLK pins can be left floating. Though not required, but  
for additional protection, a 1kresistor can be tied from PCLK to  
ground.  
All unused LVPECL output pairs can be left floating. We recommend  
that there is no trace attached. Both sides of the differential output  
pair should either be left floating or terminated.  
VFQFPN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 4. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally/  
Electrically Enhance Leadframe Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
SOLDER  
SOLDER  
PIN  
PIN  
EXPOSED HEAT SLUG  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
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Termination for 3.3V LVPECL Outputs  
The clock layout topology shown below is a typical termination for  
LVPECL outputs. The two different layouts mentioned are  
recommended only as guidelines.  
transmission lines. Matched impedance techniques should be used  
to maximize operating frequency and minimize signal distortion.  
Figures 5A and 5B show two different layouts which are  
recommended only as guidelines. Other suitable clock layouts may  
exist and it would be recommended that the board designers  
simulate to guarantee compatibility across all printed circuit and clock  
component process variations.  
The differential outputs are a low impedance follower output that  
generate ECL/LVPECL compatible outputs. Therefore, terminating  
resistors (DC current path to ground) or current sources must be  
used for functionality. These outputs are designed to drive 50  
3.3V  
R3  
R4  
125฀  
125฀  
3.3V  
3.3V  
Zo = 50฀  
Zo = 50฀  
+
_
Input  
R1  
84฀  
R2  
84฀  
Figure 5A. 3.3V LVPECL Output Termination  
Figure 5B. 3.3V LVPECL Output Termination  
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Termination for 2.5V LVPECL Outputs  
Figure 6A and Figure 6B show examples of termination for 2.5V  
LVPECLdriver. These terminations are equivalent to terminating 50  
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground  
level. The R3 in Figure 6B can be eliminated and the termination is  
shown in Figure 6C.  
2.5V  
VCC = 2.5V  
2.5V  
2.5V  
VCC = 2.5V  
50Ω  
R1  
R3  
250Ω  
250Ω  
+
50Ω  
50Ω  
+
–
50Ω  
–
2.5V LVPECL Driver  
R1  
R2  
50Ω  
50Ω  
2.5V LVPECL Driver  
R2  
R4  
62.5Ω  
62.5Ω  
R3  
18Ω  
Figure 6A. 2.5V LVPECL Driver Termination Example  
Figure 6B. 2.5V LVPECL Driver Termination Example  
2.5V  
VCC = 2.5V  
50Ω  
+
50Ω  
–
2.5V LVPECL Driver  
R1  
R2  
50Ω  
50Ω  
Figure 6C. 2.5V LVPECL Driver Termination Example  
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3.3V ±10% Power Considerations  
This section provides information on power dissipation and junction temperature for the 8SLVP1204.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the 8SLVP1204 is the sum of the core power plus the power dissipated due to loading.  
The following is the power dissipation for VCC = 3.63V.  
NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.  
The maximum current at 85° is as follows:  
IEE_MAX = 65mA  
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 60mA = 217.80mW  
Power (outputs)MAX = 33.2mW/Loaded Output pair  
If all outputs are loaded, the total power is 4 * 33.2mW = 132.8mW  
Total Power_MAX (3.63V, with all outputs switching) = 217.80mW + 132.8mW = 350.60mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 74.7°C/W per Table 6 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.351W * 74.7°C/W = 111.2°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 6. Thermal Resistance for 16-Lead VFQFPN, Forced Convection  
JA  
JA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
74.7°C/W  
65.3°C/W  
58.5°C/W  
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3. Calculations and Equations.  
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.  
LVPECL output driver circuit and termination are shown in Figure 7.  
VCC  
Q1  
VOUT  
RL  
VCC - 2V  
Figure 7. LVPECL Driver Circuit and Termination  
To calculate power dissipation due to loading, use the following equations which assume a 50load, and a termination voltage of VCC – 2V.  
These are typical calculations.  
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.7V  
(VCC_MAX – VOH_MAX) = 0.7V  
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.5V  
(VCC_MAX – VOL_MAX) = 1.5V  
Pd_H is power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =  
[(2V – 0.7V)/50] * 0.7V = 18.2mW  
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =  
[(2V – 1.5V)/50] * 1.5V = 15mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 33.2mW  
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Case Temperature Considerations  
This device supports applications in a natural convection environment which does not have any thermal conductivity through ambient air. The  
printed circuit board (PCB) is typically in a sealed enclosure without any natural or forced air flow and is kept at or below a specific temperature.  
The device package design incorporates an exposed pad (ePad) with enhanced thermal parameters which is soldered to the PCB where most  
of the heat escapes from the bottom exposed pad. For this type of application, it is recommended to use the junction-to-board thermal  
characterization parameter JB (Psi-JB) to calculate the junction temperature (TJ) and ensure it does not exceed the maximum allowed  
junction temperature in the Absolute Maximum Rating table.  
The junction-to-board thermal characterization parameter, JB, is calculated using the following equation:  
TJ = TCB + JB x Pd, Where  
TJ = Junction temperature at steady state condition in (oC).  
TCB = Case temperature (Bottom) at steady state condition in (oC).  
JB = Thermal characterization parameter to report the difference between junction temperature and the temperature of the board  
measured at the top surface of the board.  
Pd = power dissipation (W) in desired operating configuration.  
T
J
T
CB  
The ePad provides a low thermal resistance path for heat transfer to the PCB and represents the key pathway to transfer heat away from the  
IC to the PCB. It’s critical that the connection of the exposed pad to the PCB is properly constructed to maintain the desired IC case temperature  
(TCB). A good connection ensures that temperature at the exposed pad (TCB) and the board temperature (TB) are relatively the same. An  
improper connection can lead to increased junction temperature, increased power consumption and decreased electrical performance. In  
addition, there could be long-term reliability issues and increased failure rate.  
Example Calculation for Junction Temperature (TJ): TJ = TCB + JB x Pd  
Package type:  
Body size:  
ePad size:  
Thermal Via:  
JB  
16-Lead VFQFPN  
3mm x 3mm x0.9mm  
1.7mm x 1.7mm  
2 x 2 matrix  
5.1 C/W  
105oC  
TCB  
Pd  
0.351 W  
For the variables above, the junction temperature is equal to 107oC. Since this is below the maximum junction temperature of 125oC, there  
are no long term reliability concerns. In addition, since the junction temperature at which the device was characterized using forced convection  
is 111.2oC, this device can function without the degradation of the specified AC or DC parameters.  
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Reliability Information  
Table 7. vs. Air Flow Table for a 16-Lead VFQFPN  
JA  
JA at 0 Air Flow  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
74.7°C/W  
65.3°C/W  
58.5°C/W  
Transistor Count  
The transistor count for the 8SLVP1204 is: 258  
Package Outline Drawings  
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is  
the most current data available.  
www.idt.com/document/psc/16-vfqfpn-package-outline-drawing-30-x-30-x-09-mm-05-mm-170-x-170-mm-epad-nlnlg16p2  
Ordering Information  
Table 8. Ordering Information  
Part/Order Number  
8SLVP1204ANLGI  
8SLVP1204ANLGI8  
8SLVP1204ANLGI/W  
Marking  
204AI  
Package  
Shipping Packaging  
Tube  
Temperature  
-40°C to 85°C  
-40°C to 85°C  
-40°C to 85°C  
16-VFQFPN, Lead-Free  
16-VFQFPN, Lead-Free  
16-VFQFPN, Lead-Free  
204AI  
Tape & Reel, Pin 1 Orientation: EIA-481-C  
Tape & Reel, Pin 1 Orientation: EIA-481-D  
204AI  
Table 9. Pin 1 Orientation in Tape and Reel Packaging  
Part Number Suffix  
Pin 1 Orientation  
Illustration  
8
Quadrant 1 (EIA-481-C)  
/W  
Quadrant 2 (EIA-481-D)  
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Revision History  
Revision Date  
Description of Change  
September 13, 2018  
Added Note 2 to Table 5B.  
Updated the package outline drawings; however, no technical changes  
Completed other minor changes  
March 13, 2018  
June 8, 2015  
Features Section - Added Case Temperature bullet.  
Added Case Temperature Considerations.  
AC Characteristic Tables - added VCMR spec.  
Updated header/footer throughout the datasheet.  
December 19, 2014  
February 25, 2014  
Ordering Info: Changed Tray to Tube.  
VPP Deleted reference to NOTE 5; VO(pp) corrected typo ‘’;  
VDIFF_OUT corrected typo ‘’  
March 20, 2014  
VPP Deleted reference to NOTE 5; VO(pp) corrected typo ‘’;  
VDIFF_OUT corrected typo ‘’  
Output Rise/Fall; changed VSWING to VO(pp)  
January 27, 2014  
Changed NOTE 7 to read: VIL should not be less than -0.3V. VIH should not be higher than VCC  
.
Features section, 10th bullet; changed 65mA to 60mA.  
V
REF; added Minimum and Maximum values.  
September 30, 2013  
VOH; added Minimum and Maximum values.  
VOL; added Minimum and Maximum values.  
Features section - added Differential PCLK bullet referencing single-ended LVCMOS input.  
Added 3.3V ±10% Power Supply DC Characteristics Table  
Added 3.3V ±10% LVCMOS/LVTTL DC Characteristics Table  
Added 3.3V ±10% LVPECL DC Characteristics Table  
April 8, 2013  
AC Characteristics Table, added NOTE 6.  
Added 3.3V ±10% AC Characteristics Table and added NOTE 6.  
Parameter Measurement Information section - added 3.3V±10% LVPECL Output Load Test Circuit Diagram.  
Updated application note, Wiring the Differential Inputs to Accept Single-ended Levels.  
Updated Power Considerations section.  
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6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
www.idt.com/go/support  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without  
notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed  
in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any  
particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intel-  
lectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of  
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc All rights reserved.  
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16-VFQFPN Package Outline Drawing  
3.0 x 3.0 x 0.9 mm, 0.5mm Pitch, 1.70 x 1.70 mm Epad  
NL/NLG16P2, PSC-4169-02, Rev 05, Page 1  
‹ꢀ,QWHJUDWHGꢀ'HYLFHꢀ7HFKQRORJ\ꢁꢀ,QFꢂ  
16-VFQFPN Package Outline Drawing  
3.0 x 3.0 x 0.9 mm, 0.5mm Pitch, 1.70 x 1.70 mm Epad  
NL/NLG16P2, PSC-4169-02, Rev 05, Page 2  
Package Revision History  
Description  
Rev 04 Remove Bookmak at Pdf Format & Update Thickness Tolerance  
Change QFN to VFQFPN  
Date Created Rev No.  
Oct 25, 2017  
Jan 18, 2018  
Rev 05  
‹ꢀ,QWHJUDWHGꢀ'HYLFHꢀ7HFKQRORJ\ꢁꢀ,QFꢂ  
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