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9ZML1253EKILFT

型号：

9ZML1253EKILFT

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

24 页

PDF大小：

408 K

下载PDF手册
2:12 DB1200ZL Derivative for  
PCIe Gen1-4 and UPI  
9ZML1233E / 9ZML1253E  
Datasheet  
Description  
Features  
▪ SMBus write lock feature; increases system security  
The 9ZML1233E / 9ZML1253E are second generation enhanced  
performance DB1200ZL derivatives. The parts are pin-compatible  
upgrades to the 9ZML1232B, while offering much improved phase  
jitter performance. A fixed external feedback maintains low drift for  
critical QPI/UPI applications, while each input channel has software  
adjustable input-to-output delay to ease transport delay  
management for today's more complex server topologies. The  
9ZML1233E and 9ZML1253E have an SMBus Write Lockout pin for  
increased device and system security.  
▪ 2 software-configurable input-to-output delay lines; manage  
transport delay for complex topologies  
▪ LP-HCSL outputs; eliminate 24 resistors, save 41mm2 of area  
(1233E)  
▪ LP-HCSL outputs with 85Ω Zout; eliminate 48 resistors, save  
82mm2 of area (1253E)  
▪ 12 OE# pins; hardware control of each output  
▪ 3 selectable SMBus addresses; multiple devices can share same  
SMBus segment  
PCIe Clocking Architectures  
Supported  
▪ Selectable PLL bandwidths; minimizes jitter peaking in cascaded  
PLL topologies  
▪ Common Clocked (CC)  
▪ Hardware/SMBus control of PLL bandwidth and bypass; change  
▪ Independent Reference (IR) with and without spread spectrum  
mode without power cycle  
▪ Spread spectrum compatible; tracks spreading input clock for EMI  
reduction  
Typical Applications  
▪ 100MHz PLL Mode; UPI support  
▪ Servers  
▪ Storage  
▪ Networking  
▪ SSDs  
▪ 10 x 10 mm 72-VFQFPN package; small board footprint  
Key Specifications  
▪ Cycle-to-cycle jitter < 50ps  
▪ Output-to-output skew < 50ps  
Output Features  
▪ Input-to-output delay: 0ps default  
▪ Input-to-output delay variation < 50ps  
▪ Phase jitter: PCIe Gen4 < 0.5ps rms  
▪ Phase jitter: UPI > 9.6GB/s < 0.1ps rms  
▪ Phase jitter: IF-UPI < 1.0ps rms  
▪ 12 Low-Power (LP) HCSL output pairs (1233E)  
▪ 12 Low-Power (LP) HCSL output pairs with 85Ω Zout (1253E)  
Block Diagram  
FBOUT_NC  
FBOUT_NC  
I2O  
Delay  
Low Phase Noise  
Z-PLL  
^SEL_A_B#  
(SS-Compatible)  
DIF_11  
DIF_11  
DIF_INA  
DIF_INA  
Bypass path  
12  
outputs  
DIF_INB  
DIF_INB  
^vHIBW_BYPM_LOBW#  
CKPWRGD_PD#  
vSMB_A0_tri  
vSMB_WRTLOCK  
DIF_0  
DIF_0  
NOTE: Internal series resistors are only  
present on the 9ZML1253  
SMBDAT  
SMBCLK  
^OE(11:0)#  
©2018 Integrated Device Technology, Inc.  
1
April 12, 2018  
9ZML1233E / 9ZML1253E Datasheet  
Contents  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
PCIe Clocking Architectures Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Output Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Clock Periods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
General SMBus Serial Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
How to Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
9ZML1233E / 9ZML1253E SMBus Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
How to Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
©2018 Integrated Device Technology, Inc.  
2
April 12, 2018  
9ZML1233E / 9ZML1253E Datasheet  
Pin Assignments  
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55  
^OE7#  
^OE6#  
VDDIO  
GND  
VDDA  
GNDA  
1
2
3
4
5
6
7
8
9
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
^SEL_A_B#  
^vHIBW_BYPM_LOBW#  
CKPWRGD_PD#  
DIF_INB  
DIF_7#  
DIF_7  
DIF_6#  
DIF_6  
GND  
DIF_INB#  
GND  
9ZML1233  
9ZML1253  
Connect EPAD to GND  
VDDR  
VDD  
DIF_INA 10  
DIF_INA# 11  
DIF_5#  
DIF_5  
DIF_4#  
DIF_4  
VDDIO  
GND  
vSADR0_tri 12  
SMBDAT 13  
SMBCLK 14  
vSMB_WRTLOCK 15  
NC 16  
^OE5#  
^OE4#  
FBOUT_NC# 17  
FBOUT_NC 18  
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36  
^ prefix indicates internal 120kohm pull-up  
v prefix indicates internal 120kohm pull-down  
10 x 10 mm 72-VFQFPN 0.5mm pin pitch  
Pin Descriptions  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Power Power supply for PLL core.  
Description  
1
2
V
DDA  
GNDA  
GND  
Ground pin for the PLL core.  
Input to select differential input clock A or differential input clock B. This input has an  
internal 120kΩ pull-up resistor.  
3
^SEL_A_B#  
Input  
0 = input B selected, 1 = input A selected.  
Tri-level input to select High BW, Bypass or Low BW mode. This pin is biased to VDD/2  
(Bypass Mode) with internal pull-up/pull-down resistors. See PLL Operating Mode table for  
details.  
Latched  
In  
4
5
^vHIBW_BYPM_LOBW#  
CKPWRGD_PD#  
3.3V input notifies device to sample latched inputs and start up on first high assertion, or  
exit Power Down Mode on subsequent assertions. Low enters Power Down Mode.  
Input  
6
7
8
DIF_INB  
DIF_INB#  
GND  
Input  
Input  
GND  
True input of differential clock.  
Complement input of differential clock.  
Ground pin.  
Power supply for differential input clock (receiver). This V should be treated as an analog  
power rail and filtered appropriately. Nominally 3.3V.  
DD  
9
V
Power  
DDR  
10  
11  
DIF_INA  
Input  
Input  
True input of differential clock.  
DIF_INA#  
Complement input of differential clock.  
©2018 Integrated Device Technology, Inc.  
3
April 12, 2018  
9ZML1233E / 9ZML1253E Datasheet  
Table 1. Pin Descriptions (Cont.)  
Number  
Name  
Type  
Description  
SMBus address bit. This is a tri-level input that works in conjunction with other SADR pins,  
if present, to decode SMBus Addresses. It has an internal 120kΩ pull-down resistor. See  
the SMBus Addressing table.  
12  
vSADR0_tri  
Input  
13  
14  
SMBDAT  
SMBCLK  
I/O  
Data pin of SMBUS circuitry.  
Clock pin of SMBUS circuitry.  
Input  
This pin prevents SMBus writes when asserted. SMBus reads are not affected. This pin has  
an internal 120kΩ pull-down.  
15  
16  
17  
vSMB_WRTLOCK  
NC  
Input  
—
0 = SMBus writes allows, 1 = SMBus writes blocked.  
No connection.  
Complementary half of differential feedback output. This pin should NOT be connected to  
Output anything outside the chip. It exists to provide delay path matching to get 0 propagation  
delay.  
FBOUT_NC#  
True half of differential feedback output. This pin should NOT be connected to anything  
Output  
18  
19  
20  
FBOUT_NC  
^OE0#  
outside the chip. It exists to provide delay path matching to get 0 propagation delay.  
Active low input for enabling output 0. This pin has an internal 120kΩ pull-up resistor.  
Input  
1 = disable outputs, 0 = enable outputs.  
Active low input for enabling output 1. This pin has an internal pull-up resistor.  
^OE1#  
Input  
1 = disable outputs, 0 = enable outputs.  
21  
22  
NC  
—
No connection.  
Ground pin.  
GND  
GND  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
DIF_0  
DIF_0#  
DIF_1  
DIF_1#  
GND  
Output HCSL true clock output.  
Output HCSL complementary clock output.  
Output HCSL true clock output.  
Output HCSL complementary clock output.  
GND  
Ground pin.  
VDD  
Power Power supply, nominally 3.3V.  
Output HCSL true clock output.  
DIF_2  
DIF_2#  
DIF_3  
DIF_3#  
NC  
Output HCSL complementary clock output.  
Output HCSL true clock output.  
Output HCSL complementary clock output.  
—
No connection.  
Ground pin.  
GND  
GND  
Active low input for enabling output 2. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
35  
36  
37  
^OE2#  
^OE3#  
^OE4#  
Input  
Input  
Input  
Active low input for enabling output 3. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
Active low input for enabling output 4. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
©2018 Integrated Device Technology, Inc.  
4
April 12, 2018  
9ZML1233E / 9ZML1253E Datasheet  
Table 1. Pin Descriptions (Cont.)  
Number  
Name  
Type  
Description  
Active low input for enabling output 5. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
38  
^OE5#  
GND  
Input  
GND  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
Ground pin.  
V
Power Power supply for differential outputs.  
Output HCSL true clock output.  
DDIO  
DIF_4  
DIF_4#  
DIF_5  
Output HCSL complementary clock output.  
Output HCSL true clock output.  
DIF_5#  
Output HCSL complementary clock output.  
V
PWR  
GND  
Power supply, nominally 3.3V.  
Ground pin.  
DD  
GND  
DIF_6  
DIF_6#  
DIF_7  
DIF_7#  
GND  
Output HCSL true clock output.  
Output HCSL complementary clock output.  
Output HCSL true clock output.  
Output HCSL complementary clock output.  
GND  
Ground pin.  
V
Power Power supply for differential outputs.  
DDIO  
Active low input for enabling output 6. This pin has an internal pull-up resistor.  
53  
54  
55  
56  
^OE6#  
^OE7#  
^OE8#  
^OE9#  
Input  
1 = disable outputs, 0 = enable outputs.  
Active low input for enabling output 7. This pin has an internal pull-up resistor.  
Input  
1 = disable outputs, 0 = enable outputs.  
Active low input for enabling output 8. This pin has an internal pull-up resistor.  
Input  
1 = disable outputs, 0 = enable outputs.  
Active low input for enabling output 9. This pin has an internal pull-up resistor.  
Input  
1 = disable outputs, 0 = enable outputs.  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
NC  
—
No connection.  
Ground pin.  
GND  
GND  
DIF_8  
DIF_8#  
DIF_9  
DIF_9#  
GND  
Output HCSL true clock output.  
Output HCSL complementary clock output.  
Output HCSL true clock output.  
Output HCSL complementary clock output.  
GND  
Ground pin.  
V
Power Power supply, nominally 3.3V.  
Output HCSL true clock output.  
DD  
DIF_10  
DIF_10#  
DIF_11  
DIF_11#  
Output HCSL complementary clock output.  
Output HCSL true clock output.  
Output HCSL complementary clock output.  
©2018 Integrated Device Technology, Inc.  
5
April 12, 2018  
9ZML1233E / 9ZML1253E Datasheet  
Table 1. Pin Descriptions (Cont.)  
Number  
Name  
Type  
Description  
69  
70  
NC  
—
No connection.  
Ground pin.  
GND  
GND  
Active low input for enabling output 10. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
71  
^OE10#  
Input  
Active low input for enabling output 11. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
72  
73  
^OE11#  
EPAD  
Input  
GND  
Connect to ground.  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the 9ZML1233E / 9ZML1253E. These ratings, which are  
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other  
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating  
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating  
temperature range.  
Table 2. Absolute Maximum Ratings  
Parameter  
Symbol  
Conditions  
Minimum  
Typical  
Maximum Units Notes  
Supply Voltage  
Input Low Voltage  
Input High Voltage  
Input High Voltage  
Storage Temperature  
Junction Temperature  
Input ESD Protection  
V
3.9  
V
V
V
V
1,2  
1
DDx  
V
GND-0.5  
IL  
V
Except for SMBus interface.  
SMBus clock and data pins.  
V
+ 0.5  
DD  
1,3  
1
IH  
V
3.9  
150  
125  
IHSMB  
°
Ts  
-65  
C
1
Tj  
°C  
V
1
ESD prot Human Body Model.  
2000  
1
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Operation under these conditions is neither implied nor guaranteed.  
3 Not to exceed 3.9V.  
Electrical Characteristics  
Over specified temperature and voltage ranges unless otherwise indicated; see Test Loads for loading conditions.  
Table 3. SMBus Parameters  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum Units Notes  
SMBus Input Low Voltage  
SMBus Input High Voltage  
SMBus Output Low Voltage  
SMBus Sink Current  
V
0.8  
V
V
ILSMB  
V
2.1  
V
DDSMB  
IHSMB  
V
At I  
0.4  
V
OLSMB  
PULLUP  
PULLUP.  
I
At V  
4
mA  
V
OL.  
Nominal Bus Voltage  
V
2.7  
3.6  
1
DDSMB  
©2018 Integrated Device Technology, Inc.  
6
April 12, 2018  
9ZML1233E / 9ZML1253E Datasheet  
Table 3. SMBus Parameters (Cont.)  
Parameter  
Symbol  
Conditions  
(Max V - 0.15V) to (Min V + 0.15V).  
Minimum Typical Maximum Units Notes  
SCLK/SDATA Rise Time  
SCLK/SDATA Fall Time  
t
1000  
300  
ns  
ns  
1
1
5
RSMB  
IL  
IH  
t
(Min V + 0.15V) to (Max V - 0.15V).  
IH IL  
FSMB  
SMBus Operating Frequency  
f
Maximum SMBus operating frequency.  
400  
kHz  
MAXMB  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Control input must be monotonic from 20% to 80% of input swing.  
3 Time from deassertion until outputs are > 200mV.  
4 DIF_IN input.  
5 The differential input clock must be running for the SMBus to be active.  
Table 4. DIF_IN Clock Input Parameters  
Parameter  
Symbol  
Conditions  
Cross over voltage.  
Minimum  
Typical  
Maximum Units Notes  
Input Crossover Voltage  
Input Swing – DIF_IN  
V
150  
300  
0.35  
-5  
900  
mV  
mV  
V/ns  
μA  
1
1
CROSS  
V
Differential value.  
SWING  
Input Slew Rate – DIF_IN  
Input Leakage Current  
dv/dt  
Measured differentially.  
8
5
1,2  
I
V
= V  
V = GND.  
DD , IN  
IN  
IN  
Measurement from differential  
waveform.  
Input Duty Cycle  
d
45  
0
55  
%
1
1
tin  
Input Jitter –Cycle to Cycle  
J
Differential measurement.  
125  
ps  
DIFIn  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Slew rate measured through ±75mV window centered around differential zero.  
Table 5. Input/Supply/Common Parameters  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum Units Notes  
V
x
Supply voltage for core and analog.  
Supply voltage for differential outputs.  
Industrial range.  
3.135  
3.135  
3.3  
3.3  
3.465  
3.465  
V
V
DD  
Supply Voltage  
V
DDIO  
Ambient Operating  
Temperature  
T
-40  
2
85  
°C  
V
AMB  
Single-ended inputs, except SMBus, tri-level  
inputs.  
Input High Voltage  
Input Low Voltage  
V
V
V
+ 0.3  
DD  
IH  
Single-ended inputs, except SMBus, tri-level  
inputs.  
V
GND - 0.3  
0.8  
+ 0.3  
V
IL  
Input High Voltage  
Input Mid Voltage  
Input Low Voltage  
V
Tri-level inputs (“_tri” suffix).  
Tri-level inputs (“_tri” suffix).  
Tri-level inputs (“_tri” suffix).  
2.2  
1.2  
V
V
IH  
DD  
V
V
/2  
DD  
1.8  
IM  
V
GND - 0.3  
-5  
0.8  
5
V
IL  
I
Single-ended inputs, V = GND, V = V  
DDx.  
μA  
IN  
IN  
IN  
Single-ended inputs  
Input Current  
I
V
V
= 0 V; Inputs with internal pull-up resistors.  
-100  
100  
μA  
INP  
IN  
IN  
= V Inputs with internal pull-down resistors.  
DD;  
©2018 Integrated Device Technology, Inc.  
7
April 12, 2018  
9ZML1233E / 9ZML1253E Datasheet  
Table 5. Input/Supply/Common Parameters (Cont.)  
Parameter  
Symbol  
Conditions  
= 3.3V, Bypass Mode.  
Minimum Typical Maximum Units Notes  
F
V
V
1
400  
102  
7
MHz  
MHz  
nH  
IBYP  
DD  
DD  
Input Frequency  
Pin Inductance  
F
= 3.3V, 100MHz PLL Mode.  
98.5  
100.00  
5
1
IPLL  
L
pin  
C
Logic Inputs, except DIF_IN.  
DIF_IN differential clock inputs.  
Output pin capacitance.  
1.5  
1.5  
5
pF  
1
IN  
INDIF_IN  
Capacitance  
C
2.7  
6
pF  
1,4  
1
C
pF  
OUT  
From V power-up and after input clock  
stabilization or deassertion of PD# to 1st clock.  
DD  
Clk Stabilization  
t
1.2  
1.8  
33  
10  
ms  
1,2  
STAB  
Input SS  
Modulation  
Frequency PCIe  
Allowable frequency for PCIe applications  
(triangular modulation).  
f
30  
4
31.6  
kHz  
MODINPCIe  
DIF start after OE# assertion.  
DIF stop after OE# deassertion.  
OE# Latency  
t
5
clocks 1,2,3  
LATOE#  
Tdrive_PD#  
Tfall  
t
DIF output enable after PD# deassertion.  
Fall time of control inputs.  
85  
300  
5
μs  
ns  
ns  
1,3  
2
DRVPD  
t
F
Trise  
t
Rise time of control inputs.  
5
2
R
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Control input must be monotonic from 20% to 80% of input swing.  
3 Time from deassertion until outputs are > 200mV, PLL Mode.  
4 DIF_IN input.  
5 This parameter reflects the operating range after locking to a 100MHz input.  
Table 6. Current Consumption  
Parameter  
Symbol  
Conditions  
All other V pins, all outputs at 100MHz,  
Minimum  
Typical  
Maximum Units Notes  
DD  
I
22  
30  
65  
mA  
mA  
mA  
DDx  
C = 2pF; Zo = 85Ω.  
L
Operating Supply  
Current  
V
+ V  
pins, all outputs at 100MHz,  
DDR  
DDA  
I
56  
84  
1
DDA+R  
C = 2pF; Zo = 85Ω.  
L
V
pins, all outputs at 100MHz, C = 2pF; Zo =  
L
DDIO  
I
100  
DDO  
85Ω.  
I
All other V pins, all outputs Low/Low.  
0.9  
4.3  
0.1  
2
6
mA  
mA  
mA  
1
1
1
DDx  
DD  
Power Down  
Current  
I
V
V
+ V  
pins, all outputs Low/Low.  
DDR  
DDA+R  
DDA  
I
pins, all outputs Low/Low.  
0.2  
DDO  
DDIO  
1 Includes VDDR if applicable.  
©2018 Integrated Device Technology, Inc.  
8
April 12, 2018  
9ZML1233E / 9ZML1253E Datasheet  
Table 7. Skew and Differential Jitter Parameters  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum Units Notes  
Input-to-output skew in PLL Mode at 100MHz,  
nominal temperature and voltage.  
1,2,4,  
5,6,8  
CLK_IN, DIF[x:0]  
t
-100  
2.2  
-4  
100  
3.6  
50  
ps  
ns  
ps  
SKEW_PLL  
Input-to-output skew in Bypass Mode at 100MHz,  
nominal temperature and voltage.  
1,2,3,  
8
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
t
2.9  
0.0  
PD_BYP  
Input-to-output skew variation in PLL Mode at  
100MHz, across voltage and temperature.  
1,2,3,  
8
t
-50  
DSPO_PLL  
Input-to-output skew variation in Bypass Mode at  
1,2,3,  
8
100MHz, across voltage and temperature, T  
0 to 70°C, default slew rate.  
=
-250  
-350  
0.0  
0.0  
30  
250  
350  
50  
ps  
ps  
ps  
AMB  
CLK_IN, DIF[x:0]  
t
DSPO_BYP  
Input-to-output skew variation in Bypass Mode at  
1,2,3,  
8
100MHz, across voltage and temperature, T  
-40 to 85°C, default slew rate.  
=
AMB  
Output-to-output skew across all outputs,  
common to PLL and Bypass Mode, at 100MHz,  
default slew rate.  
1,2,3,  
8
DIF[x:0]  
t
SKEW_ALL  
PLL Jitter Peaking  
PLL Jitter Peaking  
PLL Bandwidth  
j
j
LOBW#_BYPASS_HIBW = 1.  
LOBW#_BYPASS_HIBW = 0.  
LOBW#_BYPASS_HIBW = 1.  
LOBW#_BYPASS_HIBW = 0.  
Measured differentially, PLL Mode.  
0
0
1.3  
1.3  
2.6  
1.0  
50  
2.5  
2
dB  
dB  
7,8  
7,8  
peak-hibw  
peak-lobw  
pll  
2
4
MHz  
MHz  
%
8,9  
HIBW  
PLL Bandwidth  
pll  
0.7  
45  
-1  
1.4  
55  
0
8,9  
LOBW  
Duty Cycle  
t
1
DC  
Duty Cycle Distortion  
t
Measured differentially, Bypass Mode at 100MHz.  
PLL Mode.  
-0.2  
13  
%
1,10  
1,11  
1,11  
DCD  
50  
5
ps  
Jitter, Cycle to Cycle  
t
jcyc-cyc  
Additive jitter in Bypass Mode.  
0.2  
ps  
1 Measured into fixed 2pF load cap. Input to output skew is measured at the first output edge following the corresponding input.  
2 Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.  
3 All Bypass Mode input-to-output specs refer to the timing between an input edge and the specific output edge created by it.  
4 This parameter is deterministic for a given device.  
5 Measured with scope averaging on to find mean value.  
6 This value is programmable.  
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.  
8 Guaranteed by design and characterization, not 100% tested in production.  
9 Measured at 3db down or half power point.  
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in Bypass Mode.  
11 Measured from differential waveform.  
©2018 Integrated Device Technology, Inc.  
9
April 12, 2018  
9ZML1233E / 9ZML1253E Datasheet  
Table 8. DIF HCSL/LP-HCSL Outputs  
Industry  
Limits  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Units Notes  
Slew Rate  
dV/dt  
Scope averaging on.  
2.0  
2.8  
4
4.0  
15  
0.6 – 4.0  
V/ns  
%
1,2,3  
1,2,4,7  
7,8  
Slew rate matching, scope  
averaging on.  
Slew Rate Matching  
Maximum Voltage  
ΔdV/dt  
20  
V
Measurement on  
660  
-111  
302  
794  
870  
1150  
MAX  
single-ended signal using  
absolute value (scope  
averaging off).  
mV  
Minimum Voltage  
V
-49  
-300  
7,8  
MIN  
Crossing Voltage (abs)  
Crossing Voltage (var)  
V
Scope averaging off.  
Scope averaging off.  
367  
32  
453  
74  
250 – 550  
140  
mV  
mV  
1,5,7  
1,6,7  
CROSS_ABS  
Δ-V  
CROSS  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Measured from differential waveform.  
3 Slew rate is measured through the VSWING voltage range centered around differential 0 V. This results in a ±150mV window around differential 0V.  
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75mV window centered on the average  
cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use  
for the edge rate calculations.  
5 VCROSS is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock  
rising and Clock# falling).  
6 The total variation of all VCROSS measurements in any particular system. Note that this is a subset of VCROSS_MIN/MAX (VCROSS absolute) allowed.  
The intent is to limit VCROSS induced modulation by setting Δ-VCROSS to be smaller than VCROSS absolute.  
7 At default SMBus settings.  
8 If driving a receiver with input terminations, the VMAX and VMIN values will be halved.  
Table 9. Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures  
Industry  
Limits  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Units Notes  
ps  
(p-p)  
1, 2, 3,  
6
t
t
PCIe Gen 1.  
13  
30  
86  
jphPCIeG1-CC  
PCIe Gen 2 Low Band  
10kHz < f < 1.5MHz  
ps  
0.25  
0.7  
3
1, 2, 6  
1, 2, 6  
(rms)  
(PLL BW of 5–16MHz or 8–16MHz,  
CDR = 5MHz).  
jphPCIeG2-CC  
PCIe Gen 2 High Band  
ps  
Phase Jitter,  
PLL Mode  
1.5MHz < f < Nyquist (50MHz)  
1.00  
1.5  
3.1  
(rms)  
(PLL BW of 5–16MHz or 8–16MHz,  
CDR = 5MHz).  
PCIe Gen 3  
ps  
t
t
0.24  
0.24  
0.35  
0.35  
1
1, 2, 6  
1, 2, 6  
(PLL BW of 2–4MHz or 2–5MHz,  
CDR = 10MHz).  
jphPCIeG3-CC  
jphPCIeG4-CC  
(rms)  
PCIe Gen 4  
ps  
0.5  
(PLL BW of 2–4MHz or 2–5MHz,  
CDR = 10MHz).  
(rms)  
©2018 Integrated Device Technology, Inc.  
10  
April 12, 2018  
9ZML1233E / 9ZML1253E Datasheet  
Table 9. Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures (Cont.)  
Industry  
Limits  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Units Notes  
ps  
(p-p)  
1, 2, 3,  
4, 6  
t
t
PCIe Gen 1.  
0.0  
0.05  
jphPCIeG1-CC  
PCIe Gen 2 Low Band  
10kHz < f < 1.5MHz  
ps  
1, 2, 3,  
4, 6  
0.00  
0.05  
(rms)  
(PLL BW of 5–16MHz or 8–16MHz,  
CDR = 5MHz).  
jphPCIeG2-CC  
PCIe Gen 2 High Band  
Additive Phase  
Jitter, Bypass  
Mode  
ps  
1.5MHz < f < Nyquist (50MHz)  
Not  
Applicable  
1, 2, 3,  
4, 6  
0.00  
0.05  
(rms)  
(PLL BW of 5–16MHz or 8–16MHz,  
CDR = 5MHz).  
PCIe Gen 3  
ps  
1, 2, 3,  
4, 6  
t
t
0.00  
0.00  
0.05  
0.05  
(PLL BW of 2–4MHz or 2–5MHz,  
CDR = 10MHz).  
jphPCIeG3-CC  
jphPCIeG4-CC  
(rms)  
PCIe Gen 4  
ps  
1, 2, 3,  
4, 6  
(PLL BW of 2–4MHz or 2–5MHz,  
CDR = 10MHz).  
(rms)  
Table 10. Filtered Phase Jitter Parameters - PCIe Independent Reference (IR) Architectures  
Industry  
Limits  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Units Notes  
PCIe Gen 2  
ps  
t
t
t
t
0.8  
1.2  
2
1, 2, 5  
(rms)  
jphPCIeG2-SRIS  
(PLL BW of 16MHz, CDR = 5MHz).  
Phase Jitter,  
PLL Mode  
PCIe Gen 3  
ps  
0.64  
0.00  
0.00  
0.68  
0.02  
0.02  
0.7  
1, 2, 5  
(rms)  
jphPCIeG3-SRIS  
jphPCIeG2-SRIS  
jphPCIeG3-SRIS  
(PLL BW of 2–4MHz, CDR = 10MHz).  
PCIe Gen 2  
ps  
2, 4, 5  
(rms)  
Additive  
Phase Jitter,  
Bypass Mode  
(PLL BW of 16MHz, CDR = 5MHz).  
Not  
Applicable  
PCIe Gen 3  
ps  
2, 4, 5  
(rms)  
(PLL BW of 2–4MHz, CDR = 10MHz).  
Notes for PCIe Filtered Phase Jitter tables:  
1 Applies to all differential outputs when driven by 9SQL495x or equivalent, guaranteed by design and characterization.  
2 Calculated from Intel-supplied clock jitter tool, when driven by 9SQL495x or equivalent with spread on and off.  
3 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1–12  
.
4 For RMS values, additive jitter is calculated by solving the following equation for b [b = sqrt(c2 - a2)] where “a” is rms input jitter and “c” is rms total  
jitter.  
5 IR is the new name for Separate Reference Independent Spread (SRIS) and Separate Reference no Spread (SRNS) PCIe clock architectures.  
According to the PCIe Base Specification Rev4.0 version 0.7 draft, the jitter transfer functions and corresponding jitter limits are not defined for the  
IR clock architecture. Widely accepted industry limits using widely accepted industry filters are used to populate this table. There are no accepted  
filters or limits for IR clock architectures at PCIe Gen1 or Gen4 data rates.  
©2018 Integrated Device Technology, Inc.  
11  
April 12, 2018  
9ZML1233E / 9ZML1253E Datasheet  
Table 11. Filtered Phase Jitter Parameters – QPI/UPI  
Industry  
Limits  
Parameter  
Symbol  
Conditions  
Minimum  
Typical  
Maximum  
Units Notes  
QPI & UPI  
ps  
0.15  
0.3  
0.5  
1, 2  
(100MHz or 133MHz, 4.8Gb/s,  
6.4Gb/s 12UI).  
(rms)  
QPI & UPI  
ps  
t
jphQPI_UPI  
0.08  
0.07  
0.1  
0.1  
0.3  
0.2  
1
1, 2  
Phase Jitter,  
PLL Mode  
(100MHz, 8.0Gb/s, 12UI).  
(rms)  
QPI & UPI  
ps  
1, 2  
(100MHz, > 9.6Gb/s, 12UI).  
(rms)  
0.1  
0.15  
0.2  
ps  
t
IF-UPI.  
1, 4, 5  
(rms)  
jphIF-UPI  
0.17  
QPI & UPI  
ps  
0.00  
0.03  
1, 2, 3  
(rms)  
(100MHz or 133MHz, 4.8Gb/s,  
6.4Gb/s 12UI).  
QPI & UPI  
ps  
t
jphQPI_UPI  
Additive  
Phase Jitter,  
Bypass Mode  
0.02  
0.02  
0.06  
0.07  
0.06  
0.08  
1, 2, 3  
(rms)  
Not  
Applicable  
(100MHz, 8.0Gb/s, 12UI).  
QPI & UPI  
ps  
1, 2, 3  
(rms)  
(100MHz, > 9.6Gb/s, 12UI).  
ps  
t
IF-UPI.  
1, 4  
jphIF-UPI  
(rms)  
1 Applies to all differential outputs, guaranteed by design and characterization.  
2 Calculated from Intel-supplied clock jitter tool, when driven by 9SQL495x or equivalent with spread on and off.  
3 Additive jitter for RMS values is calculated by solving for b [b = sqrt(c2 - a2)] where “a” is rms input jitter and “c” is rms total jitter.  
4 Calculated from phase noise analyzer when driven by Wenzel Associates source with Intel-specified brick-wall filter applied.  
5 Top number is when the buffer is in Low BW mode, bottom number is when the buffer is in High BW mode.  
Table 12. Unfiltered Phase Jitter Parameters – 12kHz to 20MHz  
Industry  
Limits  
Parameter  
Symbol  
Conditions  
Minimum  
Typical  
Maximum  
Units  
Notes  
fs  
Phase Jitter, PLL  
Mode  
PLL High BW, SSC Off,  
100MHz.  
t
171  
250  
1,2  
1,2  
jph12k-20MHi  
(rms)  
fs  
Phase Jitter, PLL  
Mode  
PLL Low BW, SSC Off,  
100MHz.  
Not  
applicable  
t
183  
109  
250  
150  
jph12k-20MLo  
(rms)  
fs  
Additive Phase  
Jitter, Bypass Mode  
Bypass Mode, SSC Off,  
100MHz.  
t
1,2,3  
jph12k-20MByp  
(rms)  
1 Applies to all outputs when driven by Wenzel clock source.  
2 12kHz to 20MHz brick wall filter.  
3 For RMS values, additive jitter is calculated by solving for b [a^2 + b^2 = c^2] where “a” is rms input jitter and “c” is rms total jitter.  
©2018 Integrated Device Technology, Inc.  
12  
April 12, 2018  
9ZML1233E / 9ZML1253E Datasheet  
Power Management  
Inputs  
Control Bits  
Outputs  
CKPWRGD_PD#  
DIF_IN  
SMBus EN bit  
DIF_x  
FBOUT_NC  
PLL State  
0
X
X
0
1
Low/Low  
Low/Low  
Running  
Low/Low  
Running  
Running  
Off  
On  
On  
1
Running  
Power Connections (9ZML12xxE)  
Pin Number  
V
V
GND  
Description  
DD  
DDIO  
1
9
2
8
Analog PLL  
Analog input  
28, 45, 64  
40, 52  
22, 27, 34, 39, 46, 51, 58, 63, 70  
DIF clocks  
Power Connections (for pin-compatibility with 9ZML12xxB)  
Pin Number  
V
V
GND  
Description  
DD  
DDIO  
1
9
2
8
Analog PLL  
Analog input  
16, 22, 27, 34, 39, 46, 51, 58, 63,  
28, 45, 64  
21, 33, 40, 52, 57, 69  
DIF clocks  
70  
PLL Operating Mode  
HIBW_BYPM_LOBW#  
Byte0[7:6]  
Low (PLL Low BW)  
Mid (Bypass)  
00  
01  
11  
High (PLL High BW)  
Note: PLL is off in Bypass Mode.  
©2018 Integrated Device Technology, Inc.  
13  
April 12, 2018  
9ZML1233E / 9ZML1253E Datasheet  
Skew Programming  
Skew[2:0]  
Skew Steps  
Skew (ps)  
000  
001  
010  
011  
100  
101  
110  
111  
0
1
2
3
4
5
6
7
0
-416.67  
-833.33  
-1250.00  
-1666.67  
-2083.33  
-2500.00  
-2916.67  
Figure 1. Skew Diagram  
DIF_INx  
tSKEW_PLL  
DIF_n  
Test Loads  
Low-Power HCSL Output Test Load  
(standard PCIe source-terminated test load)  
Rs  
CL  
L
Test  
Points  
Differential Zo  
CL  
Rs  
Table 13. Parameters for Low-Power HCSL Output Test Load  
Device  
Rs (Ω)  
Zo (Ω)  
L (inches)  
C (pF)  
L
9ZML123x  
9ZML123x  
9ZML125x *  
9ZML125x *  
27  
33  
85  
100  
85  
12  
12  
12  
12  
2
2
2
2
Internal  
7.5  
100  
* Contact factory for versions of this device with Zo=100Ω.  
©2018 Integrated Device Technology, Inc.  
14  
April 12, 2018  
9ZML1233E / 9ZML1253E Datasheet  
Alternate Terminations  
The LP-HCSL can easily drive other logic families. See “AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's “Universal”  
Low-Power HCSL Outputs” for details.  
Clock Periods  
Table 14. Clock Periods – Differential Outputs with Spread Spectrum Disabled  
Measurement Window  
1 Clock  
1μs  
0.1s  
0.1s  
0.1s  
1μs  
1 Clock  
- S S C  
- p p m  
+ p p m  
+ S S C  
Center  
Frequency  
MHz  
- c 2 c jit t e r  
AbsPer  
Minimum  
Short-Term Long-Term  
Average  
Minimum  
0 ppm  
Period  
Nominal  
Long-Term Short-Term +c2cjitter  
Average  
Maximum  
Average  
Minimum  
Average  
Maximum  
AbsPer  
Maximum Units Notes  
SSC On  
DIF  
100.00  
9.94900  
—
9.99900  
10.00000  
10.00100  
—
10.05100  
ns  
1,2,3  
Table 15. Clock Periods – Differential Outputs with Spread Spectrum Enabled  
Measurement Window  
1 Clock  
1μs  
0.1s  
0.1s  
0.1s  
1μs  
1 Clock  
- S S C  
- p p m  
+ p p m  
+ S S C  
Center  
Frequency  
MHz  
-c2cjitter  
AbsPer  
Minimum  
Short-Term Long-Term  
Average  
Minimum  
0 ppm  
Period  
Nominal  
Long-Term Short-Term +c2cjitter  
Average  
Maximum  
Average  
Minimum  
Average  
Maximum  
AbsPer  
Maximum Units Notes  
SSC On  
DIF  
99.75  
9.94906  
9.99906  
10.02406  
10.02506  
10.02607  
10.05107  
10.10107 ns 1,2,3  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ accuracy requirements  
(+/-100ppm). The buffer itself does not contribute to ppm error.  
3 Driven by SRC output of main clock, 100MHz PLL Mode or Bypass Mode.  
©2018 Integrated Device Technology, Inc.  
15  
April 12, 2018  
9ZML1233E / 9ZML1253E Datasheet  
General SMBus Serial Interface Information  
How to Write  
How to Read  
▪ Controller (host) sends a start bit  
▪ Controller (host) will send a start bit  
▪ Controller (host) sends the write address  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the write address  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the beginning byte location = N  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the beginning byte location = N  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the byte count = X  
▪ IDT clock will acknowledge  
▪ Controller (host) will send a separate start bit  
▪ Controller (host) sends the read address  
▪ IDT clock will acknowledge  
▪ Controller (host) starts sending Byte N through Byte N+X-1  
▪ IDT clock will acknowledge each byte one at a time  
▪ Controller (host) sends a stop bit  
▪ IDT clock will send the data byte count = X  
▪ IDT clock sends Byte N+X-1  
▪ IDT clock sends Byte 0 through Byte X (if X(H) was written to  
Index Block Write Operation  
Byte 8)  
Controller (Host)  
IDT (Slave/Receiver)  
▪ Controller (host) will need to acknowledge each byte  
▪ Controller (host) will send a not acknowledge bit  
▪ Controller (host) will send a stop bit  
T
starT bit  
Slave Address  
WR  
WRite  
ACK  
ACK  
ACK  
ACK  
Index Block Read Operation  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
Controller (Host)  
starT bit  
IDT (Slave/Receiver)  
T
Slave Address  
WRite  
WR  
ACK  
ACK  
Beginning Byte = N  
O
O
O
O
O
O
RT  
Repeat starT  
Slave Address  
ReaD  
RD  
Byte N + X - 1  
ACK  
ACK  
P
stoP bit  
Data Byte Count=X  
Beginning Byte N  
ACK  
ACK  
9ZML1233E / 9ZML1253E SMBus Addressing  
SMB_A0_tri  
SMBus Address (Read/Write bit = 0)  
O
O
O
O
O
O
0
M
1
D8  
DA  
DE  
Byte N + X - 1  
N
P
Not acknowledge  
stoP bit  
©2018 Integrated Device Technology, Inc.  
16  
April 12, 2018  
9ZML1233E / 9ZML1253E Datasheet  
SMBus Table: PLL Mode and Frequency Select Register  
Byte 0  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
PLL Mode bit [1]  
PLL Mode bit [0]  
SEL_A_B#  
PLL Operating Mode Rd back 1  
PLL Operating Mode Rd back 0  
Input Select Readback  
Reserved  
R
R
R
Latch  
Latch  
Real  
0
See PLL Operating Mode table  
DIF_INB  
DIF_INA  
Enable S/W control of PLL BW and  
Input select  
Bit 3  
PLL_InSEL_SW_EN  
RW  
Pin Control  
SMBus Control  
0
Bit 2  
Bit 1  
Bit 0  
PLL Mode bit [1]  
PLL Mode bit [0]  
PLL Operating Mode 1  
PLL Operating Mode 1  
Reserved  
RW  
RW  
1
1
1
1
See PLL Operating Mode table  
Note: Changing the PLL operating mode between HiBW or LoBW and Bypass mode or between Bypass mode and HiBW or LoBW  
requires a system reset. Changing the PLL operating mode between HiBW and LoBw or between LoBW and HiBW does not require a  
system reset.  
SMBus Table: Output Disable Register  
Byte 1  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
DIF_7_En  
DIF_6_En  
DIF_5_En  
DIF_4_En  
DIF_3_En  
DIF_2_En  
DIF_1_En  
DIF_0_En  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
1
1
1
1
1
1
1
1
Low/Low  
Pin Control  
SMBus Table: Output Control Register  
Byte 2  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
Reserved  
0
0
0
0
1
1
1
1
Reserved  
Reserved  
DIF_11_En  
DIF_10_En  
DIF_9_En  
DIF_8_En  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
RW  
RW  
RW  
RW  
Low/Low  
Pin Control  
©2018 Integrated Device Technology, Inc.  
17  
April 12, 2018  
9ZML1233E / 9ZML1253E Datasheet  
SMBus Table: Reserved Register  
Byte 3  
Name  
Control Function  
Type  
Type  
Type  
0
0
0
1
1
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
0
0
0
SMBus Table: Reserved Register  
Byte 4  
Name  
Control Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
0
0
0
SMBus Table: Vendor & Revision ID Register  
Byte 5  
Name  
Control Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
RID3  
RID2  
RID1  
RID0  
VID3  
VID2  
VID1  
VID0  
R
R
R
R
R
R
R
R
0
1
0
0
0
0
0
1
REVISION ID  
E rev = 0100  
—
—
—
—
—
—
—
—
VENDOR ID  
©2018 Integrated Device Technology, Inc.  
18  
April 12, 2018  
9ZML1233E / 9ZML1253E Datasheet  
SMBus Table: Device ID  
Byte 6  
Name  
Control Function  
Device ID 7 (MSB)  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R
R
R
R
R
R
R
R
1
1
1
X
1
1
0
X
Device ID 6  
Device ID 5  
Device ID 4  
Device ID 3  
Device ID 2  
Device ID 1  
Device ID 0  
9ZML1233=ED  
9ZML1253=FD  
SMBus Table: Byte Count Register  
Byte 7  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
Reserved  
Reserved  
0
0
0
0
1
0
0
0
BC4  
BC3  
BC2  
BC1  
BC0  
RW  
RW  
RW  
RW  
RW  
Writing to this register configures how  
many bytes will be read back.  
Default value is 8 hex, so 9 bytes (0 to 8)  
will be read back by default.  
SMBus Table: Output Skew Register A (when Input Clock A is selected)  
Byte 8  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
0
0
0
I2O_FB_ASkew2  
I2O_FB_ASkew1  
I2O_FB_ASkew0  
RW  
RW  
RW  
Binary value of number of VCO periods  
that outputs will be pulled earlier than  
input.  
Channel A Output delay programming  
(early)  
Note: For example, at 2.4GHz, each VCO period is 416.7ps and there are 24 VCO periods in a 100MHz output. Each write to bits [2:0] will  
pull the output a early by that number of VCO periods. Writing “110” 4 times would pull the output back in phase with the input. Writing  
“001” twice will accomplish the same result as writing “010” once - pulling the output 2 VCO periods earlier.  
©2018 Integrated Device Technology, Inc.  
19  
April 12, 2018  
9ZML1233E / 9ZML1253E Datasheet  
SMBus Table: Output Skew Register A (when Input Clock B is selected)  
Byte 9  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
0
0
0
I2O_FB_BSkew2  
I2O_FB_BSkew1  
I2O_FB_BSkew0  
RW  
RW  
RW  
Binary value of number of VCO periods  
that outputs will be earlier than input.  
Default is 0.  
Channel B Output delay programming  
(early)  
Note: For example, at 2.4GHz, each VCO period is 416.7ps and there are 24 VCO periods in a 100MHz output. Each write to bits [2:0] will  
pull the output a early by that number of VCO periods. Writing “110” 4 times would pull the output back in phase with the input. Writing  
“001” twice will accomplish the same result as writing “010” once - pulling the output 2 VCO periods earlier.  
Package Outline Drawings  
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information  
is the most current data available.  
www.idt.com/document/psc/nlnlg72-package-outline-100-x-100-mm-body-epad-59-mm-sq-050-mm-pitch-vfqfpn-sawn  
Ordering Information  
Orderable Part Number  
Package  
Carrier Type  
Temperature  
9ZML1233EKILF  
9ZML1233EKILFT  
9ZML1253EKILF  
9ZML1253EKILFT  
10 x 10 mm, 0.5mm pitch 72-VFQFPN  
10 x 10 mm, 0.5mm pitch 72-VFQFPN  
10 x 10 mm, 0.5mm pitch 72-VFQFPN  
10 x 10 mm, 0.5mm pitch 72-VFQFPN  
Tray  
-40° to +85°C  
-40° to +85°C  
-40° to +85°C  
-40° to +85°C  
Tape and Reel  
Tray  
Tape and Reel  
“LF” designates PB-free configuration, RoHS compliant.  
“E” is the device revision designator (will not correlate with the datasheet revision).  
Marking Diagrams  
1. “L” denotes RoHS compliant package.  
2. “LOT” denotes the lot number.  
ICS  
ICS  
3. “COO” denotes country of origin.  
9ZML1253EKIL  
LOT  
COO YYWW  
9ZML1233EKIL  
LOT  
COO YYWW  
4. “YYWW” denotes the last two digits of the year and week the part  
was assembled.  
©2018 Integrated Device Technology, Inc.  
20  
April 12, 2018  
9ZML1233E / 9ZML1253E Datasheet  
Revision History  
Revision Date  
Description of Change  
April 12, 2018  
December 1, 2017  
May 19, 2017  
May 11, 2017  
Updated absolute maximum supply voltage rating and VIHSMB to 3.9V.  
Removed “5V tolerant” reference in pins 13 and 14 descriptions.  
Corrected typos in orderable part numbers.  
▪ Updated package outline drawings to latest version.  
▪ Updated Byte 6 IDs.  
April 27, 2017  
April 21, 2017  
▪ Updated Phase Jitter, PLL Mode IF-UPI typical and maximum values.  
▪ Update Features and Key Specifications.  
▪ Updated PCIe Common Clocked, PCIe Separate Clocked, and QPI/UPI to latest format, added IF-UPI spec  
to QPI/UPI tables.  
▪ Updated Test Loads drawing to latest version.  
▪ Corrected SMBus Addressing table for 1233/1253.  
April 11, 2017  
▪ Reverted back to original Device ID Scheme, byte 6 updated accordingly:  
9ZML1233=ED  
9ZML1253=FD  
January 31, 2017  
Initial release.  
Corporate Headquarters  
Sales  
Tech Support  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
www.IDT.com/go/support  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,  
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same  
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability  
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not  
convey any license under intellectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-  
sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property  
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.  
©2018 Integrated Device Technology, Inc.  
21  
April 12, 2018  
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