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9ZML1232BKLFT

型号：

9ZML1232BKLFT

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

19 页

PDF大小：

223 K

下载PDF手册
DATASHEET  
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
9ZML1232  
General Description  
Features/Benefits  
The 9ZML1232 is a 2-input/12-output differential mux for  
use in servers. It meets the demanding DB1200ZL  
performance specifications and utilizes Low-Power  
HCSL-compatible outputs to reduce power consumption  
and termination components. It is suitable for PCI-Express  
Gen1/2/3 or QPI/UPI applications, and uses a fixed external  
feedback to maintain low drift for demanding QPI  
applications.  
• Fixed feedback path; 0ps input-to-output delay  
• 9 Selectable SMBus addresses; multiple devices can  
share same SMBus segment  
• Separate VDDIO for outputs; allows maximum power  
savings  
• PLL or bypass mode; PLL can dejitter incoming clock  
• Hardware or Software-selectable PLL BW; minimizes  
jitter peaking in downstream PLL's  
• Spread spectrum compatible; tracks spreading input  
Recommended Application  
Clock Mux for Romley, Grantley and Purley Servers  
clock for EMI reduction  
• SMBus Interface; unused outputs can be disabled  
• Differential outputs are Low/Low in power down;  
maximum power savings  
Output Features  
• 12 - Low-Power (LP) HCSL Output Pairs  
Key Specifications  
• Cycle-to-cycle jitter <50ps  
• Output-to-output skew <65 ps  
• Input-to-output delay: Fixed at 0 ps  
• Input-to-output delay variation <50ps  
• Phase jitter: PCIe Gen3 <1ps rms  
• Phase jitter: QPI/UPI 9.6GB/s <0.2ps rms  
Block Diagram  
OE(11:0)#  
FBOUT_NC  
Z-PLL  
(SS Compatible)  
DIF_INB  
DIF_INB#  
DIF(11:0)  
DIF_INA  
DIF_INA#  
HIBW_BYPM_LOBW#  
SEL_A_B#  
CKPWRGD/PD#  
Logic  
SMB_A0_tri  
SMB_A1_tri  
SMBDAT  
SMBCLK  
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
1
9ZML1232  
REV E 112015  
9ZML1232  
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
Pin Configuration  
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55  
^OE7#  
^OE6#  
VDDIO  
GND  
VDDA  
GNDA  
1
2
3
4
5
6
7
8
9
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
^SEL_A_B#  
^vHIBW_BYPM_LOBW#  
CKPWRGD_PD#  
DIF_INB  
DIF_7#  
DIF_7  
DIF_6#  
DIF_6  
GND  
DIF_INB#  
GND  
VDDR  
9ZML1232  
VDD  
DIF_INA 10  
DIF_INA# 11  
vSMB_A0_tri 12  
SMBDAT 13  
DIF_5#  
DIF_5  
DIF_4#  
DIF_4  
VDDIO  
GND  
SMBCLK 14  
vSMB_A1_tri 15  
GND 16  
^OE5#  
^OE4#  
FBOUT_NC# 17  
FBOUT_NC 18  
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36  
^ prefix indicates internal 120Kohm Pull Up  
v prefix indicates internal 120Kohm Pull down  
10mm x 10mm 72-MLF, 0.5mm pin pitch  
Power Management Table  
Inputs  
Outputs  
Control Bits  
PLL State  
DIF_IN/  
SMBus  
DIFx/  
FBOUT_NC/  
CKPWRGD_PD#  
DIF_IN#  
EN bit  
DIFx# FB_OUT_NC#  
0
X
X
0
1
Low/Low  
Low/Low  
Running  
Low/Low  
Running  
Running  
OFF  
ON  
ON  
1
Running  
PLL Operating Mode Table  
Tri-Level Input Thresholds  
Level  
Low  
Mid  
High  
Voltage  
<0.8V  
1.2<Vin<1.8V  
Vin > 2.2V  
HiBW_BypM_LoBW# Byte0, bit (7:6)  
Low ( PLL Low BW)  
Mid (Bypass)  
00  
01  
11  
High (PLL High BW)  
NOTE: PLL is off in Bypass mode  
9ZML1232 SMBus Addressing  
Power Connections  
SMB_A(1:0)_tri  
SMBus Address (Rd/Wrt bit = 0)  
00  
0M  
01  
M0  
MM  
M1  
10  
D8  
DA  
DE  
C2  
C4  
C6  
CA  
CC  
CE  
Pin Number  
VDDIO  
Description  
VDD  
1
9
GND  
2
8
Analog PLL  
Analog Input  
16, 22, 27, 34,  
39, 46, 51, 58,  
63, 70  
21, 33, 40,  
52, 57, 69  
28, 45, 64  
DIF clocks  
1M  
11  
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
2
9ZML1232  
REV E 112015  
9ZML1232  
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
Pin Descriptions  
PIN #  
PIN NAME  
PIN TYPE  
PWR  
PWR  
DESCRIPTION  
1
2
VDDA  
GNDA  
3.3V power for the PLL core.  
Ground pin for the PLL core.  
Input to select differential input clock A or differential input clock B. This input has  
an internal pull-up resistor.  
0 = Input B selected, 1 = Input A selected.  
Trilevel input to select High BW, Bypass or Low BW mode.  
See PLL Operating Mode Table for Details.  
3.3V Input notifies device to sample latched inputs and start up on first high  
assertion, or exit Power Down Mode on subsequent assertions. Low enters  
Power Down Mode.  
3
4
5
^SEL_A_B#  
IN  
LATCHE  
D IN  
^vHIBW_BYPM_LOBW#  
CKPWRGD_PD#  
IN  
6
7
8
DIF_INB  
DIF_INB#  
GND  
IN  
IN  
PWR  
0.7 V HCSL-Compatible Differential True input  
0.7 V HCSL-Compatible Differential Complement Input  
Ground pin.  
3.3V power for differential input clock (receiver). This VDD should be treated as  
an analog power rail and filtered appropriately.  
0.7 V HCSL-Compatible Differential True input  
0.7 V HCSL-Compatible Differential Complement Input  
SMBus address bit. This is a tri-level input that works in conjunction with the  
SMB_A1 to decode 1 of 9 SMBus Addresses. It has an internal 120Kohm pull  
down resistor.  
9
VDDR  
PWR  
10  
11  
DIF_INA  
DIF_INA#  
IN  
IN  
12  
vSMB_A0_tri  
IN  
13  
14  
SMBDAT  
SMBCLK  
I/O  
IN  
Data pin of SMBUS circuitry, 5V tolerant  
Clock pin of SMBUS circuitry, 5V tolerant  
SMBus address bit. This is a tri-level input that works in conjunction with the  
SMB_A0 to decode 1 of 9 SMBus Addresses. It has an internal 120Kohm pull  
down resistor.  
15  
16  
17  
vSMB_A1_tri  
GND  
IN  
PWR  
OUT  
Ground pin.  
Complementary half of differential feedback output. This pin should NOT be  
connected to anything outside the chip. It exists to provide delay path matching to  
get 0 propagation delay.  
FBOUT_NC#  
True half of differential feedback output. This pin should NOT be connected to  
anything outside the chip. It exists to provide delay path matching to get 0  
propagation delay.  
18  
19  
20  
FBOUT_NC  
^OE0#  
OUT  
IN  
Active low input for enabling DIF pair 0. This pin has an internal pull-up resistor.  
1 =disable outputs, 0 = enable outputs  
Active low input for enabling DIF pair 1. This pin has an internal pull-up resistor.  
1 =disable outputs, 0 = enable outputs  
^OE1#  
IN  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
VDDIO  
GND  
PWR  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
PWR  
Power supply for differential outputs  
Ground pin.  
DIF_0  
DIF_0#  
DIF_1  
DIF_1#  
GND  
0.7V differential true clock output  
0.7V differential Complementary clock output  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Ground pin.  
VDD  
Power supply, nominal 3.3V  
DIF_2  
DIF_2#  
DIF_3  
DIF_3#  
VDDIO  
GND  
0.7V differential true clock output  
0.7V differential Complementary clock output  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Power supply for differential outputs  
Ground pin.  
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
3
9ZML1232  
REV E 112015  
9ZML1232  
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
Pin Descriptions (cont.)  
PIN #  
PIN NAME  
PIN TYPE  
DESCRIPTION  
Active low input for enabling DIF pair 2. This pin has an internal pull-up resistor.  
1 =disable outputs, 0 = enable outputs  
35  
^OE2#  
IN  
Active low input for enabling DIF pair 3. This pin has an internal pull-up resistor.  
1 =disable outputs, 0 = enable outputs  
36  
37  
38  
^OE3#  
^OE4#  
^OE5#  
IN  
IN  
IN  
Active low input for enabling DIF pair 4. This pin has an internal pull-up resistor.  
1 =disable outputs, 0 = enable outputs  
Active low input for enabling DIF pair 5. This pin has an internal pull-up resistor.  
1 =disable outputs, 0 = enable outputs  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
GND  
PWR  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
PWR  
Ground pin.  
VDDIO  
DIF_4  
DIF_4#  
DIF_5  
DIF_5#  
VDD  
Power supply for differential outputs  
0.7V differential true clock output  
0.7V differential Complementary clock output  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Power supply, nominal 3.3V  
GND  
Ground pin.  
DIF_6  
DIF_6#  
DIF_7  
DIF_7#  
GND  
0.7V differential true clock output  
0.7V differential Complementary clock output  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Ground pin.  
VDDIO  
Power supply for differential outputs  
Active low input for enabling DIF pair 6. This pin has an internal pull-up resistor.  
1 =disable outputs, 0 = enable outputs  
53  
54  
55  
56  
^OE6#  
^OE7#  
^OE8#  
^OE9#  
IN  
IN  
IN  
IN  
Active low input for enabling DIF pair 7. This pin has an internal pull-up resistor.  
1 =disable outputs, 0 = enable outputs  
Active low input for enabling DIF pair 8. This pin has an internal pull-up resistor.  
1 =disable outputs, 0 = enable outputs  
Active low input for enabling DIF pair 9. This pin has an internal pull-up resistor.  
1 =disable outputs, 0 = enable outputs  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
VDDIO  
GND  
PWR  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
PWR  
Power supply for differential outputs  
Ground pin.  
DIF_8  
DIF_8#  
DIF_9  
DIF_9#  
GND  
0.7V differential true clock output  
0.7V differential Complementary clock output  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Ground pin.  
VDD  
Power supply, nominal 3.3V  
DIF_10  
DIF_10#  
DIF_11  
DIF_11#  
VDDIO  
GND  
0.7V differential true clock output  
0.7V differential Complementary clock output  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Power supply for differential outputs  
Ground pin.  
Active low input for enabling DIF pair 10. This pin has an internal pull-up resistor.  
1 =disable outputs, 0 = enable outputs  
71  
72  
^OE10#  
^OE11#  
IN  
IN  
Active low input for enabling DIF pair 11. This pin has an internal pull-up resistor.  
1 =disable outputs, 0 = enable outputs  
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
4
9ZML1232  
REV E 112015  
9ZML1232  
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the 9ZML1232. These ratings, which are standard  
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other  
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute  
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over  
the recommended operating temperature range.  
PARAMETER  
SYMBOL  
CONDITIONS  
UNITS NOTES  
MIN  
TYP  
MAX  
4.6  
4.6  
3.3V Core Supply Voltage VDDA, R  
3.3V Logic Supply Voltage  
I/O Supply Voltage  
V
V
V
V
1,2  
1,2  
1,2  
1
VDD  
VDDIO  
VIL  
4.6  
Input Low Voltage  
GND-0.5  
Input High Voltage  
Input High Voltage  
VIH  
Except for SMBus interface  
SMBus clock and data pins  
VDD+0.5V  
5.5V  
V
1
1
VIHSMB  
V
°C  
°C  
V
1
1
1
Storage Temperature  
Junction Temperature  
Input ESD protection  
Ts  
Tj  
ESD prot  
-65  
150  
125  
Human Body Model  
2000  
1Guaranteed by design and characterization, not 100% tested in production.  
2 Operation under these conditions is neither implied nor guaranteed.  
Electrical Characteristics–DIF_IN Clock Input Parameters  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS NOTES  
Input Crossover Voltage -  
DIF_IN  
VCROSS  
Cross Over Voltage  
150  
900  
mV  
1
Input Swing - DIF_IN  
Input Slew Rate - DIF_IN  
Input Leakage Current  
Input Duty Cycle  
VSWING  
dv/dt  
IIN  
Differential value  
Measured differentially  
300  
0.4  
-5  
mV  
V/ns  
uA  
1
8
5
1,2  
VIN = VDD , VIN = GND  
dtin  
Measurement from differential wavefrom  
45  
0
55  
125  
%
1
1
Input Jitter - Cycle to Cycle  
JDIFIn  
Differential Measurement  
ps  
1 Guaranteed by design and characterization, not 100% tested in production.  
2Slew rate measured through +/-75mV window centered around differential zero  
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
5
9ZML1232  
REV E 112015  
9ZML1232  
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
Electrical Characteristics–Input/Supply/Common Output Parameters  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS NOTES  
Ambient Operating  
Temperature  
TCOM  
Commmercial range  
0
25  
70  
°C  
V
1
1
Single-ended inputs, except SMBus, low  
threshold and tri-level inputs  
Single-ended inputs, except SMBus, low  
threshold and tri-level inputs  
Input High Voltage  
Input Low Voltage  
VIH  
2
VDD + 0.3  
VIL  
IIN  
GND - 0.3  
-5  
0.8  
5
V
1
1
Single-ended inputs, VIN = GND, VIN = VDD  
-0.12  
-0.02  
uA  
Single-ended inputs  
VIN = 0 V; Inputs with internal pull-up resistors  
IN = VDD; Inputs with internal pull-down resistors  
Input Current  
IINP  
-200  
200  
uA  
1
V
Input Frequency  
Pin Inductance  
Fibyp  
Fipll  
VDD = 3.3 V, Bypass mode  
33  
90  
150  
110  
7
MHz  
MHz  
nH  
2
2
VDD = 3.3 V, 100MHz PLL mode  
100.00  
Lpin  
1
CIN  
Logic Inputs, except DIF_IN  
DIF_IN differential clock inputs  
1.5  
1.5  
5
pF  
1
CINDIF_IN  
2.7  
pF  
1,4  
Capacitance  
COUT  
Output pin capacitance  
6
pF  
1
From VDD Power-Up and after input clock  
stabilization or de-assertion of PD# to 1st clock  
Clk Stabilization  
TSTAB  
1
ms  
1,2  
Input SS Modulation  
Frequency  
Allowable Frequency  
(Triangular Modulation)  
fMODIN  
30  
4
33  
kHz  
1
DIF start after OE# assertion  
DIF stop after OE# deassertion  
DIF output enable after  
OE# Latency  
Tdrive_PD#  
tLATOE#  
tDRVPD  
12  
clocks  
us  
1
300  
1,3  
PD# de-assertion  
Tfall  
tF  
Fall time of control inputs  
5
5
ns  
ns  
V
1,2  
1,2  
1
Trise  
tR  
Rise time of control inputs  
SMBus Input Low Voltage  
SMBus Input High Voltage  
VILSMB  
VIHSMB  
0.8  
2.1  
VDDSMB  
0.4  
V
1
SMBus Output Low Voltage VOLSMB  
@ IPULLUP  
@ VOL  
V
1
SMBus Sink Current  
Nominal Bus Voltage  
SCLK/SDATA Rise Time  
IPULLUP  
VDDSMB  
tRSMB  
4
mA  
V
1
3V to 5V +/- 10%  
2.7  
5.5  
1000  
300  
1
(Max VIL - 0.15) to (Min VIH + 0.15)  
(Min VIH + 0.15) to (Max VIL - 0.15)  
ns  
ns  
1
SCLK/SDATA Fall Time  
SMBus Operating  
Frequency  
tFSMB  
1
fMAXSMB  
Maximum SMBus operating frequency  
400  
kHz  
1,5  
1Guaranteed by design and characterization, not 100% tested in production.  
2Control input must be monotonic from 20% to 80% of input swing.  
3Time from deassertion until outputs are >200 mV  
4DIF_IN input  
5The differential input clock must be running for the SMBus to be active  
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
6
9ZML1232  
REV E 112015  
9ZML1232  
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
Electrical Characteristics–DIF 0.7V Low Power Differential Outputs  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
Trf  
CONDITIONS  
MIN  
1
TYP MAX UNITS NOTES  
V/ns  
%
Slew rate  
Slew rate matching  
Scope averaging on  
Slew rate matching, Scope averaging on  
3.3  
2
4
20  
1, 2, 3  
1, 2, 4  
∆
Trf  
Statistical measurement on single-ended signal  
using oscilloscope math function. (Scope  
averaging on)  
Voltage High  
Voltage Low  
VHigh  
VLow  
660  
804  
19  
850  
1
1
mV  
-150  
150  
Max Voltage  
Min Voltage  
Vswing  
Crossing Voltage (abs)  
Crossing Voltage (var)  
Vmax  
Vmin  
Vswing  
Measurement on single ended signal using  
absolute value. (Scope averaging off)  
Scope averaging off  
885  
-29  
1569  
465  
12  
1150  
1
1
1, 2  
1, 5  
1, 6  
mV  
-300  
300  
300  
mV  
mV  
mV  
Vcross_abs  
Scope averaging off  
Scope averaging off  
550  
140  
∆
-Vcross  
1
Ω
Ω
Guaranteed by design and characterization, not 100% tested in production. CL = 2pF with RS = 27 for Zo = 85 differential trace  
impedance).  
2 Measured from differential waveform  
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around  
differential 0V.  
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on  
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the  
oscilloscope is to use for the edge rate calculations.  
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising  
edge (i.e. Clock rising and Clock# falling).  
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross  
∆
absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.  
Electrical Characteristics–Current Consumption  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
IDDVDD  
CONDITIONS  
MIN TYP MAX  
UNITS  
mA  
NOTES  
Ω
Ω
Ω
All outputs @100MHz, CL = 2pF; Zo=85  
All outputs @100MHz, CL = 2pF; Zo=85  
All outputs @100MHz, CL = 2pF; Zo=85  
All differential pairs low/low  
13  
14  
35  
20  
100  
4
1
Operating Supply Current  
IDDVDDA/R  
IDDVDDIO  
mA  
1
86  
mA  
1
IDDVDDPD  
IDDVDDA/RPD  
IDDVDDIOPD  
0.7  
mA  
1,2  
1,2  
1,2  
Powerdown Current  
All differential pairs low/low  
5
mA  
All differential pairs low/low  
0.2  
mA  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 With input clock running. Stopping the input clock will result in lower numbers.  
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
7
9ZML1232  
REV E 112015  
9ZML1232  
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
Electrical Characteristics–Skew and Differential Jitter Parameters  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
tSPO_PLL  
CONDITIONS  
Input-to-Output Skew in PLL mode  
nominal value @ 25°C, 3.3V  
MIN TYP MAX  
-325 -225 -125  
UNITS  
ps  
NOTES  
CLK_IN, DIF[x:0]  
1,2,4,5,8  
Input-to-Output Skew in Bypass mode  
nominal value @ 25°C, 3.3V  
Input-to-Output Skew Varation in PLL mode  
across voltage and temperature  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
tPD_BYP  
3
3.8  
0
4.5  
50  
ns  
ps  
1,2,3,5,8  
1,2,3,5,8  
tDSPO_PLL  
-50  
Input-to-Output Skew Varation in Bypass mode  
across voltage and temperature  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
DIF{x:0]  
tDSPO_BYP  
-250  
250  
5
ps  
1,2,3,5,8  
1,2,3,5,8  
1,2,3,5,8  
1,2,3,8  
Random Differential Tracking error beween two  
9ZM devices in Hi BW Mode  
ps  
(rms)  
tDTE  
Random Differential Spread Spectrum Tracking  
error beween two 9ZM devices in Hi BW Mode  
tDSSTE  
75  
65  
ps  
Output-to-Output Skew across all outputs  
(Common to Bypass and PLL mode)  
LOBW#_BYPASS_HIBW = 1  
tSKEW_ALL  
40  
ps  
PLL Jitter Peaking  
PLL Jitter Peaking  
PLL Bandwidth  
PLL Bandwidth  
Duty Cycle  
jpeak-hibw  
jpeak-lobw  
pllHIBW  
pllLOBW  
tDC  
0
0
2.5  
2
dB  
dB  
7,8  
7,8  
8,9  
8,9  
1
LOBW#_BYPASS_HIBW = 0  
LOBW#_BYPASS_HIBW = 1  
LOBW#_BYPASS_HIBW = 0  
2
4
MHz  
MHz  
%
0.7  
45  
1.4  
55  
Measured differentially, PLL Mode  
Measured differentially, Bypass Mode  
@100MHz  
50.2  
0.8  
Duty Cycle Distortion  
Jitter, Cycle to cycle  
tDCD  
-2  
2
%
1,10  
PLL mode  
Additive Jitter in Bypass Mode  
10  
0.1  
50  
50  
ps  
ps  
1,11  
1,11  
tjcyc-cyc  
Notes for preceding table:  
1
Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.  
Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.  
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.  
2
3
4 This parameter is deterministic for a given device  
5
Measured with scope averaging on to find mean value.  
6. t is the period of the input clock  
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.  
8.  
Guaranteed by design and characterization, not 100% tested in production.  
9
Measured at 3 db down or half power point.  
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode  
11 Measured from differential waveform  
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
8
9ZML1232  
REV E 112015  
9ZML1232  
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
Electrical Characteristics–Phase Jitter Parameters  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions  
INDUSTRY  
PARAMETER  
SYMBOL  
tjphPCIeG1  
CONDITIONS  
MIN TYP MAX  
23 36 44  
0.84 1.18 1.41  
UNITS  
Notes  
1,2,3  
1,2  
LIMIT  
86  
PCIe Gen 1  
PCIe Gen 2 Lo Band  
10kHz < f < 1.5MHz  
ps (p-p)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
3
3.1  
1
tjphPCIeG2  
PCIe Gen 2 High Band  
1.5MHz < f < Nyquist (50MHz)  
PCIe Gen 3  
1.44  
0.37  
2.48  
0.59  
0.35  
0.28  
2.01  
0.49  
1,2  
1,2,4  
1,5  
tjphPCIeG3  
Phase Jitter, PLL Mode  
(PLL BW of 2-4MHz, CDR = 10MHz)  
QPI & SMI  
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)  
QPI & SMI  
0.20 0.25  
0.08 0.16  
0.07 0.12  
0.5  
0.3  
tjphQPI_SMI  
1,5  
(100MHz, 8.0Gb/s, 12UI)  
QPI & SMI  
(100MHz, 9.6Gb/s, 12UI)  
0.19  
10  
0.2  
N/A  
N/A  
1,5  
(rms)  
tjphPCIeG1  
PCIe Gen 1  
PCIe Gen 2 Lo Band  
10kHz < f < 1.5MHz  
0
3
ps (p-p)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
1,2,3  
1,2,6  
0.09 0.13 0.30  
tjphPCIeG2  
PCIe Gen 2 High Band  
1.5MHz < f < Nyquist (50MHz)  
PCIe Gen 3  
0.00  
0.00  
0.10 0.70  
N/A  
1,2,6  
1,2,4,6  
1,5,6  
0.30  
N/A  
AdditivePhase Jitter,  
tjphPCIeG3  
0.10  
(PLL BW of 2-4MHz, CDR = 10MHz)  
QPI & SMI  
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)  
QPI & SMI  
Bypass mode  
0.00 0.10  
0.04 0.05  
0.04 0.05  
0.30  
0.10  
0.10  
N/A  
N/A  
N/A  
tjphQPI_SMI  
1,5,6  
(100MHz, 8.0Gb/s, 12UI)  
QPI & SMI  
(100MHz, 9.6Gb/s, 12UI)  
1,5,6  
(rms)  
1 Applies to all outputs.  
2 See http://www.pcisig.com for complete specs  
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.  
4 Subject to final ratification by PCI SIG.  
5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.3  
6 For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)^2 = (total jittter)^2 - (input jitter)^2  
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
9
9ZML1232  
REV E 112015  
9ZML1232  
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
Clock Periods–Differential Outputs with Spread Spectrum Disabled  
Measurement Window  
1 Clock  
1us  
-SSC  
0.1s  
- ppm  
0.1s  
0.1s  
+ ppm  
Long-Term  
Average  
Max  
1us  
+SSC  
Short-Term  
Average  
Max  
1 Clock  
Center  
Freq.  
MHz  
SSC OFF  
-c2c jitter  
AbsPer  
Min  
0 ppm  
Period  
Nominal  
+c2c jitter Units Notes  
AbsPer  
Max  
Short-Term Long-Term  
Average  
Min  
Average  
Min  
DIF  
100.00  
9.94900  
9.99900  
10.00000  
10.00100  
10.05100  
ns  
1,2,3  
Clock Periods–Differential Outputs with Spread Spectrum Enabled  
Measurement Window  
1 Clock  
1us  
-SSC  
0.1s  
- ppm  
0.1s  
0.1s  
+ ppm  
Long-Term  
Average  
Max  
1us  
+SSC  
Short-Term  
Average  
Max  
1 Clock  
Center  
Freq.  
MHz  
SSC ON  
Units Notes  
-c2c jitter  
AbsPer  
Min  
0 ppm  
Period  
Nominal  
+c2c jitter  
AbsPer  
Max  
Short-Term Long-Term  
Average  
Min  
Average  
Min  
DIF  
99.75  
9.94906  
9.99906  
10.02406  
10.02506  
10.02607  
10.05107  
10.10107  
ns  
1,2,3  
Notes:  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ accuracy  
requirements (+/-100ppm). The 9ZML1232 itself does not contribute to ppm error.  
3
Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode  
4
Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode  
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
10  
9ZML1232  
REV E 112015  
9ZML1232  
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
DIF Reference Clock  
Common Recommendations for Differential Routing  
Dimension or Value  
0.5 max  
0.2 max  
0.2 max  
33  
Unit Figure  
L1 length, route as non-coupled 50ohm trace  
L2 length, route as non-coupled 50ohm trace  
L3 length, route as non-coupled 50ohm trace  
Rs (100 ohm differential traces)  
inch  
inch  
inch  
ohm  
ohm  
1
1
1
1
1
Rs (85 ohm differential traces)  
27  
Down Device Differential Routing  
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max  
inch  
inch  
1
1
L4 length, route as coupled stripline 100ohm differential trace  
1.8 min to 14.4 max  
Differential Routing to PCI Express Connector  
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max  
inch  
inch  
2
2
L4 length, route as coupled stripline 100ohm differential trace  
0.225 min to 12.6 max  
Figure 1: Down Device Routing  
L2  
L1  
Rs  
Rs  
L4  
L4'  
L2'  
L1'  
LP-HCSL  
Output  
PCI Express  
Down Device  
REF_CLK Input  
Figure 2: PCI Express Connector Routing  
L2  
L1  
Rs  
L4  
L4'  
L2'  
L1'  
Rs  
LP-HCSL  
PCI Express  
Add-in Board  
REF_CLK Input  
Output  
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
11  
9ZML1232  
REV E 112015  
9ZML1232  
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
Cable Connected AC Coupled Application (Figure 3)  
Component  
R5a, R5b  
R6a, R6b  
Cc  
Value  
8.2K 5%  
1K 5%  
Note  
0.1 µF  
Vcm  
0.350 volts  
Figure 3  
L2  
L1  
R3  
R4  
R1a  
L4  
L4'  
L2'  
L1'  
R1b  
R2a  
R2b  
HCSL Output Buffer  
Down Device  
REF_CLK Input  
L3'  
L3  
Figure 4  
3.3 Volts  
R5a  
R5b  
Cc  
Cc  
L4  
L4'  
R6a  
R6b  
PCIe Device  
REF_CLK Input  
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
12  
9ZML1232  
REV E 112015  
9ZML1232  
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
General SMBus Serial Interface Information for 9ZML1232  
How to Write  
How to Read  
• Controller (host) sends a start bit  
• Controller (host) sends the write address  
• IDT clock will acknowledge  
• Controller (host) will send a start bit  
• Controller (host) sends the write address  
• IDT clock will acknowledge  
• Controller (host) sends the beginning byte location = N  
• IDT clock will acknowledge  
• Controller (host) sends the beginning byte location = N  
• IDT clock will acknowledge  
• Controller (host) sends the byte count = X  
• IDT clock will acknowledge  
• Controller (host) will send a separate start bit  
• Controller (host) sends the read address  
• IDT clock will acknowledge  
• IDT clock will send the data byte count = X  
• IDT clock sends Byte N+X-1  
• Controller (host) starts sending Byte N through Byte  
N+X-1  
• IDT clock will acknowledge each byte one at a time  
• Controller (host) sends a Stop bit  
• IDT clock sends Byte 0 through Byte X (if X was  
(H)  
written to Byte 8)  
• Controller (host) will need to acknowledge each byte  
• Controller (host) will send a not acknowledge bit  
• Controller (host) will send a stop bit  
Index Block Write Operation  
Controller (Host)  
starT bit  
Slave Address  
WR WRite  
IDT (Slave/Receiver)  
T
Index Block Read Operation  
Controller (Host)  
starT bit  
IDT (Slave/Receiver)  
T
ACK  
ACK  
ACK  
ACK  
Slave Address  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
WR  
WRite  
ACK  
ACK  
Beginning Byte = N  
RT  
Repeat starT  
Slave Address  
ReaD  
O
O
O
RD  
O
O
O
ACK  
Data Byte Count=X  
Beginning Byte N  
Byte N + X - 1  
ACK  
ACK  
ACK  
P
stoP bit  
O
O
O
9ZML1232 SMBus Addressing  
O
O
O
SMB_A(1:0)_tri  
SMBus Address (Rd/Wrt bit = 0)  
00  
0M  
01  
M0  
MM  
M1  
10  
D8  
DA  
DE  
C2  
C4  
C6  
CA  
CC  
CE  
Byte N + X - 1  
N
P
Not acknowledge  
stoP bit  
1M  
11  
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
13  
9ZML1232  
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9ZML1232  
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
SMBusTable: PLL Mode, and Frequency Select Register  
Byte 0  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Pin #  
4
4
3
Name  
Control Function  
PLL Operating Mode Rd back 1  
PLL Operating Mode Rd back 0  
Input Select Readback  
Reserved  
Type  
R
R
0
1
Default  
Latch  
Latch  
Latch  
0
PLL Mode 1  
PLL Mode 0  
SEL_A_B#  
See PLL Operating Mode  
Readback Table  
DIF_INA  
DIF_INB  
R
Enable S/W control of PLL BW and  
Software_EN  
RW  
HW Latch  
SMBus Control  
0
Bit 3  
Input Select  
PLL Mode 1  
PLL Mode 0  
SEL_A_B#  
PLL Operating Mode 1  
PLL Operating Mode 1  
Input Select  
RW  
RW  
RW  
See PLL Operating Mode  
Readback Table  
1
1
1
Bit 2  
Bit 1  
Bit 0  
DIF_INB  
DIF_INA  
Setting bit 3 to '1' allows the user to overide the Latch value from pins 4 and 5 via use of bits [2:0]. Use the values from the PLL  
Note:  
Operating Mode Readback Table. Note that Bits [7:5] will keep the value originally latched on pins 4 and 5. A warm reset of the system will  
have to accomplished if the user changes Bits [2:0] bits.  
SMBusTable: Output Control Register  
Byte 1  
Bit 7  
Pin #  
49/50  
Name  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
DIF_7_En  
DIF_6_En  
DIF_5_En  
DIF_4_En  
DIF_3_En  
DIF_2_En  
DIF_1_En  
DIF_0_En  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
1
1
1
1
1
1
1
1
47/48  
43/44  
41/42  
31/32  
29/30  
25/26  
23/24  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Low/Low  
Enable  
SMBusTable: Output Control Register  
Byte 2  
Bit 7  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
1
1
1
1
Reserved  
Reserved  
Reserved  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
67/68  
DIF_11_En  
DIF_10_En  
DIF_9_En  
DIF_8_En  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
RW  
RW  
RW  
RW  
65/66  
61/62  
59/60  
Low/Low  
Enable  
SMBusTable: Output Amplitude Control Register  
Byte 3  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
000=350mV, 001=450mV,  
010=550mV, 011=650mV,  
100=750mV 101=850mV,  
110=950mV, 111=Reserved  
AMP2  
AMP1  
AMP0  
RW  
RW  
RW  
1
0
0
Bit 2  
Bit 1  
Bit 0  
Output Amplitude  
SMBusTable: Reserved Register  
Byte 4 Pin # Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
14  
9ZML1232  
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9ZML1232  
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
SMBusTable: Vendor & Revision ID Register  
Byte 5  
Bit 7  
Pin #  
-
Name  
RID3  
RID2  
RID1  
RID0  
VID3  
VID2  
VID1  
VID0  
Control Function  
Type  
R
R
R
R
R
R
R
R
0
1
Default  
X
X
X
X
0
0
0
1
A rev = 0000  
B rev = 0001  
-
-
-
-
-
-
-
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
REVISION ID  
-
-
-
-
-
-
-
-
VENDOR ID  
SMBusTable: DEVICE ID  
Byte 6 Pin #  
Bit 7  
Name  
Control Function  
Device ID 7 (MSB)  
Type  
R
R
R
R
R
R
R
R
0
1
Default  
-
1
1
1
1
0
0
0
1
-
-
-
-
-
-
-
Device ID 6  
Device ID 5  
Device ID 4  
Device ID 3  
Device ID 2  
Device ID 1  
Device ID 0  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
9ZML1231 = F1 hex  
SMBusTable: Byte Count Register  
Byte 7  
Bit 7  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
1
0
0
0
Reserved  
Reserved  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
-
BC4  
BC3  
BC2  
BC1  
BC0  
RW  
RW  
RW  
RW  
RW  
Default value is 8 hex, so 9  
bytes (0 to 8) will be read back  
by default.  
-
-
-
-
Writing to this register configures how  
many bytes will be read back.  
SMBusTable: Reserved Register  
Byte 8 Pin # Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
15  
9ZML1232  
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9ZML1232  
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
Marking Diagram  
ICS  
9ZML1232BKL  
LOT  
COO YYWW  
Notes:  
1. “L” denotes RoHS compliant package.  
2. ‘LOT’ denotes the lot number.  
3. “COO”: country of origin.  
4. YYWW is the last two digits of the year and week that the part was assembled.  
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
16  
9ZML1232  
REV E 112015  
9ZML1232  
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
Package Outline and Package Dimensions (72-pin MLF)  
(Ref)  
ND & NE  
Even  
Seating Plane  
(ND-1)x  
(Ref)  
e
A1  
Index Area  
(Typ)  
If ND & NE  
are Even  
L
A3  
e
2
N
1
2
N
Anvil  
Singulation  
1
2
(NE-1)x  
(Ref)  
e
-- or --  
E2  
E
E2  
2
Sawn  
Singulation  
Top View  
b
A
C
(Ref)  
ND & NE  
Odd  
e
Thermal Base  
D
D2  
2
C
D2  
0.08  
Millimeters  
Symbol  
Min  
Max  
1.0  
A
A1  
0.8  
0
0.05  
A3  
b
0.25 Reference  
0.18 0.3  
e
0.50 BASIC  
D x E BASIC  
D2 MIN./MAX.  
E2 MIN./MAX.  
L MIN./MAX.  
N
10.00 x 10.00  
5.75  
5.75  
0.30  
6.15  
6.15  
0.50  
72  
18  
18  
N
N
D
E
Ordering Information  
Part Number  
9ZML1232BKLF  
9ZML1232BKLFT  
Shipping Package  
Package  
72-pin QFN  
72-pin QFN  
Temperature  
0 to +70°C  
0 to +70°C  
Trays  
Tape and Reel  
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
“B” is the device revision designator (will not correlate with the datasheet revision).  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes  
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No  
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications  
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not  
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT  
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
17  
9ZML1232  
REV E 112015  
9ZML1232  
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
Revision History  
Rev. Issuer Issue Date Description  
Page #  
A
B
C
RDW  
RDW  
RDW  
RDW  
8/17/2012 Updated electrical characteristics and move to final.  
10/2/2012 Corrected Phase Jitter Parameters  
9
14  
3/24/2014  
1. Corrected pin references in Byte 0, bits (7:5) from 4 and 5 to 3 and 4.  
D
9/16/2015 Corrected typo in general description; changed DB1900Z to DB1200ZL  
1
1. Updated QPI references to QPI/UPI  
11/20/2015  
E
RDW  
1,5  
2. Updated DIF_IN table to match PCI SIG specification, no silicon change  
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
18  
9ZML1232  
REV E 112015  
9ZML1232  
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI  
SYNTHESIZERS  
Innovate with IDT and accelerate your future networks. Contact:  
www.IDT.com  
For Sales  
800-345-7015  
408-284-8200  
Fax: 408-284-2775  
For Tech Support  
www.idt.com/go/clockhelp  
pcclockhelp@idt.com  
Corporate Headquarters  
Integrated Device Technology, Inc.  
www.idt.com  
© 2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated  
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or  
registered trademarks used to identify products or services of their respective owners.  
Printed in USA  
厂商 型号 描述 页数 下载

IDT

 		9ZML1232 [ 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI ] 19 页

IDT

 		9ZML1232BKLF [ 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI ] 19 页

IDT

 		9ZML1232E [ 2:12 DB1200ZL Derivative for PCIe Gen1–4 and UPI ] 19 页

IDT

 		9ZML1232EKILF [ 2:12 DB1200ZL Derivative for PCIe Gen1–4 and UPI ] 19 页

IDT

 		9ZML1232EKILFT [ 2:12 DB1200ZL Derivative for PCIe Gen1–4 and UPI ] 19 页

IDT

 		9ZML1233E [ 2:12 DB1200ZL Derivative for PCIe Gen1-4 ] 24 页

IDT

 		9ZML1233EKILF [ 2:12 DB1200ZL Derivative for PCIe Gen1-4 ] 24 页

IDT

 		9ZML1233EKILFT [ 2:12 DB1200ZL Derivative for PCIe Gen1-4 ] 24 页

IDT

 		9ZML1252E [ 2:12 DB1200ZL Derivative for PCIe Gen1–4 and UPI ] 19 页

IDT

 		9ZML1252EKILF [ 2:12 DB1200ZL Derivative for PCIe Gen1–4 and UPI ] 19 页

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